2015-01-31 19:17:59 +08:00
|
|
|
//===-- AArch64TargetTransformInfo.h - AArch64 specific TTI -----*- C++ -*-===//
|
|
|
|
//
|
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
// License. See LICENSE.TXT for details.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// \file
|
|
|
|
/// This file a TargetTransformInfo::Concept conforming object specific to the
|
|
|
|
/// AArch64 target machine. It uses the target's detailed information to
|
|
|
|
/// provide more precise answers to certain TTI queries, while letting the
|
|
|
|
/// target independent and default TTI implementations handle the rest.
|
|
|
|
///
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
|
|
|
|
#define LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
|
|
|
|
|
|
|
|
#include "AArch64.h"
|
|
|
|
#include "AArch64TargetMachine.h"
|
|
|
|
#include "llvm/Analysis/TargetTransformInfo.h"
|
|
|
|
#include "llvm/CodeGen/BasicTTIImpl.h"
|
|
|
|
#include "llvm/Target/TargetLowering.h"
|
|
|
|
#include <algorithm>
|
|
|
|
|
|
|
|
namespace llvm {
|
|
|
|
|
|
|
|
class AArch64TTIImpl : public BasicTTIImplBase<AArch64TTIImpl> {
|
|
|
|
typedef BasicTTIImplBase<AArch64TTIImpl> BaseT;
|
|
|
|
typedef TargetTransformInfo TTI;
|
2015-02-01 22:01:15 +08:00
|
|
|
friend BaseT;
|
2015-01-31 19:17:59 +08:00
|
|
|
|
|
|
|
const AArch64Subtarget *ST;
|
|
|
|
const AArch64TargetLowering *TLI;
|
|
|
|
|
2015-02-01 22:22:17 +08:00
|
|
|
const AArch64Subtarget *getST() const { return ST; }
|
2015-02-01 22:01:15 +08:00
|
|
|
const AArch64TargetLowering *getTLI() const { return TLI; }
|
|
|
|
|
2015-01-31 19:17:59 +08:00
|
|
|
enum MemIntrinsicType {
|
|
|
|
VECTOR_LDST_TWO_ELEMENTS,
|
|
|
|
VECTOR_LDST_THREE_ELEMENTS,
|
|
|
|
VECTOR_LDST_FOUR_ELEMENTS
|
|
|
|
};
|
|
|
|
|
2017-05-10 04:18:12 +08:00
|
|
|
bool isWideningInstruction(Type *Ty, unsigned Opcode,
|
|
|
|
ArrayRef<const Value *> Args);
|
|
|
|
|
2015-01-31 19:17:59 +08:00
|
|
|
public:
|
2015-09-17 07:38:13 +08:00
|
|
|
explicit AArch64TTIImpl(const AArch64TargetMachine *TM, const Function &F)
|
2015-07-09 10:08:42 +08:00
|
|
|
: BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
|
2015-02-01 22:01:15 +08:00
|
|
|
TLI(ST->getTargetLowering()) {}
|
2015-01-31 19:17:59 +08:00
|
|
|
|
|
|
|
/// \name Scalar TTI Implementations
|
|
|
|
/// @{
|
|
|
|
|
|
|
|
using BaseT::getIntImmCost;
|
2015-08-06 02:08:10 +08:00
|
|
|
int getIntImmCost(int64_t Val);
|
|
|
|
int getIntImmCost(const APInt &Imm, Type *Ty);
|
|
|
|
int getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty);
|
|
|
|
int getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
|
|
|
|
Type *Ty);
|
2015-01-31 19:17:59 +08:00
|
|
|
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth);
|
|
|
|
|
|
|
|
/// @}
|
|
|
|
|
|
|
|
/// \name Vector TTI Implementations
|
|
|
|
/// @{
|
|
|
|
|
2015-09-01 19:26:46 +08:00
|
|
|
bool enableInterleavedAccessVectorization() { return true; }
|
|
|
|
|
2015-01-31 19:17:59 +08:00
|
|
|
unsigned getNumberOfRegisters(bool Vector) {
|
|
|
|
if (Vector) {
|
|
|
|
if (ST->hasNEON())
|
|
|
|
return 32;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
return 31;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned getRegisterBitWidth(bool Vector) {
|
|
|
|
if (Vector) {
|
|
|
|
if (ST->hasNEON())
|
|
|
|
return 128;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
return 64;
|
|
|
|
}
|
|
|
|
|
2017-05-16 05:15:01 +08:00
|
|
|
unsigned getMinVectorRegisterBitWidth() {
|
|
|
|
return ST->getMinVectorRegisterBitWidth();
|
|
|
|
}
|
|
|
|
|
2015-05-07 01:12:25 +08:00
|
|
|
unsigned getMaxInterleaveFactor(unsigned VF);
|
2015-01-31 19:17:59 +08:00
|
|
|
|
2017-04-12 19:49:08 +08:00
|
|
|
int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
|
|
|
|
const Instruction *I = nullptr);
|
2015-01-31 19:17:59 +08:00
|
|
|
|
2016-04-27 23:20:21 +08:00
|
|
|
int getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy,
|
|
|
|
unsigned Index);
|
|
|
|
|
2015-08-06 02:08:10 +08:00
|
|
|
int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
|
2015-01-31 19:17:59 +08:00
|
|
|
|
2015-08-06 02:08:10 +08:00
|
|
|
int getArithmeticInstrCost(
|
2015-01-31 19:17:59 +08:00
|
|
|
unsigned Opcode, Type *Ty,
|
|
|
|
TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
|
|
|
|
TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
|
|
|
|
TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
|
[X86] updating TTI costs for arithmetic instructions on X86\SLM arch.
updated instructions:
pmulld, pmullw, pmulhw, mulsd, mulps, mulpd, divss, divps, divsd, divpd, addpd and subpd.
special optimization case which replaces pmulld with pmullw\pmulhw\pshuf seq.
In case if the real operands bitwidth <= 16.
Differential Revision: https://reviews.llvm.org/D28104
llvm-svn: 291657
2017-01-11 16:23:37 +08:00
|
|
|
TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None,
|
|
|
|
ArrayRef<const Value *> Args = ArrayRef<const Value *>());
|
2015-01-31 19:17:59 +08:00
|
|
|
|
2017-01-05 22:03:41 +08:00
|
|
|
int getAddressComputationCost(Type *Ty, ScalarEvolution *SE, const SCEV *Ptr);
|
2015-01-31 19:17:59 +08:00
|
|
|
|
2017-04-12 19:49:08 +08:00
|
|
|
int getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
|
|
|
|
const Instruction *I = nullptr);
|
2015-01-31 19:17:59 +08:00
|
|
|
|
2015-08-06 02:08:10 +08:00
|
|
|
int getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
|
2017-04-12 19:49:08 +08:00
|
|
|
unsigned AddressSpace, const Instruction *I = nullptr);
|
2015-01-31 19:17:59 +08:00
|
|
|
|
2015-08-06 02:08:10 +08:00
|
|
|
int getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys);
|
2015-01-31 19:17:59 +08:00
|
|
|
|
2015-02-01 22:31:23 +08:00
|
|
|
void getUnrollingPreferences(Loop *L, TTI::UnrollingPreferences &UP);
|
2015-01-31 19:17:59 +08:00
|
|
|
|
|
|
|
Value *getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst,
|
|
|
|
Type *ExpectedType);
|
|
|
|
|
|
|
|
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info);
|
|
|
|
|
2015-08-06 02:08:10 +08:00
|
|
|
int getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor,
|
|
|
|
ArrayRef<unsigned> Indices, unsigned Alignment,
|
|
|
|
unsigned AddressSpace);
|
2016-03-18 08:27:29 +08:00
|
|
|
|
2017-04-04 03:20:07 +08:00
|
|
|
bool
|
|
|
|
shouldConsiderAddressTypePromotion(const Instruction &I,
|
|
|
|
bool &AllowPromotionWithoutCommonHeader);
|
|
|
|
|
2016-03-18 08:27:29 +08:00
|
|
|
unsigned getCacheLineSize();
|
|
|
|
|
|
|
|
unsigned getPrefetchDistance();
|
2016-03-18 08:27:38 +08:00
|
|
|
|
|
|
|
unsigned getMinPrefetchStride();
|
2016-03-18 08:27:43 +08:00
|
|
|
|
|
|
|
unsigned getMaxPrefetchIterationsAhead();
|
2017-05-10 17:42:49 +08:00
|
|
|
|
|
|
|
bool shouldExpandReduction(const IntrinsicInst *II) const {
|
|
|
|
return false;
|
|
|
|
}
|
2015-01-31 19:17:59 +08:00
|
|
|
/// @}
|
|
|
|
};
|
|
|
|
|
|
|
|
} // end namespace llvm
|
|
|
|
|
|
|
|
#endif
|