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llvm-project/llvm/test/CodeGen/X86/memset-nonzero.ll

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[x86] regenerate checks with update_llc_test_checks.py The dream of a unified check-line auto-generator for all phases of compilation is dead. The llc script has already diverged to be better at its goal, so having 2 scripts that do almost the same thing is just causing confusion. We can rip out the llc ability in update_test_checks.py next and rename it, so it will be clear that we have one script for llc check auto-generation and another for opt. llvm-svn: 305206
2017-06-13 01:31:36 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[x86] add an SSE2 + fast-unaligned accesses run for memset nonzero tests Was there really no other way to splat a byte in SSE2? punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] llvm-svn: 265172
2016-04-02 02:29:25 +08:00
; RUN: llc -mtriple=x86_64-unknown-unknown < %s -mattr=sse | FileCheck %s --check-prefix=SSE
; RUN: llc -mtriple=x86_64-unknown-unknown < %s -mattr=sse2 | FileCheck %s --check-prefix=SSE
; RUN: llc -mtriple=x86_64-unknown-unknown < %s -mattr=sse2,-slow-unaligned-mem-16 | FileCheck %s --check-prefix=SSE2FAST
; RUN: llc -mtriple=x86_64-unknown-unknown < %s -mattr=avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
; RUN: llc -mtriple=x86_64-unknown-unknown < %s -mattr=avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2
[x86] add tests to show current memset codegen llvm-svn: 264748
2016-03-30 01:09:27 +08:00
[x86] add memset tests to show another potential improvement llvm-svn: 265048
2016-04-01 04:40:32 +08:00
; https://llvm.org/bugs/show_bug.cgi?id=27100
[x86] add tests to show current memset codegen llvm-svn: 264748
2016-03-30 01:09:27 +08:00
define void @memset_16_nonzero_bytes(i8* %x) {
[x86] add an SSE1 run for these tests Note however that this is identical to the existing SSE2 run. What we really want is yet another run for an SSE2 machine that also has fast unaligned 16-byte accesses. llvm-svn: 265167
2016-04-02 02:11:30 +08:00
; SSE-LABEL: memset_16_nonzero_bytes:
[x86] regenerate checks utils/update_test_checks.py was improved with: http://reviews.llvm.org/rL265414 to include the first line of the function (expected to be a comment line). This ensures that nothing bad has happened before the first actual line of checked asm. It also matches the existing behavior of the old script. llvm-svn: 265416
2016-04-06 01:12:19 +08:00
; SSE: # BB#0:
; SSE-NEXT: movabsq $3038287259199220266, %rax # imm = 0x2A2A2A2A2A2A2A2A
[x86] add an SSE1 run for these tests Note however that this is identical to the existing SSE2 run. What we really want is yet another run for an SSE2 machine that also has fast unaligned 16-byte accesses. llvm-svn: 265167
2016-04-02 02:11:30 +08:00
; SSE-NEXT: movq %rax, 8(%rdi)
; SSE-NEXT: movq %rax, (%rdi)
; SSE-NEXT: retq
[x86] use SSE/AVX ops for non-zero memsets (PR27100) Move the memset check down to the CPU-with-slow-SSE-unaligned-memops case: this allows fast targets to take advantage of SSE/AVX instructions and prevents slow targets from stepping into a codegen sinkhole while trying to splat a byte into an XMM reg. Follow-on bugs exposed by the current codegen are: https://llvm.org/bugs/show_bug.cgi?id=27141 https://llvm.org/bugs/show_bug.cgi?id=27143 Differential Revision: http://reviews.llvm.org/D18566 llvm-svn: 265029
2016-04-01 01:30:06 +08:00
;
[x86] add an SSE2 + fast-unaligned accesses run for memset nonzero tests Was there really no other way to splat a byte in SSE2? punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] llvm-svn: 265172
2016-04-02 02:29:25 +08:00
; SSE2FAST-LABEL: memset_16_nonzero_bytes:
[x86] regenerate checks utils/update_test_checks.py was improved with: http://reviews.llvm.org/rL265414 to include the first line of the function (expected to be a comment line). This ensures that nothing bad has happened before the first actual line of checked asm. It also matches the existing behavior of the old script. llvm-svn: 265416
2016-04-06 01:12:19 +08:00
; SSE2FAST: # BB#0:
; SSE2FAST-NEXT: movaps {{.*#+}} xmm0 = [42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42]
[x86] add an SSE2 + fast-unaligned accesses run for memset nonzero tests Was there really no other way to splat a byte in SSE2? punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] llvm-svn: 265172
2016-04-02 02:29:25 +08:00
; SSE2FAST-NEXT: movups %xmm0, (%rdi)
; SSE2FAST-NEXT: retq
;
[x86] avoid intermediate splat for non-zero memsets (PR27100) Follow-up to http://reviews.llvm.org/D18566 and http://reviews.llvm.org/D18676 - where we noticed that an intermediate splat was being generated for memsets of non-zero chars. That was because we told getMemsetStores() to use a 32-bit vector element type, and it happily obliged by producing that constant using an integer multiply. The 16-byte test that was added in D18566 is now equivalent for AVX1 and AVX2 (no splats, just a vector load), but we have PR27141 to track that splat difference. Note that the SSE1 path is not changed in this patch. That can be a follow-up. This patch should resolve PR27100. llvm-svn: 265161
2016-04-02 01:36:45 +08:00
; AVX-LABEL: memset_16_nonzero_bytes:
[x86] regenerate checks utils/update_test_checks.py was improved with: http://reviews.llvm.org/rL265414 to include the first line of the function (expected to be a comment line). This ensures that nothing bad has happened before the first actual line of checked asm. It also matches the existing behavior of the old script. llvm-svn: 265416
2016-04-06 01:12:19 +08:00
; AVX: # BB#0:
; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42]
[x86] avoid intermediate splat for non-zero memsets (PR27100) Follow-up to http://reviews.llvm.org/D18566 and http://reviews.llvm.org/D18676 - where we noticed that an intermediate splat was being generated for memsets of non-zero chars. That was because we told getMemsetStores() to use a 32-bit vector element type, and it happily obliged by producing that constant using an integer multiply. The 16-byte test that was added in D18566 is now equivalent for AVX1 and AVX2 (no splats, just a vector load), but we have PR27141 to track that splat difference. Note that the SSE1 path is not changed in this patch. That can be a follow-up. This patch should resolve PR27100. llvm-svn: 265161
2016-04-02 01:36:45 +08:00
; AVX-NEXT: vmovups %xmm0, (%rdi)
; AVX-NEXT: retq
[x86] add tests to show current memset codegen llvm-svn: 264748
2016-03-30 01:09:27 +08:00
%call = tail call i8* @__memset_chk(i8* %x, i32 42, i64 16, i64 -1)
ret void
}
define void @memset_32_nonzero_bytes(i8* %x) {
[x86] add an SSE1 run for these tests Note however that this is identical to the existing SSE2 run. What we really want is yet another run for an SSE2 machine that also has fast unaligned 16-byte accesses. llvm-svn: 265167
2016-04-02 02:11:30 +08:00
; SSE-LABEL: memset_32_nonzero_bytes:
[x86] regenerate checks utils/update_test_checks.py was improved with: http://reviews.llvm.org/rL265414 to include the first line of the function (expected to be a comment line). This ensures that nothing bad has happened before the first actual line of checked asm. It also matches the existing behavior of the old script. llvm-svn: 265416
2016-04-06 01:12:19 +08:00
; SSE: # BB#0:
; SSE-NEXT: movabsq $3038287259199220266, %rax # imm = 0x2A2A2A2A2A2A2A2A
[x86] add an SSE1 run for these tests Note however that this is identical to the existing SSE2 run. What we really want is yet another run for an SSE2 machine that also has fast unaligned 16-byte accesses. llvm-svn: 265167
2016-04-02 02:11:30 +08:00
; SSE-NEXT: movq %rax, 24(%rdi)
; SSE-NEXT: movq %rax, 16(%rdi)
; SSE-NEXT: movq %rax, 8(%rdi)
; SSE-NEXT: movq %rax, (%rdi)
; SSE-NEXT: retq
[x86] use SSE/AVX ops for non-zero memsets (PR27100) Move the memset check down to the CPU-with-slow-SSE-unaligned-memops case: this allows fast targets to take advantage of SSE/AVX instructions and prevents slow targets from stepping into a codegen sinkhole while trying to splat a byte into an XMM reg. Follow-on bugs exposed by the current codegen are: https://llvm.org/bugs/show_bug.cgi?id=27141 https://llvm.org/bugs/show_bug.cgi?id=27143 Differential Revision: http://reviews.llvm.org/D18566 llvm-svn: 265029
2016-04-01 01:30:06 +08:00
;
[x86] add an SSE2 + fast-unaligned accesses run for memset nonzero tests Was there really no other way to splat a byte in SSE2? punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] llvm-svn: 265172
2016-04-02 02:29:25 +08:00
; SSE2FAST-LABEL: memset_32_nonzero_bytes:
[x86] regenerate checks utils/update_test_checks.py was improved with: http://reviews.llvm.org/rL265414 to include the first line of the function (expected to be a comment line). This ensures that nothing bad has happened before the first actual line of checked asm. It also matches the existing behavior of the old script. llvm-svn: 265416
2016-04-06 01:12:19 +08:00
; SSE2FAST: # BB#0:
; SSE2FAST-NEXT: movaps {{.*#+}} xmm0 = [42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42]
[x86] add an SSE2 + fast-unaligned accesses run for memset nonzero tests Was there really no other way to splat a byte in SSE2? punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] llvm-svn: 265172
2016-04-02 02:29:25 +08:00
; SSE2FAST-NEXT: movups %xmm0, 16(%rdi)
; SSE2FAST-NEXT: movups %xmm0, (%rdi)
; SSE2FAST-NEXT: retq
;
[x86] avoid intermediate splat for non-zero memsets (PR27100) Follow-up to D18566 - where we noticed that an intermediate splat was being generated for memsets of non-zero chars. That was because we told getMemsetStores() to use a 32-bit vector element type, and it happily obliged by producing that constant using an integer multiply. The tests that were added in the last patch are now equivalent for AVX1 and AVX2 (no splats, just a vector load), but we have PR27141 to track that splat difference. In the new tests, the splat via shuffling looks ok to me, but there might be some room for improvement depending on uarch there. Note that the SSE1/2 paths are not changed in this patch. That can be a follow-up. This patch should resolve PR27100. Differential Revision: http://reviews.llvm.org/D18676 llvm-svn: 265148
2016-04-02 00:27:14 +08:00
; AVX-LABEL: memset_32_nonzero_bytes:
[x86] regenerate checks utils/update_test_checks.py was improved with: http://reviews.llvm.org/rL265414 to include the first line of the function (expected to be a comment line). This ensures that nothing bad has happened before the first actual line of checked asm. It also matches the existing behavior of the old script. llvm-svn: 265416
2016-04-06 01:12:19 +08:00
; AVX: # BB#0:
; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42]
[x86] avoid intermediate splat for non-zero memsets (PR27100) Follow-up to D18566 - where we noticed that an intermediate splat was being generated for memsets of non-zero chars. That was because we told getMemsetStores() to use a 32-bit vector element type, and it happily obliged by producing that constant using an integer multiply. The tests that were added in the last patch are now equivalent for AVX1 and AVX2 (no splats, just a vector load), but we have PR27141 to track that splat difference. In the new tests, the splat via shuffling looks ok to me, but there might be some room for improvement depending on uarch there. Note that the SSE1/2 paths are not changed in this patch. That can be a follow-up. This patch should resolve PR27100. Differential Revision: http://reviews.llvm.org/D18676 llvm-svn: 265148
2016-04-02 00:27:14 +08:00
; AVX-NEXT: vmovups %ymm0, (%rdi)
; AVX-NEXT: vzeroupper
; AVX-NEXT: retq
[x86] add tests to show current memset codegen llvm-svn: 264748
2016-03-30 01:09:27 +08:00
%call = tail call i8* @__memset_chk(i8* %x, i32 42, i64 32, i64 -1)
ret void
}
define void @memset_64_nonzero_bytes(i8* %x) {
[x86] add an SSE1 run for these tests Note however that this is identical to the existing SSE2 run. What we really want is yet another run for an SSE2 machine that also has fast unaligned 16-byte accesses. llvm-svn: 265167
2016-04-02 02:11:30 +08:00
; SSE-LABEL: memset_64_nonzero_bytes:
[x86] regenerate checks utils/update_test_checks.py was improved with: http://reviews.llvm.org/rL265414 to include the first line of the function (expected to be a comment line). This ensures that nothing bad has happened before the first actual line of checked asm. It also matches the existing behavior of the old script. llvm-svn: 265416
2016-04-06 01:12:19 +08:00
; SSE: # BB#0:
; SSE-NEXT: movabsq $3038287259199220266, %rax # imm = 0x2A2A2A2A2A2A2A2A
[x86] add an SSE1 run for these tests Note however that this is identical to the existing SSE2 run. What we really want is yet another run for an SSE2 machine that also has fast unaligned 16-byte accesses. llvm-svn: 265167
2016-04-02 02:11:30 +08:00
; SSE-NEXT: movq %rax, 56(%rdi)
; SSE-NEXT: movq %rax, 48(%rdi)
; SSE-NEXT: movq %rax, 40(%rdi)
; SSE-NEXT: movq %rax, 32(%rdi)
; SSE-NEXT: movq %rax, 24(%rdi)
; SSE-NEXT: movq %rax, 16(%rdi)
; SSE-NEXT: movq %rax, 8(%rdi)
; SSE-NEXT: movq %rax, (%rdi)
; SSE-NEXT: retq
[x86] use SSE/AVX ops for non-zero memsets (PR27100) Move the memset check down to the CPU-with-slow-SSE-unaligned-memops case: this allows fast targets to take advantage of SSE/AVX instructions and prevents slow targets from stepping into a codegen sinkhole while trying to splat a byte into an XMM reg. Follow-on bugs exposed by the current codegen are: https://llvm.org/bugs/show_bug.cgi?id=27141 https://llvm.org/bugs/show_bug.cgi?id=27143 Differential Revision: http://reviews.llvm.org/D18566 llvm-svn: 265029
2016-04-01 01:30:06 +08:00
;
[x86] add an SSE2 + fast-unaligned accesses run for memset nonzero tests Was there really no other way to splat a byte in SSE2? punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] llvm-svn: 265172
2016-04-02 02:29:25 +08:00
; SSE2FAST-LABEL: memset_64_nonzero_bytes:
[x86] regenerate checks utils/update_test_checks.py was improved with: http://reviews.llvm.org/rL265414 to include the first line of the function (expected to be a comment line). This ensures that nothing bad has happened before the first actual line of checked asm. It also matches the existing behavior of the old script. llvm-svn: 265416
2016-04-06 01:12:19 +08:00
; SSE2FAST: # BB#0:
; SSE2FAST-NEXT: movaps {{.*#+}} xmm0 = [42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42]
[x86] add an SSE2 + fast-unaligned accesses run for memset nonzero tests Was there really no other way to splat a byte in SSE2? punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] llvm-svn: 265172
2016-04-02 02:29:25 +08:00
; SSE2FAST-NEXT: movups %xmm0, 48(%rdi)
; SSE2FAST-NEXT: movups %xmm0, 32(%rdi)
; SSE2FAST-NEXT: movups %xmm0, 16(%rdi)
; SSE2FAST-NEXT: movups %xmm0, (%rdi)
; SSE2FAST-NEXT: retq
;
[x86] avoid intermediate splat for non-zero memsets (PR27100) Follow-up to D18566 - where we noticed that an intermediate splat was being generated for memsets of non-zero chars. That was because we told getMemsetStores() to use a 32-bit vector element type, and it happily obliged by producing that constant using an integer multiply. The tests that were added in the last patch are now equivalent for AVX1 and AVX2 (no splats, just a vector load), but we have PR27141 to track that splat difference. In the new tests, the splat via shuffling looks ok to me, but there might be some room for improvement depending on uarch there. Note that the SSE1/2 paths are not changed in this patch. That can be a follow-up. This patch should resolve PR27100. Differential Revision: http://reviews.llvm.org/D18676 llvm-svn: 265148
2016-04-02 00:27:14 +08:00
; AVX-LABEL: memset_64_nonzero_bytes:
[x86] regenerate checks utils/update_test_checks.py was improved with: http://reviews.llvm.org/rL265414 to include the first line of the function (expected to be a comment line). This ensures that nothing bad has happened before the first actual line of checked asm. It also matches the existing behavior of the old script. llvm-svn: 265416
2016-04-06 01:12:19 +08:00
; AVX: # BB#0:
; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42]
[x86] avoid intermediate splat for non-zero memsets (PR27100) Follow-up to D18566 - where we noticed that an intermediate splat was being generated for memsets of non-zero chars. That was because we told getMemsetStores() to use a 32-bit vector element type, and it happily obliged by producing that constant using an integer multiply. The tests that were added in the last patch are now equivalent for AVX1 and AVX2 (no splats, just a vector load), but we have PR27141 to track that splat difference. In the new tests, the splat via shuffling looks ok to me, but there might be some room for improvement depending on uarch there. Note that the SSE1/2 paths are not changed in this patch. That can be a follow-up. This patch should resolve PR27100. Differential Revision: http://reviews.llvm.org/D18676 llvm-svn: 265148
2016-04-02 00:27:14 +08:00
; AVX-NEXT: vmovups %ymm0, 32(%rdi)
; AVX-NEXT: vmovups %ymm0, (%rdi)
; AVX-NEXT: vzeroupper
; AVX-NEXT: retq
[x86] add tests to show current memset codegen llvm-svn: 264748
2016-03-30 01:09:27 +08:00
%call = tail call i8* @__memset_chk(i8* %x, i32 42, i64 64, i64 -1)
ret void
}
define void @memset_128_nonzero_bytes(i8* %x) {
[x86] add an SSE1 run for these tests Note however that this is identical to the existing SSE2 run. What we really want is yet another run for an SSE2 machine that also has fast unaligned 16-byte accesses. llvm-svn: 265167
2016-04-02 02:11:30 +08:00
; SSE-LABEL: memset_128_nonzero_bytes:
[x86] regenerate checks utils/update_test_checks.py was improved with: http://reviews.llvm.org/rL265414 to include the first line of the function (expected to be a comment line). This ensures that nothing bad has happened before the first actual line of checked asm. It also matches the existing behavior of the old script. llvm-svn: 265416
2016-04-06 01:12:19 +08:00
; SSE: # BB#0:
; SSE-NEXT: movabsq $3038287259199220266, %rax # imm = 0x2A2A2A2A2A2A2A2A
[x86] add an SSE1 run for these tests Note however that this is identical to the existing SSE2 run. What we really want is yet another run for an SSE2 machine that also has fast unaligned 16-byte accesses. llvm-svn: 265167
2016-04-02 02:11:30 +08:00
; SSE-NEXT: movq %rax, 120(%rdi)
; SSE-NEXT: movq %rax, 112(%rdi)
; SSE-NEXT: movq %rax, 104(%rdi)
; SSE-NEXT: movq %rax, 96(%rdi)
; SSE-NEXT: movq %rax, 88(%rdi)
; SSE-NEXT: movq %rax, 80(%rdi)
; SSE-NEXT: movq %rax, 72(%rdi)
; SSE-NEXT: movq %rax, 64(%rdi)
; SSE-NEXT: movq %rax, 56(%rdi)
; SSE-NEXT: movq %rax, 48(%rdi)
; SSE-NEXT: movq %rax, 40(%rdi)
; SSE-NEXT: movq %rax, 32(%rdi)
; SSE-NEXT: movq %rax, 24(%rdi)
; SSE-NEXT: movq %rax, 16(%rdi)
; SSE-NEXT: movq %rax, 8(%rdi)
; SSE-NEXT: movq %rax, (%rdi)
; SSE-NEXT: retq
[x86] use SSE/AVX ops for non-zero memsets (PR27100) Move the memset check down to the CPU-with-slow-SSE-unaligned-memops case: this allows fast targets to take advantage of SSE/AVX instructions and prevents slow targets from stepping into a codegen sinkhole while trying to splat a byte into an XMM reg. Follow-on bugs exposed by the current codegen are: https://llvm.org/bugs/show_bug.cgi?id=27141 https://llvm.org/bugs/show_bug.cgi?id=27143 Differential Revision: http://reviews.llvm.org/D18566 llvm-svn: 265029
2016-04-01 01:30:06 +08:00
;
[x86] add an SSE2 + fast-unaligned accesses run for memset nonzero tests Was there really no other way to splat a byte in SSE2? punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] llvm-svn: 265172
2016-04-02 02:29:25 +08:00
; SSE2FAST-LABEL: memset_128_nonzero_bytes:
[x86] regenerate checks utils/update_test_checks.py was improved with: http://reviews.llvm.org/rL265414 to include the first line of the function (expected to be a comment line). This ensures that nothing bad has happened before the first actual line of checked asm. It also matches the existing behavior of the old script. llvm-svn: 265416
2016-04-06 01:12:19 +08:00
; SSE2FAST: # BB#0:
; SSE2FAST-NEXT: movaps {{.*#+}} xmm0 = [42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42]
[x86] add an SSE2 + fast-unaligned accesses run for memset nonzero tests Was there really no other way to splat a byte in SSE2? punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] llvm-svn: 265172
2016-04-02 02:29:25 +08:00
; SSE2FAST-NEXT: movups %xmm0, 112(%rdi)
; SSE2FAST-NEXT: movups %xmm0, 96(%rdi)
; SSE2FAST-NEXT: movups %xmm0, 80(%rdi)
; SSE2FAST-NEXT: movups %xmm0, 64(%rdi)
; SSE2FAST-NEXT: movups %xmm0, 48(%rdi)
; SSE2FAST-NEXT: movups %xmm0, 32(%rdi)
; SSE2FAST-NEXT: movups %xmm0, 16(%rdi)
; SSE2FAST-NEXT: movups %xmm0, (%rdi)
; SSE2FAST-NEXT: retq
;
[x86] avoid intermediate splat for non-zero memsets (PR27100) Follow-up to D18566 - where we noticed that an intermediate splat was being generated for memsets of non-zero chars. That was because we told getMemsetStores() to use a 32-bit vector element type, and it happily obliged by producing that constant using an integer multiply. The tests that were added in the last patch are now equivalent for AVX1 and AVX2 (no splats, just a vector load), but we have PR27141 to track that splat difference. In the new tests, the splat via shuffling looks ok to me, but there might be some room for improvement depending on uarch there. Note that the SSE1/2 paths are not changed in this patch. That can be a follow-up. This patch should resolve PR27100. Differential Revision: http://reviews.llvm.org/D18676 llvm-svn: 265148
2016-04-02 00:27:14 +08:00
; AVX-LABEL: memset_128_nonzero_bytes:
[x86] regenerate checks utils/update_test_checks.py was improved with: http://reviews.llvm.org/rL265414 to include the first line of the function (expected to be a comment line). This ensures that nothing bad has happened before the first actual line of checked asm. It also matches the existing behavior of the old script. llvm-svn: 265416
2016-04-06 01:12:19 +08:00
; AVX: # BB#0:
; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42]
[x86] avoid intermediate splat for non-zero memsets (PR27100) Follow-up to D18566 - where we noticed that an intermediate splat was being generated for memsets of non-zero chars. That was because we told getMemsetStores() to use a 32-bit vector element type, and it happily obliged by producing that constant using an integer multiply. The tests that were added in the last patch are now equivalent for AVX1 and AVX2 (no splats, just a vector load), but we have PR27141 to track that splat difference. In the new tests, the splat via shuffling looks ok to me, but there might be some room for improvement depending on uarch there. Note that the SSE1/2 paths are not changed in this patch. That can be a follow-up. This patch should resolve PR27100. Differential Revision: http://reviews.llvm.org/D18676 llvm-svn: 265148
2016-04-02 00:27:14 +08:00
; AVX-NEXT: vmovups %ymm0, 96(%rdi)
; AVX-NEXT: vmovups %ymm0, 64(%rdi)
; AVX-NEXT: vmovups %ymm0, 32(%rdi)
; AVX-NEXT: vmovups %ymm0, (%rdi)
; AVX-NEXT: vzeroupper
; AVX-NEXT: retq
[x86] add tests to show current memset codegen llvm-svn: 264748
2016-03-30 01:09:27 +08:00
%call = tail call i8* @__memset_chk(i8* %x, i32 42, i64 128, i64 -1)
ret void
}
define void @memset_256_nonzero_bytes(i8* %x) {
[x86] add an SSE1 run for these tests Note however that this is identical to the existing SSE2 run. What we really want is yet another run for an SSE2 machine that also has fast unaligned 16-byte accesses. llvm-svn: 265167
2016-04-02 02:11:30 +08:00
; SSE-LABEL: memset_256_nonzero_bytes:
[x86] regenerate checks utils/update_test_checks.py was improved with: http://reviews.llvm.org/rL265414 to include the first line of the function (expected to be a comment line). This ensures that nothing bad has happened before the first actual line of checked asm. It also matches the existing behavior of the old script. llvm-svn: 265416
2016-04-06 01:12:19 +08:00
; SSE: # BB#0:
; SSE-NEXT: pushq %rax
[x86] add an SSE1 run for these tests Note however that this is identical to the existing SSE2 run. What we really want is yet another run for an SSE2 machine that also has fast unaligned 16-byte accesses. llvm-svn: 265167
2016-04-02 02:11:30 +08:00
; SSE-NEXT: .cfi_def_cfa_offset 16
; SSE-NEXT: movl $42, %esi
; SSE-NEXT: movl $256, %edx # imm = 0x100
; SSE-NEXT: callq memset
; SSE-NEXT: popq %rax
; SSE-NEXT: retq
[x86] use SSE/AVX ops for non-zero memsets (PR27100) Move the memset check down to the CPU-with-slow-SSE-unaligned-memops case: this allows fast targets to take advantage of SSE/AVX instructions and prevents slow targets from stepping into a codegen sinkhole while trying to splat a byte into an XMM reg. Follow-on bugs exposed by the current codegen are: https://llvm.org/bugs/show_bug.cgi?id=27141 https://llvm.org/bugs/show_bug.cgi?id=27143 Differential Revision: http://reviews.llvm.org/D18566 llvm-svn: 265029
2016-04-01 01:30:06 +08:00
;
[x86] add an SSE2 + fast-unaligned accesses run for memset nonzero tests Was there really no other way to splat a byte in SSE2? punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] llvm-svn: 265172
2016-04-02 02:29:25 +08:00
; SSE2FAST-LABEL: memset_256_nonzero_bytes:
[x86] regenerate checks utils/update_test_checks.py was improved with: http://reviews.llvm.org/rL265414 to include the first line of the function (expected to be a comment line). This ensures that nothing bad has happened before the first actual line of checked asm. It also matches the existing behavior of the old script. llvm-svn: 265416
2016-04-06 01:12:19 +08:00
; SSE2FAST: # BB#0:
; SSE2FAST-NEXT: movaps {{.*#+}} xmm0 = [42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42]
[x86] add an SSE2 + fast-unaligned accesses run for memset nonzero tests Was there really no other way to splat a byte in SSE2? punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] llvm-svn: 265172
2016-04-02 02:29:25 +08:00
; SSE2FAST-NEXT: movups %xmm0, 240(%rdi)
; SSE2FAST-NEXT: movups %xmm0, 224(%rdi)
; SSE2FAST-NEXT: movups %xmm0, 208(%rdi)
; SSE2FAST-NEXT: movups %xmm0, 192(%rdi)
; SSE2FAST-NEXT: movups %xmm0, 176(%rdi)
; SSE2FAST-NEXT: movups %xmm0, 160(%rdi)
; SSE2FAST-NEXT: movups %xmm0, 144(%rdi)
; SSE2FAST-NEXT: movups %xmm0, 128(%rdi)
; SSE2FAST-NEXT: movups %xmm0, 112(%rdi)
; SSE2FAST-NEXT: movups %xmm0, 96(%rdi)
; SSE2FAST-NEXT: movups %xmm0, 80(%rdi)
; SSE2FAST-NEXT: movups %xmm0, 64(%rdi)
; SSE2FAST-NEXT: movups %xmm0, 48(%rdi)
; SSE2FAST-NEXT: movups %xmm0, 32(%rdi)
; SSE2FAST-NEXT: movups %xmm0, 16(%rdi)
; SSE2FAST-NEXT: movups %xmm0, (%rdi)
; SSE2FAST-NEXT: retq
;
[x86] avoid intermediate splat for non-zero memsets (PR27100) Follow-up to D18566 - where we noticed that an intermediate splat was being generated for memsets of non-zero chars. That was because we told getMemsetStores() to use a 32-bit vector element type, and it happily obliged by producing that constant using an integer multiply. The tests that were added in the last patch are now equivalent for AVX1 and AVX2 (no splats, just a vector load), but we have PR27141 to track that splat difference. In the new tests, the splat via shuffling looks ok to me, but there might be some room for improvement depending on uarch there. Note that the SSE1/2 paths are not changed in this patch. That can be a follow-up. This patch should resolve PR27100. Differential Revision: http://reviews.llvm.org/D18676 llvm-svn: 265148
2016-04-02 00:27:14 +08:00
; AVX-LABEL: memset_256_nonzero_bytes:
[x86] regenerate checks utils/update_test_checks.py was improved with: http://reviews.llvm.org/rL265414 to include the first line of the function (expected to be a comment line). This ensures that nothing bad has happened before the first actual line of checked asm. It also matches the existing behavior of the old script. llvm-svn: 265416
2016-04-06 01:12:19 +08:00
; AVX: # BB#0:
; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42]
[x86] avoid intermediate splat for non-zero memsets (PR27100) Follow-up to D18566 - where we noticed that an intermediate splat was being generated for memsets of non-zero chars. That was because we told getMemsetStores() to use a 32-bit vector element type, and it happily obliged by producing that constant using an integer multiply. The tests that were added in the last patch are now equivalent for AVX1 and AVX2 (no splats, just a vector load), but we have PR27141 to track that splat difference. In the new tests, the splat via shuffling looks ok to me, but there might be some room for improvement depending on uarch there. Note that the SSE1/2 paths are not changed in this patch. That can be a follow-up. This patch should resolve PR27100. Differential Revision: http://reviews.llvm.org/D18676 llvm-svn: 265148
2016-04-02 00:27:14 +08:00
; AVX-NEXT: vmovups %ymm0, 224(%rdi)
; AVX-NEXT: vmovups %ymm0, 192(%rdi)
; AVX-NEXT: vmovups %ymm0, 160(%rdi)
; AVX-NEXT: vmovups %ymm0, 128(%rdi)
; AVX-NEXT: vmovups %ymm0, 96(%rdi)
; AVX-NEXT: vmovups %ymm0, 64(%rdi)
; AVX-NEXT: vmovups %ymm0, 32(%rdi)
; AVX-NEXT: vmovups %ymm0, (%rdi)
; AVX-NEXT: vzeroupper
; AVX-NEXT: retq
[x86] add tests to show current memset codegen llvm-svn: 264748
2016-03-30 01:09:27 +08:00
%call = tail call i8* @__memset_chk(i8* %x, i32 42, i64 256, i64 -1)
ret void
}
declare i8* @__memset_chk(i8*, i32, i64, i64)
[x86] add memset tests to show another potential improvement llvm-svn: 265048
2016-04-01 04:40:32 +08:00
; Repeat with a non-constant value for the stores.
define void @memset_16_nonconst_bytes(i8* %x, i8 %c) {
[x86] add an SSE1 run for these tests Note however that this is identical to the existing SSE2 run. What we really want is yet another run for an SSE2 machine that also has fast unaligned 16-byte accesses. llvm-svn: 265167
2016-04-02 02:11:30 +08:00
; SSE-LABEL: memset_16_nonconst_bytes:
[x86] regenerate checks utils/update_test_checks.py was improved with: http://reviews.llvm.org/rL265414 to include the first line of the function (expected to be a comment line). This ensures that nothing bad has happened before the first actual line of checked asm. It also matches the existing behavior of the old script. llvm-svn: 265416
2016-04-06 01:12:19 +08:00
; SSE: # BB#0:
; SSE-NEXT: movzbl %sil, %eax
[x86] add an SSE1 run for these tests Note however that this is identical to the existing SSE2 run. What we really want is yet another run for an SSE2 machine that also has fast unaligned 16-byte accesses. llvm-svn: 265167
2016-04-02 02:11:30 +08:00
; SSE-NEXT: movabsq $72340172838076673, %rcx # imm = 0x101010101010101
; SSE-NEXT: imulq %rax, %rcx
; SSE-NEXT: movq %rcx, 8(%rdi)
; SSE-NEXT: movq %rcx, (%rdi)
; SSE-NEXT: retq
[x86] add memset tests to show another potential improvement llvm-svn: 265048
2016-04-01 04:40:32 +08:00
;
[x86] add an SSE2 + fast-unaligned accesses run for memset nonzero tests Was there really no other way to splat a byte in SSE2? punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] llvm-svn: 265172
2016-04-02 02:29:25 +08:00
; SSE2FAST-LABEL: memset_16_nonconst_bytes:
[x86] regenerate checks utils/update_test_checks.py was improved with: http://reviews.llvm.org/rL265414 to include the first line of the function (expected to be a comment line). This ensures that nothing bad has happened before the first actual line of checked asm. It also matches the existing behavior of the old script. llvm-svn: 265416
2016-04-06 01:12:19 +08:00
; SSE2FAST: # BB#0:
; SSE2FAST-NEXT: movd %esi, %xmm0
[x86] add an SSE2 + fast-unaligned accesses run for memset nonzero tests Was there really no other way to splat a byte in SSE2? punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] llvm-svn: 265172
2016-04-02 02:29:25 +08:00
; SSE2FAST-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE2FAST-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]
; SSE2FAST-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1]
; SSE2FAST-NEXT: movdqu %xmm0, (%rdi)
; SSE2FAST-NEXT: retq
;
[x86] add memset tests to show another potential improvement llvm-svn: 265048
2016-04-01 04:40:32 +08:00
; AVX1-LABEL: memset_16_nonconst_bytes:
[x86] regenerate checks utils/update_test_checks.py was improved with: http://reviews.llvm.org/rL265414 to include the first line of the function (expected to be a comment line). This ensures that nothing bad has happened before the first actual line of checked asm. It also matches the existing behavior of the old script. llvm-svn: 265416
2016-04-06 01:12:19 +08:00
; AVX1: # BB#0:
; AVX1-NEXT: vmovd %esi, %xmm0
[x86] avoid intermediate splat for non-zero memsets (PR27100) Follow-up to http://reviews.llvm.org/D18566 and http://reviews.llvm.org/D18676 - where we noticed that an intermediate splat was being generated for memsets of non-zero chars. That was because we told getMemsetStores() to use a 32-bit vector element type, and it happily obliged by producing that constant using an integer multiply. The 16-byte test that was added in D18566 is now equivalent for AVX1 and AVX2 (no splats, just a vector load), but we have PR27141 to track that splat difference. Note that the SSE1 path is not changed in this patch. That can be a follow-up. This patch should resolve PR27100. llvm-svn: 265161
2016-04-02 01:36:45 +08:00
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpshufb %xmm1, %xmm0, %xmm0
[x86] add memset tests to show another potential improvement llvm-svn: 265048
2016-04-01 04:40:32 +08:00
; AVX1-NEXT: vmovdqu %xmm0, (%rdi)
; AVX1-NEXT: retq
;
; AVX2-LABEL: memset_16_nonconst_bytes:
[x86] regenerate checks utils/update_test_checks.py was improved with: http://reviews.llvm.org/rL265414 to include the first line of the function (expected to be a comment line). This ensures that nothing bad has happened before the first actual line of checked asm. It also matches the existing behavior of the old script. llvm-svn: 265416
2016-04-06 01:12:19 +08:00
; AVX2: # BB#0:
; AVX2-NEXT: vmovd %esi, %xmm0
[x86] avoid intermediate splat for non-zero memsets (PR27100) Follow-up to http://reviews.llvm.org/D18566 and http://reviews.llvm.org/D18676 - where we noticed that an intermediate splat was being generated for memsets of non-zero chars. That was because we told getMemsetStores() to use a 32-bit vector element type, and it happily obliged by producing that constant using an integer multiply. The 16-byte test that was added in D18566 is now equivalent for AVX1 and AVX2 (no splats, just a vector load), but we have PR27141 to track that splat difference. Note that the SSE1 path is not changed in this patch. That can be a follow-up. This patch should resolve PR27100. llvm-svn: 265161
2016-04-02 01:36:45 +08:00
; AVX2-NEXT: vpbroadcastb %xmm0, %xmm0
; AVX2-NEXT: vmovdqu %xmm0, (%rdi)
[x86] add memset tests to show another potential improvement llvm-svn: 265048
2016-04-01 04:40:32 +08:00
; AVX2-NEXT: retq
tail call void @llvm.memset.p0i8.i64(i8* %x, i8 %c, i64 16, i32 1, i1 false)
ret void
}
define void @memset_32_nonconst_bytes(i8* %x, i8 %c) {
[x86] add an SSE1 run for these tests Note however that this is identical to the existing SSE2 run. What we really want is yet another run for an SSE2 machine that also has fast unaligned 16-byte accesses. llvm-svn: 265167
2016-04-02 02:11:30 +08:00
; SSE-LABEL: memset_32_nonconst_bytes:
[x86] regenerate checks utils/update_test_checks.py was improved with: http://reviews.llvm.org/rL265414 to include the first line of the function (expected to be a comment line). This ensures that nothing bad has happened before the first actual line of checked asm. It also matches the existing behavior of the old script. llvm-svn: 265416
2016-04-06 01:12:19 +08:00
; SSE: # BB#0:
; SSE-NEXT: movzbl %sil, %eax
[x86] add an SSE1 run for these tests Note however that this is identical to the existing SSE2 run. What we really want is yet another run for an SSE2 machine that also has fast unaligned 16-byte accesses. llvm-svn: 265167
2016-04-02 02:11:30 +08:00
; SSE-NEXT: movabsq $72340172838076673, %rcx # imm = 0x101010101010101
; SSE-NEXT: imulq %rax, %rcx
; SSE-NEXT: movq %rcx, 24(%rdi)
; SSE-NEXT: movq %rcx, 16(%rdi)
; SSE-NEXT: movq %rcx, 8(%rdi)
; SSE-NEXT: movq %rcx, (%rdi)
; SSE-NEXT: retq
[x86] add memset tests to show another potential improvement llvm-svn: 265048
2016-04-01 04:40:32 +08:00
;
[x86] add an SSE2 + fast-unaligned accesses run for memset nonzero tests Was there really no other way to splat a byte in SSE2? punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] llvm-svn: 265172
2016-04-02 02:29:25 +08:00
; SSE2FAST-LABEL: memset_32_nonconst_bytes:
[x86] regenerate checks utils/update_test_checks.py was improved with: http://reviews.llvm.org/rL265414 to include the first line of the function (expected to be a comment line). This ensures that nothing bad has happened before the first actual line of checked asm. It also matches the existing behavior of the old script. llvm-svn: 265416
2016-04-06 01:12:19 +08:00
; SSE2FAST: # BB#0:
; SSE2FAST-NEXT: movd %esi, %xmm0
[x86] add an SSE2 + fast-unaligned accesses run for memset nonzero tests Was there really no other way to splat a byte in SSE2? punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] llvm-svn: 265172
2016-04-02 02:29:25 +08:00
; SSE2FAST-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE2FAST-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]
; SSE2FAST-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1]
; SSE2FAST-NEXT: movdqu %xmm0, 16(%rdi)
; SSE2FAST-NEXT: movdqu %xmm0, (%rdi)
; SSE2FAST-NEXT: retq
;
[x86] add memset tests to show another potential improvement llvm-svn: 265048
2016-04-01 04:40:32 +08:00
; AVX1-LABEL: memset_32_nonconst_bytes:
[x86] regenerate checks utils/update_test_checks.py was improved with: http://reviews.llvm.org/rL265414 to include the first line of the function (expected to be a comment line). This ensures that nothing bad has happened before the first actual line of checked asm. It also matches the existing behavior of the old script. llvm-svn: 265416
2016-04-06 01:12:19 +08:00
; AVX1: # BB#0:
; AVX1-NEXT: vmovd %esi, %xmm0
[x86] avoid intermediate splat for non-zero memsets (PR27100) Follow-up to D18566 - where we noticed that an intermediate splat was being generated for memsets of non-zero chars. That was because we told getMemsetStores() to use a 32-bit vector element type, and it happily obliged by producing that constant using an integer multiply. The tests that were added in the last patch are now equivalent for AVX1 and AVX2 (no splats, just a vector load), but we have PR27141 to track that splat difference. In the new tests, the splat via shuffling looks ok to me, but there might be some room for improvement depending on uarch there. Note that the SSE1/2 paths are not changed in this patch. That can be a follow-up. This patch should resolve PR27100. Differential Revision: http://reviews.llvm.org/D18676 llvm-svn: 265148
2016-04-02 00:27:14 +08:00
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpshufb %xmm1, %xmm0, %xmm0
[x86] add memset tests to show another potential improvement llvm-svn: 265048
2016-04-01 04:40:32 +08:00
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; AVX1-NEXT: vmovups %ymm0, (%rdi)
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: memset_32_nonconst_bytes:
[x86] regenerate checks utils/update_test_checks.py was improved with: http://reviews.llvm.org/rL265414 to include the first line of the function (expected to be a comment line). This ensures that nothing bad has happened before the first actual line of checked asm. It also matches the existing behavior of the old script. llvm-svn: 265416
2016-04-06 01:12:19 +08:00
; AVX2: # BB#0:
; AVX2-NEXT: vmovd %esi, %xmm0
[x86] avoid intermediate splat for non-zero memsets (PR27100) Follow-up to D18566 - where we noticed that an intermediate splat was being generated for memsets of non-zero chars. That was because we told getMemsetStores() to use a 32-bit vector element type, and it happily obliged by producing that constant using an integer multiply. The tests that were added in the last patch are now equivalent for AVX1 and AVX2 (no splats, just a vector load), but we have PR27141 to track that splat difference. In the new tests, the splat via shuffling looks ok to me, but there might be some room for improvement depending on uarch there. Note that the SSE1/2 paths are not changed in this patch. That can be a follow-up. This patch should resolve PR27100. Differential Revision: http://reviews.llvm.org/D18676 llvm-svn: 265148
2016-04-02 00:27:14 +08:00
; AVX2-NEXT: vpbroadcastb %xmm0, %ymm0
; AVX2-NEXT: vmovdqu %ymm0, (%rdi)
[x86] add memset tests to show another potential improvement llvm-svn: 265048
2016-04-01 04:40:32 +08:00
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
tail call void @llvm.memset.p0i8.i64(i8* %x, i8 %c, i64 32, i32 1, i1 false)
ret void
}
define void @memset_64_nonconst_bytes(i8* %x, i8 %c) {
[x86] add an SSE1 run for these tests Note however that this is identical to the existing SSE2 run. What we really want is yet another run for an SSE2 machine that also has fast unaligned 16-byte accesses. llvm-svn: 265167
2016-04-02 02:11:30 +08:00
; SSE-LABEL: memset_64_nonconst_bytes:
[x86] regenerate checks utils/update_test_checks.py was improved with: http://reviews.llvm.org/rL265414 to include the first line of the function (expected to be a comment line). This ensures that nothing bad has happened before the first actual line of checked asm. It also matches the existing behavior of the old script. llvm-svn: 265416
2016-04-06 01:12:19 +08:00
; SSE: # BB#0:
; SSE-NEXT: movzbl %sil, %eax
[x86] add an SSE1 run for these tests Note however that this is identical to the existing SSE2 run. What we really want is yet another run for an SSE2 machine that also has fast unaligned 16-byte accesses. llvm-svn: 265167
2016-04-02 02:11:30 +08:00
; SSE-NEXT: movabsq $72340172838076673, %rcx # imm = 0x101010101010101
; SSE-NEXT: imulq %rax, %rcx
; SSE-NEXT: movq %rcx, 56(%rdi)
; SSE-NEXT: movq %rcx, 48(%rdi)
; SSE-NEXT: movq %rcx, 40(%rdi)
; SSE-NEXT: movq %rcx, 32(%rdi)
; SSE-NEXT: movq %rcx, 24(%rdi)
; SSE-NEXT: movq %rcx, 16(%rdi)
; SSE-NEXT: movq %rcx, 8(%rdi)
; SSE-NEXT: movq %rcx, (%rdi)
; SSE-NEXT: retq
[x86] add memset tests to show another potential improvement llvm-svn: 265048
2016-04-01 04:40:32 +08:00
;
[x86] add an SSE2 + fast-unaligned accesses run for memset nonzero tests Was there really no other way to splat a byte in SSE2? punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] llvm-svn: 265172
2016-04-02 02:29:25 +08:00
; SSE2FAST-LABEL: memset_64_nonconst_bytes:
[x86] regenerate checks utils/update_test_checks.py was improved with: http://reviews.llvm.org/rL265414 to include the first line of the function (expected to be a comment line). This ensures that nothing bad has happened before the first actual line of checked asm. It also matches the existing behavior of the old script. llvm-svn: 265416
2016-04-06 01:12:19 +08:00
; SSE2FAST: # BB#0:
; SSE2FAST-NEXT: movd %esi, %xmm0
[x86] add an SSE2 + fast-unaligned accesses run for memset nonzero tests Was there really no other way to splat a byte in SSE2? punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] llvm-svn: 265172
2016-04-02 02:29:25 +08:00
; SSE2FAST-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE2FAST-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]
; SSE2FAST-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1]
; SSE2FAST-NEXT: movdqu %xmm0, 48(%rdi)
; SSE2FAST-NEXT: movdqu %xmm0, 32(%rdi)
; SSE2FAST-NEXT: movdqu %xmm0, 16(%rdi)
; SSE2FAST-NEXT: movdqu %xmm0, (%rdi)
; SSE2FAST-NEXT: retq
;
[x86] add memset tests to show another potential improvement llvm-svn: 265048
2016-04-01 04:40:32 +08:00
; AVX1-LABEL: memset_64_nonconst_bytes:
[x86] regenerate checks utils/update_test_checks.py was improved with: http://reviews.llvm.org/rL265414 to include the first line of the function (expected to be a comment line). This ensures that nothing bad has happened before the first actual line of checked asm. It also matches the existing behavior of the old script. llvm-svn: 265416
2016-04-06 01:12:19 +08:00
; AVX1: # BB#0:
; AVX1-NEXT: vmovd %esi, %xmm0
[x86] avoid intermediate splat for non-zero memsets (PR27100) Follow-up to D18566 - where we noticed that an intermediate splat was being generated for memsets of non-zero chars. That was because we told getMemsetStores() to use a 32-bit vector element type, and it happily obliged by producing that constant using an integer multiply. The tests that were added in the last patch are now equivalent for AVX1 and AVX2 (no splats, just a vector load), but we have PR27141 to track that splat difference. In the new tests, the splat via shuffling looks ok to me, but there might be some room for improvement depending on uarch there. Note that the SSE1/2 paths are not changed in this patch. That can be a follow-up. This patch should resolve PR27100. Differential Revision: http://reviews.llvm.org/D18676 llvm-svn: 265148
2016-04-02 00:27:14 +08:00
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpshufb %xmm1, %xmm0, %xmm0
[x86] add memset tests to show another potential improvement llvm-svn: 265048
2016-04-01 04:40:32 +08:00
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; AVX1-NEXT: vmovups %ymm0, 32(%rdi)
; AVX1-NEXT: vmovups %ymm0, (%rdi)
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: memset_64_nonconst_bytes:
[x86] regenerate checks utils/update_test_checks.py was improved with: http://reviews.llvm.org/rL265414 to include the first line of the function (expected to be a comment line). This ensures that nothing bad has happened before the first actual line of checked asm. It also matches the existing behavior of the old script. llvm-svn: 265416
2016-04-06 01:12:19 +08:00
; AVX2: # BB#0:
; AVX2-NEXT: vmovd %esi, %xmm0
[x86] avoid intermediate splat for non-zero memsets (PR27100) Follow-up to D18566 - where we noticed that an intermediate splat was being generated for memsets of non-zero chars. That was because we told getMemsetStores() to use a 32-bit vector element type, and it happily obliged by producing that constant using an integer multiply. The tests that were added in the last patch are now equivalent for AVX1 and AVX2 (no splats, just a vector load), but we have PR27141 to track that splat difference. In the new tests, the splat via shuffling looks ok to me, but there might be some room for improvement depending on uarch there. Note that the SSE1/2 paths are not changed in this patch. That can be a follow-up. This patch should resolve PR27100. Differential Revision: http://reviews.llvm.org/D18676 llvm-svn: 265148
2016-04-02 00:27:14 +08:00
; AVX2-NEXT: vpbroadcastb %xmm0, %ymm0
; AVX2-NEXT: vmovdqu %ymm0, 32(%rdi)
; AVX2-NEXT: vmovdqu %ymm0, (%rdi)
[x86] add memset tests to show another potential improvement llvm-svn: 265048
2016-04-01 04:40:32 +08:00
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
tail call void @llvm.memset.p0i8.i64(i8* %x, i8 %c, i64 64, i32 1, i1 false)
ret void
}
define void @memset_128_nonconst_bytes(i8* %x, i8 %c) {
[x86] add an SSE1 run for these tests Note however that this is identical to the existing SSE2 run. What we really want is yet another run for an SSE2 machine that also has fast unaligned 16-byte accesses. llvm-svn: 265167
2016-04-02 02:11:30 +08:00
; SSE-LABEL: memset_128_nonconst_bytes:
[x86] regenerate checks utils/update_test_checks.py was improved with: http://reviews.llvm.org/rL265414 to include the first line of the function (expected to be a comment line). This ensures that nothing bad has happened before the first actual line of checked asm. It also matches the existing behavior of the old script. llvm-svn: 265416
2016-04-06 01:12:19 +08:00
; SSE: # BB#0:
; SSE-NEXT: movzbl %sil, %eax
[x86] add an SSE1 run for these tests Note however that this is identical to the existing SSE2 run. What we really want is yet another run for an SSE2 machine that also has fast unaligned 16-byte accesses. llvm-svn: 265167
2016-04-02 02:11:30 +08:00
; SSE-NEXT: movabsq $72340172838076673, %rcx # imm = 0x101010101010101
; SSE-NEXT: imulq %rax, %rcx
; SSE-NEXT: movq %rcx, 120(%rdi)
; SSE-NEXT: movq %rcx, 112(%rdi)
; SSE-NEXT: movq %rcx, 104(%rdi)
; SSE-NEXT: movq %rcx, 96(%rdi)
; SSE-NEXT: movq %rcx, 88(%rdi)
; SSE-NEXT: movq %rcx, 80(%rdi)
; SSE-NEXT: movq %rcx, 72(%rdi)
; SSE-NEXT: movq %rcx, 64(%rdi)
; SSE-NEXT: movq %rcx, 56(%rdi)
; SSE-NEXT: movq %rcx, 48(%rdi)
; SSE-NEXT: movq %rcx, 40(%rdi)
; SSE-NEXT: movq %rcx, 32(%rdi)
; SSE-NEXT: movq %rcx, 24(%rdi)
; SSE-NEXT: movq %rcx, 16(%rdi)
; SSE-NEXT: movq %rcx, 8(%rdi)
; SSE-NEXT: movq %rcx, (%rdi)
; SSE-NEXT: retq
[x86] add memset tests to show another potential improvement llvm-svn: 265048
2016-04-01 04:40:32 +08:00
;
[x86] add an SSE2 + fast-unaligned accesses run for memset nonzero tests Was there really no other way to splat a byte in SSE2? punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] llvm-svn: 265172
2016-04-02 02:29:25 +08:00
; SSE2FAST-LABEL: memset_128_nonconst_bytes:
[x86] regenerate checks utils/update_test_checks.py was improved with: http://reviews.llvm.org/rL265414 to include the first line of the function (expected to be a comment line). This ensures that nothing bad has happened before the first actual line of checked asm. It also matches the existing behavior of the old script. llvm-svn: 265416
2016-04-06 01:12:19 +08:00
; SSE2FAST: # BB#0:
; SSE2FAST-NEXT: movd %esi, %xmm0
[x86] add an SSE2 + fast-unaligned accesses run for memset nonzero tests Was there really no other way to splat a byte in SSE2? punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] llvm-svn: 265172
2016-04-02 02:29:25 +08:00
; SSE2FAST-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE2FAST-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]
; SSE2FAST-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1]
; SSE2FAST-NEXT: movdqu %xmm0, 112(%rdi)
; SSE2FAST-NEXT: movdqu %xmm0, 96(%rdi)
; SSE2FAST-NEXT: movdqu %xmm0, 80(%rdi)
; SSE2FAST-NEXT: movdqu %xmm0, 64(%rdi)
; SSE2FAST-NEXT: movdqu %xmm0, 48(%rdi)
; SSE2FAST-NEXT: movdqu %xmm0, 32(%rdi)
; SSE2FAST-NEXT: movdqu %xmm0, 16(%rdi)
; SSE2FAST-NEXT: movdqu %xmm0, (%rdi)
; SSE2FAST-NEXT: retq
;
[x86] add memset tests to show another potential improvement llvm-svn: 265048
2016-04-01 04:40:32 +08:00
; AVX1-LABEL: memset_128_nonconst_bytes:
[x86] regenerate checks utils/update_test_checks.py was improved with: http://reviews.llvm.org/rL265414 to include the first line of the function (expected to be a comment line). This ensures that nothing bad has happened before the first actual line of checked asm. It also matches the existing behavior of the old script. llvm-svn: 265416
2016-04-06 01:12:19 +08:00
; AVX1: # BB#0:
; AVX1-NEXT: vmovd %esi, %xmm0
[x86] avoid intermediate splat for non-zero memsets (PR27100) Follow-up to D18566 - where we noticed that an intermediate splat was being generated for memsets of non-zero chars. That was because we told getMemsetStores() to use a 32-bit vector element type, and it happily obliged by producing that constant using an integer multiply. The tests that were added in the last patch are now equivalent for AVX1 and AVX2 (no splats, just a vector load), but we have PR27141 to track that splat difference. In the new tests, the splat via shuffling looks ok to me, but there might be some room for improvement depending on uarch there. Note that the SSE1/2 paths are not changed in this patch. That can be a follow-up. This patch should resolve PR27100. Differential Revision: http://reviews.llvm.org/D18676 llvm-svn: 265148
2016-04-02 00:27:14 +08:00
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpshufb %xmm1, %xmm0, %xmm0
[x86] add memset tests to show another potential improvement llvm-svn: 265048
2016-04-01 04:40:32 +08:00
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; AVX1-NEXT: vmovups %ymm0, 96(%rdi)
; AVX1-NEXT: vmovups %ymm0, 64(%rdi)
; AVX1-NEXT: vmovups %ymm0, 32(%rdi)
; AVX1-NEXT: vmovups %ymm0, (%rdi)
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: memset_128_nonconst_bytes:
[x86] regenerate checks utils/update_test_checks.py was improved with: http://reviews.llvm.org/rL265414 to include the first line of the function (expected to be a comment line). This ensures that nothing bad has happened before the first actual line of checked asm. It also matches the existing behavior of the old script. llvm-svn: 265416
2016-04-06 01:12:19 +08:00
; AVX2: # BB#0:
; AVX2-NEXT: vmovd %esi, %xmm0
[x86] avoid intermediate splat for non-zero memsets (PR27100) Follow-up to D18566 - where we noticed that an intermediate splat was being generated for memsets of non-zero chars. That was because we told getMemsetStores() to use a 32-bit vector element type, and it happily obliged by producing that constant using an integer multiply. The tests that were added in the last patch are now equivalent for AVX1 and AVX2 (no splats, just a vector load), but we have PR27141 to track that splat difference. In the new tests, the splat via shuffling looks ok to me, but there might be some room for improvement depending on uarch there. Note that the SSE1/2 paths are not changed in this patch. That can be a follow-up. This patch should resolve PR27100. Differential Revision: http://reviews.llvm.org/D18676 llvm-svn: 265148
2016-04-02 00:27:14 +08:00
; AVX2-NEXT: vpbroadcastb %xmm0, %ymm0
; AVX2-NEXT: vmovdqu %ymm0, 96(%rdi)
; AVX2-NEXT: vmovdqu %ymm0, 64(%rdi)
; AVX2-NEXT: vmovdqu %ymm0, 32(%rdi)
; AVX2-NEXT: vmovdqu %ymm0, (%rdi)
[x86] add memset tests to show another potential improvement llvm-svn: 265048
2016-04-01 04:40:32 +08:00
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
tail call void @llvm.memset.p0i8.i64(i8* %x, i8 %c, i64 128, i32 1, i1 false)
ret void
}
define void @memset_256_nonconst_bytes(i8* %x, i8 %c) {
[x86] add an SSE1 run for these tests Note however that this is identical to the existing SSE2 run. What we really want is yet another run for an SSE2 machine that also has fast unaligned 16-byte accesses. llvm-svn: 265167
2016-04-02 02:11:30 +08:00
; SSE-LABEL: memset_256_nonconst_bytes:
[x86] regenerate checks utils/update_test_checks.py was improved with: http://reviews.llvm.org/rL265414 to include the first line of the function (expected to be a comment line). This ensures that nothing bad has happened before the first actual line of checked asm. It also matches the existing behavior of the old script. llvm-svn: 265416
2016-04-06 01:12:19 +08:00
; SSE: # BB#0:
; SSE-NEXT: movl $256, %edx # imm = 0x100
[x86] add an SSE1 run for these tests Note however that this is identical to the existing SSE2 run. What we really want is yet another run for an SSE2 machine that also has fast unaligned 16-byte accesses. llvm-svn: 265167
2016-04-02 02:11:30 +08:00
; SSE-NEXT: jmp memset # TAILCALL
[x86] add memset tests to show another potential improvement llvm-svn: 265048
2016-04-01 04:40:32 +08:00
;
[x86] add an SSE2 + fast-unaligned accesses run for memset nonzero tests Was there really no other way to splat a byte in SSE2? punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] llvm-svn: 265172
2016-04-02 02:29:25 +08:00
; SSE2FAST-LABEL: memset_256_nonconst_bytes:
[x86] regenerate checks utils/update_test_checks.py was improved with: http://reviews.llvm.org/rL265414 to include the first line of the function (expected to be a comment line). This ensures that nothing bad has happened before the first actual line of checked asm. It also matches the existing behavior of the old script. llvm-svn: 265416
2016-04-06 01:12:19 +08:00
; SSE2FAST: # BB#0:
; SSE2FAST-NEXT: movd %esi, %xmm0
[x86] add an SSE2 + fast-unaligned accesses run for memset nonzero tests Was there really no other way to splat a byte in SSE2? punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] llvm-svn: 265172
2016-04-02 02:29:25 +08:00
; SSE2FAST-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE2FAST-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]
; SSE2FAST-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1]
; SSE2FAST-NEXT: movdqu %xmm0, 240(%rdi)
; SSE2FAST-NEXT: movdqu %xmm0, 224(%rdi)
; SSE2FAST-NEXT: movdqu %xmm0, 208(%rdi)
; SSE2FAST-NEXT: movdqu %xmm0, 192(%rdi)
; SSE2FAST-NEXT: movdqu %xmm0, 176(%rdi)
; SSE2FAST-NEXT: movdqu %xmm0, 160(%rdi)
; SSE2FAST-NEXT: movdqu %xmm0, 144(%rdi)
; SSE2FAST-NEXT: movdqu %xmm0, 128(%rdi)
; SSE2FAST-NEXT: movdqu %xmm0, 112(%rdi)
; SSE2FAST-NEXT: movdqu %xmm0, 96(%rdi)
; SSE2FAST-NEXT: movdqu %xmm0, 80(%rdi)
; SSE2FAST-NEXT: movdqu %xmm0, 64(%rdi)
; SSE2FAST-NEXT: movdqu %xmm0, 48(%rdi)
; SSE2FAST-NEXT: movdqu %xmm0, 32(%rdi)
; SSE2FAST-NEXT: movdqu %xmm0, 16(%rdi)
; SSE2FAST-NEXT: movdqu %xmm0, (%rdi)
; SSE2FAST-NEXT: retq
;
[x86] add memset tests to show another potential improvement llvm-svn: 265048
2016-04-01 04:40:32 +08:00
; AVX1-LABEL: memset_256_nonconst_bytes:
[x86] regenerate checks utils/update_test_checks.py was improved with: http://reviews.llvm.org/rL265414 to include the first line of the function (expected to be a comment line). This ensures that nothing bad has happened before the first actual line of checked asm. It also matches the existing behavior of the old script. llvm-svn: 265416
2016-04-06 01:12:19 +08:00
; AVX1: # BB#0:
; AVX1-NEXT: vmovd %esi, %xmm0
[x86] avoid intermediate splat for non-zero memsets (PR27100) Follow-up to D18566 - where we noticed that an intermediate splat was being generated for memsets of non-zero chars. That was because we told getMemsetStores() to use a 32-bit vector element type, and it happily obliged by producing that constant using an integer multiply. The tests that were added in the last patch are now equivalent for AVX1 and AVX2 (no splats, just a vector load), but we have PR27141 to track that splat difference. In the new tests, the splat via shuffling looks ok to me, but there might be some room for improvement depending on uarch there. Note that the SSE1/2 paths are not changed in this patch. That can be a follow-up. This patch should resolve PR27100. Differential Revision: http://reviews.llvm.org/D18676 llvm-svn: 265148
2016-04-02 00:27:14 +08:00
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpshufb %xmm1, %xmm0, %xmm0
[x86] add memset tests to show another potential improvement llvm-svn: 265048
2016-04-01 04:40:32 +08:00
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; AVX1-NEXT: vmovups %ymm0, 224(%rdi)
; AVX1-NEXT: vmovups %ymm0, 192(%rdi)
; AVX1-NEXT: vmovups %ymm0, 160(%rdi)
; AVX1-NEXT: vmovups %ymm0, 128(%rdi)
; AVX1-NEXT: vmovups %ymm0, 96(%rdi)
; AVX1-NEXT: vmovups %ymm0, 64(%rdi)
; AVX1-NEXT: vmovups %ymm0, 32(%rdi)
; AVX1-NEXT: vmovups %ymm0, (%rdi)
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: memset_256_nonconst_bytes:
[x86] regenerate checks utils/update_test_checks.py was improved with: http://reviews.llvm.org/rL265414 to include the first line of the function (expected to be a comment line). This ensures that nothing bad has happened before the first actual line of checked asm. It also matches the existing behavior of the old script. llvm-svn: 265416
2016-04-06 01:12:19 +08:00
; AVX2: # BB#0:
; AVX2-NEXT: vmovd %esi, %xmm0
[x86] avoid intermediate splat for non-zero memsets (PR27100) Follow-up to D18566 - where we noticed that an intermediate splat was being generated for memsets of non-zero chars. That was because we told getMemsetStores() to use a 32-bit vector element type, and it happily obliged by producing that constant using an integer multiply. The tests that were added in the last patch are now equivalent for AVX1 and AVX2 (no splats, just a vector load), but we have PR27141 to track that splat difference. In the new tests, the splat via shuffling looks ok to me, but there might be some room for improvement depending on uarch there. Note that the SSE1/2 paths are not changed in this patch. That can be a follow-up. This patch should resolve PR27100. Differential Revision: http://reviews.llvm.org/D18676 llvm-svn: 265148
2016-04-02 00:27:14 +08:00
; AVX2-NEXT: vpbroadcastb %xmm0, %ymm0
; AVX2-NEXT: vmovdqu %ymm0, 224(%rdi)
; AVX2-NEXT: vmovdqu %ymm0, 192(%rdi)
; AVX2-NEXT: vmovdqu %ymm0, 160(%rdi)
; AVX2-NEXT: vmovdqu %ymm0, 128(%rdi)
; AVX2-NEXT: vmovdqu %ymm0, 96(%rdi)
; AVX2-NEXT: vmovdqu %ymm0, 64(%rdi)
; AVX2-NEXT: vmovdqu %ymm0, 32(%rdi)
; AVX2-NEXT: vmovdqu %ymm0, (%rdi)
[x86] add memset tests to show another potential improvement llvm-svn: 265048
2016-04-01 04:40:32 +08:00
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
tail call void @llvm.memset.p0i8.i64(i8* %x, i8 %c, i64 256, i32 1, i1 false)
ret void
}
declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) #1