forked from OSchip/llvm-project
76 lines
3.6 KiB
LLVM
76 lines
3.6 KiB
LLVM
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; RUN: llc -march=cpp -o - %s | FileCheck %s
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define void @test_atomicrmw(i32* %addr, i32 %inc) {
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%inst0 = atomicrmw xchg i32* %addr, i32 %inc seq_cst
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; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Xchg, {{.*}}, SequentiallyConsistent, CrossThread
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; CHECK: [[INST]]->setName("inst0");
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; CHECK: [[INST]]->setVolatile(false);
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%inst1 = atomicrmw add i32* %addr, i32 %inc seq_cst
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; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Add, {{.*}}, SequentiallyConsistent, CrossThread
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; CHECK: [[INST]]->setName("inst1");
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; CHECK: [[INST]]->setVolatile(false);
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%inst2 = atomicrmw volatile sub i32* %addr, i32 %inc singlethread monotonic
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; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Sub, {{.*}}, Monotonic, SingleThread
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; CHECK: [[INST]]->setName("inst2");
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; CHECK: [[INST]]->setVolatile(true);
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%inst3 = atomicrmw and i32* %addr, i32 %inc acq_rel
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; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::And, {{.*}}, AcquireRelease, CrossThread
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; CHECK: [[INST]]->setName("inst3");
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; CHECK: [[INST]]->setVolatile(false);
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%inst4 = atomicrmw nand i32* %addr, i32 %inc release
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; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Nand, {{.*}}, Release, CrossThread
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; CHECK: [[INST]]->setName("inst4");
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; CHECK: [[INST]]->setVolatile(false);
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%inst5 = atomicrmw volatile or i32* %addr, i32 %inc singlethread seq_cst
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; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Or, {{.*}}, SequentiallyConsistent, SingleThread
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; CHECK: [[INST]]->setName("inst5");
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; CHECK: [[INST]]->setVolatile(true);
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%inst6 = atomicrmw xor i32* %addr, i32 %inc release
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; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Xor, {{.*}}, Release, CrossThread
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; CHECK: [[INST]]->setName("inst6");
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; CHECK: [[INST]]->setVolatile(false);
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%inst7 = atomicrmw volatile max i32* %addr, i32 %inc singlethread monotonic
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; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Max, {{.*}}, Monotonic, SingleThread
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; CHECK: [[INST]]->setName("inst7");
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; CHECK: [[INST]]->setVolatile(true);
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%inst8 = atomicrmw min i32* %addr, i32 %inc acquire
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; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Min, {{.*}}, Acquire, CrossThread
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; CHECK: [[INST]]->setName("inst8");
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; CHECK: [[INST]]->setVolatile(false);
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%inst9 = atomicrmw volatile umax i32* %addr, i32 %inc monotonic
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; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::UMax, {{.*}}, Monotonic, CrossThread
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; CHECK: [[INST]]->setName("inst9");
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; CHECK: [[INST]]->setVolatile(true);
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%inst10 = atomicrmw umin i32* %addr, i32 %inc singlethread release
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; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::UMin, {{.*}}, Release, SingleThread
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; CHECK: [[INST]]->setName("inst10");
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; CHECK: [[INST]]->setVolatile(false);
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ret void
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}
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define void @test_cmpxchg(i32* %addr, i32 %desired, i32 %new) {
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%inst0 = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst monotonic
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; CHECK: AtomicCmpXchgInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicCmpXchgInst({{.*}}, SequentiallyConsistent, Monotonic, CrossThread
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; CHECK: [[INST]]->setName("inst0");
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; CHECK: [[INST]]->setVolatile(false);
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%inst1 = cmpxchg volatile i32* %addr, i32 %desired, i32 %new singlethread acq_rel acquire
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; CHECK: AtomicCmpXchgInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicCmpXchgInst({{.*}}, AcquireRelease, Acquire, SingleThread
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; CHECK: [[INST]]->setName("inst1");
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; CHECK: [[INST]]->setVolatile(true);
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ret void
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}
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