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llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-from-extend-nar...

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GlobalISel: Reduce G_SHL width if source is extension shl ([sza]ext x, y) => zext (shl x, y). Turns expensive 64 bit shifts into 32 bit if it does not overflow the source type: This is a port of an AMDGPU DAG combine added in 5fa289f0d8ff85b9e14d2f814a90761378ab54ae. InstCombine does this already, but we need to do it again here to apply it to shifts introduced for lowered getelementptrs. This will help matching addressing modes that use 32-bit offsets in a future patch. TableGen annoyingly assumes only a single match data operand, so introduce a reusable struct. However, this still requires defining a separate GIMatchData for every combine which is still annoying. Adds a morally equivalent function to the existing getShiftAmountTy. Without this, we would have to do try to repeatedly query the legalizer info and guess at what type to use for the shift.
2020-08-16 01:38:29 +08:00
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX6 %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX9 %s
---
name: narrow_shl_s32_by_2_from_zext_s16
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
; GFX6-LABEL: name: narrow_shl_s32_by_2_from_zext_s16
; GFX6: liveins: $vgpr0
; GFX6: %argument:_(s32) = COPY $vgpr0
; GFX6: %narrow:_(s16) = G_TRUNC %argument(s32)
; GFX6: %masklow14:_(s16) = G_CONSTANT i16 16383
; GFX6: %masked:_(s16) = G_AND %narrow, %masklow14
; GFX6: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
; GFX6: [[SHL:%[0-9]+]]:_(s16) = G_SHL %masked, [[C]](s16)
; GFX6: %shl:_(s32) = G_ZEXT [[SHL]](s16)
; GFX6: $vgpr0 = COPY %shl(s32)
; GFX9-LABEL: name: narrow_shl_s32_by_2_from_zext_s16
; GFX9: liveins: $vgpr0
; GFX9: %argument:_(s32) = COPY $vgpr0
; GFX9: %narrow:_(s16) = G_TRUNC %argument(s32)
; GFX9: %masklow14:_(s16) = G_CONSTANT i16 16383
; GFX9: %masked:_(s16) = G_AND %narrow, %masklow14
; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL %masked, [[C]](s16)
; GFX9: %shl:_(s32) = G_ZEXT [[SHL]](s16)
; GFX9: $vgpr0 = COPY %shl(s32)
%argument:_(s32) = COPY $vgpr0
%narrow:_(s16) = G_TRUNC %argument
%masklow14:_(s16) = G_CONSTANT i16 16383
%masked:_(s16) = G_AND %narrow, %masklow14
%extend:_(s32) = G_ZEXT %masked
%shiftamt:_(s32) = G_CONSTANT i32 2
%shl:_(s32) = G_SHL %extend, %shiftamt
$vgpr0 = COPY %shl
...
---
name: narrow_shl_s64_by_2_from_zext_s16
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
; GFX6-LABEL: name: narrow_shl_s64_by_2_from_zext_s16
; GFX6: liveins: $vgpr0
; GFX6: %argument:_(s32) = COPY $vgpr0
; GFX6: %narrow:_(s16) = G_TRUNC %argument(s32)
; GFX6: %masklow14:_(s16) = G_CONSTANT i16 16383
; GFX6: %masked:_(s16) = G_AND %narrow, %masklow14
; GFX6: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
; GFX6: [[SHL:%[0-9]+]]:_(s16) = G_SHL %masked, [[C]](s16)
; GFX6: %shl:_(s64) = G_ZEXT [[SHL]](s16)
; GFX6: $vgpr0_vgpr1 = COPY %shl(s64)
; GFX9-LABEL: name: narrow_shl_s64_by_2_from_zext_s16
; GFX9: liveins: $vgpr0
; GFX9: %argument:_(s32) = COPY $vgpr0
; GFX9: %narrow:_(s16) = G_TRUNC %argument(s32)
; GFX9: %masklow14:_(s16) = G_CONSTANT i16 16383
; GFX9: %masked:_(s16) = G_AND %narrow, %masklow14
; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL %masked, [[C]](s16)
; GFX9: %shl:_(s64) = G_ZEXT [[SHL]](s16)
; GFX9: $vgpr0_vgpr1 = COPY %shl(s64)
%argument:_(s32) = COPY $vgpr0
%narrow:_(s16) = G_TRUNC %argument
%masklow14:_(s16) = G_CONSTANT i16 16383
%masked:_(s16) = G_AND %narrow, %masklow14
%extend:_(s64) = G_ZEXT %masked
%shiftamt:_(s32) = G_CONSTANT i32 2
%shl:_(s64) = G_SHL %extend, %shiftamt
$vgpr0_vgpr1 = COPY %shl
...
---
name: narrow_shl_s16_by_2_from_zext_s8
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
; GFX6-LABEL: name: narrow_shl_s16_by_2_from_zext_s8
; GFX6: liveins: $vgpr0
; GFX6: %argument:_(s32) = COPY $vgpr0
; GFX6: %narrow:_(s8) = G_TRUNC %argument(s32)
; GFX6: %masklow6:_(s8) = G_CONSTANT i8 63
; GFX6: %masked:_(s8) = G_AND %narrow, %masklow6
; GFX6: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 2
; GFX6: [[SHL:%[0-9]+]]:_(s8) = G_SHL %masked, [[C]](s8)
GlobalISel: Add combines for extend operations https://reviews.llvm.org/D86516
2020-09-01 23:50:06 +08:00
; GFX6: %result:_(s32) = G_ZEXT [[SHL]](s8)
GlobalISel: Reduce G_SHL width if source is extension shl ([sza]ext x, y) => zext (shl x, y). Turns expensive 64 bit shifts into 32 bit if it does not overflow the source type: This is a port of an AMDGPU DAG combine added in 5fa289f0d8ff85b9e14d2f814a90761378ab54ae. InstCombine does this already, but we need to do it again here to apply it to shifts introduced for lowered getelementptrs. This will help matching addressing modes that use 32-bit offsets in a future patch. TableGen annoyingly assumes only a single match data operand, so introduce a reusable struct. However, this still requires defining a separate GIMatchData for every combine which is still annoying. Adds a morally equivalent function to the existing getShiftAmountTy. Without this, we would have to do try to repeatedly query the legalizer info and guess at what type to use for the shift.
2020-08-16 01:38:29 +08:00
; GFX6: $vgpr0 = COPY %result(s32)
; GFX9-LABEL: name: narrow_shl_s16_by_2_from_zext_s8
; GFX9: liveins: $vgpr0
; GFX9: %argument:_(s32) = COPY $vgpr0
; GFX9: %narrow:_(s8) = G_TRUNC %argument(s32)
; GFX9: %masklow6:_(s8) = G_CONSTANT i8 63
; GFX9: %masked:_(s8) = G_AND %narrow, %masklow6
; GFX9: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 2
; GFX9: [[SHL:%[0-9]+]]:_(s8) = G_SHL %masked, [[C]](s8)
GlobalISel: Add combines for extend operations https://reviews.llvm.org/D86516
2020-09-01 23:50:06 +08:00
; GFX9: %result:_(s32) = G_ZEXT [[SHL]](s8)
GlobalISel: Reduce G_SHL width if source is extension shl ([sza]ext x, y) => zext (shl x, y). Turns expensive 64 bit shifts into 32 bit if it does not overflow the source type: This is a port of an AMDGPU DAG combine added in 5fa289f0d8ff85b9e14d2f814a90761378ab54ae. InstCombine does this already, but we need to do it again here to apply it to shifts introduced for lowered getelementptrs. This will help matching addressing modes that use 32-bit offsets in a future patch. TableGen annoyingly assumes only a single match data operand, so introduce a reusable struct. However, this still requires defining a separate GIMatchData for every combine which is still annoying. Adds a morally equivalent function to the existing getShiftAmountTy. Without this, we would have to do try to repeatedly query the legalizer info and guess at what type to use for the shift.
2020-08-16 01:38:29 +08:00
; GFX9: $vgpr0 = COPY %result(s32)
%argument:_(s32) = COPY $vgpr0
%narrow:_(s8) = G_TRUNC %argument
%masklow6:_(s8) = G_CONSTANT i8 63
%masked:_(s8) = G_AND %narrow, %masklow6
%extend:_(s16) = G_ZEXT %masked
%shiftamt:_(s16) = G_CONSTANT i16 2
%shl:_(s16) = G_SHL %extend, %shiftamt
%result:_(s32) = G_ANYEXT %shl
$vgpr0 = COPY %result
...
---
name: narrow_shl_v2s32_by_2_from_zext_v2s16
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
; GFX6-LABEL: name: narrow_shl_v2s32_by_2_from_zext_v2s16
; GFX6: liveins: $vgpr0
; GFX6: %narrow:_(<2 x s16>) = COPY $vgpr0
; GFX6: %masklow14:_(s16) = G_CONSTANT i16 16383
; GFX6: %masklow14vec:_(<2 x s16>) = G_BUILD_VECTOR %masklow14(s16), %masklow14(s16)
; GFX6: %masked:_(<2 x s16>) = G_AND %narrow, %masklow14vec
; GFX6: %extend:_(<2 x s32>) = G_ZEXT %masked(<2 x s16>)
; GFX6: %shiftamt:_(s32) = G_CONSTANT i32 2
; GFX6: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
; GFX6: %shl:_(<2 x s32>) = G_SHL %extend, %shiftamtvec(<2 x s32>)
; GFX6: $vgpr0_vgpr1 = COPY %shl(<2 x s32>)
; GFX9-LABEL: name: narrow_shl_v2s32_by_2_from_zext_v2s16
; GFX9: liveins: $vgpr0
; GFX9: %narrow:_(<2 x s16>) = COPY $vgpr0
; GFX9: %masklow14:_(s16) = G_CONSTANT i16 16383
; GFX9: %masklow14vec:_(<2 x s16>) = G_BUILD_VECTOR %masklow14(s16), %masklow14(s16)
; GFX9: %masked:_(<2 x s16>) = G_AND %narrow, %masklow14vec
; GFX9: %extend:_(<2 x s32>) = G_ZEXT %masked(<2 x s16>)
; GFX9: %shiftamt:_(s32) = G_CONSTANT i32 2
; GFX9: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
; GFX9: %shl:_(<2 x s32>) = G_SHL %extend, %shiftamtvec(<2 x s32>)
; GFX9: $vgpr0_vgpr1 = COPY %shl(<2 x s32>)
%narrow:_(<2 x s16>) = COPY $vgpr0
%masklow14:_(s16) = G_CONSTANT i16 16383
%masklow14vec:_(<2 x s16>) = G_BUILD_VECTOR %masklow14, %masklow14
%masked:_(<2 x s16>) = G_AND %narrow, %masklow14vec
%extend:_(<2 x s32>) = G_ZEXT %masked
%shiftamt:_(s32) = G_CONSTANT i32 2
%shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt, %shiftamt
%shl:_(<2 x s32>) = G_SHL %extend, %shiftamtvec
$vgpr0_vgpr1 = COPY %shl
...
---
name: narrow_shl_v2s64_by_2_from_anyext_v2s32
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; GFX6-LABEL: name: narrow_shl_v2s64_by_2_from_anyext_v2s32
; GFX6: liveins: $vgpr0_vgpr1
; GFX6: %narrow:_(<2 x s32>) = COPY $vgpr0_vgpr1
; GFX6: %masklow30:_(s32) = G_CONSTANT i32 1073741823
; GFX6: %masklow30vec:_(<2 x s32>) = G_BUILD_VECTOR %masklow30(s32), %masklow30(s32)
; GFX6: %masked:_(<2 x s32>) = G_AND %narrow, %masklow30vec
; GFX6: %extend:_(<2 x s64>) = G_ANYEXT %masked(<2 x s32>)
; GFX6: %shiftamt:_(s32) = G_CONSTANT i32 2
; GFX6: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
; GFX6: %shl:_(<2 x s64>) = G_SHL %extend, %shiftamtvec(<2 x s32>)
; GFX6: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %shl(<2 x s64>)
; GFX9-LABEL: name: narrow_shl_v2s64_by_2_from_anyext_v2s32
; GFX9: liveins: $vgpr0_vgpr1
; GFX9: %narrow:_(<2 x s32>) = COPY $vgpr0_vgpr1
; GFX9: %masklow30:_(s32) = G_CONSTANT i32 1073741823
; GFX9: %masklow30vec:_(<2 x s32>) = G_BUILD_VECTOR %masklow30(s32), %masklow30(s32)
; GFX9: %masked:_(<2 x s32>) = G_AND %narrow, %masklow30vec
; GFX9: %extend:_(<2 x s64>) = G_ANYEXT %masked(<2 x s32>)
; GFX9: %shiftamt:_(s32) = G_CONSTANT i32 2
; GFX9: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
; GFX9: %shl:_(<2 x s64>) = G_SHL %extend, %shiftamtvec(<2 x s32>)
; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %shl(<2 x s64>)
%narrow:_(<2 x s32>) = COPY $vgpr0_vgpr1
%masklow30:_(s32) = G_CONSTANT i32 1073741823
%masklow30vec:_(<2 x s32>) = G_BUILD_VECTOR %masklow30, %masklow30
%masked:_(<2 x s32>) = G_AND %narrow, %masklow30vec
%extend:_(<2 x s64>) = G_ANYEXT %masked
%shiftamt:_(s32) = G_CONSTANT i32 2
%shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt, %shiftamt
%shl:_(<2 x s64>) = G_SHL %extend, %shiftamtvec
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %shl
...