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llvm-project/llvm/test/MC/AArch64/fullfp16-diagnostics.s

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[AArch64] Add ARMv8.2-A FP16 vector instructions ARMv8.2-A adds 16-bit floating point versions of all existing SIMD floating-point instructions. This is an optional extension, so all of these instructions require the FeatureFullFP16 subtarget feature. Note that VFP without SIMD is not a valid combination for any version of ARMv8-A, but I have ensured that these instructions all depend on both FeatureNEON and FeatureFullFP16 for consistency. The ".2h" vector type specifier is now legal (for the scalar pairwise reduction instructions), so some unrelated tests have been modified as different error messages are emitted. This is not a problem as the invalid operands are still caught. llvm-svn: 255010
2015-12-08 20:16:10 +08:00
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon < %s 2> %t
// RUN: FileCheck < %t %s
fmla v0.4h, v1.4h, v16.h[3]
fmla v2.8h, v3.8h, v17.h[6]
// CHECK: error: invalid operand for instruction
// CHECK-NEXT: fmla v0.4h, v1.4h, v16.h[3]
// CHECK-NEXT: ^
// CHECK: error: invalid operand for instruction
// CHECK-NEXT: fmla v2.8h, v3.8h, v17.h[6]
// CHECK-NEXT: ^
fmls v0.4h, v1.4h, v16.h[3]
fmls v2.8h, v3.8h, v17.h[6]
// CHECK: error: invalid operand for instruction
// CHECK-NEXT: fmls v0.4h, v1.4h, v16.h[3]
// CHECK-NEXT: ^
// CHECK: error: invalid operand for instruction
// CHECK-NEXT: fmls v2.8h, v3.8h, v17.h[6]
// CHECK-NEXT: ^
fmul v0.4h, v1.4h, v16.h[3]
fmul v2.8h, v3.8h, v17.h[6]
// CHECK: error: invalid operand for instruction
// CHECK-NEXT: fmul v0.4h, v1.4h, v16.h[3]
// CHECK-NEXT: ^
// CHECK: error: invalid operand for instruction
// CHECK-NEXT: fmul v2.8h, v3.8h, v17.h[6]
// CHECK-NEXT: ^
fmulx v0.4h, v1.4h, v16.h[3]
fmulx v2.8h, v3.8h, v17.h[6]
// CHECK: error: invalid operand for instruction
// CHECK-NEXT: fmulx v0.4h, v1.4h, v16.h[3]
// CHECK-NEXT: ^
// CHECK: error: invalid operand for instruction
// CHECK-NEXT: fmulx v2.8h, v3.8h, v17.h[6]
// CHECK-NEXT: ^