2017-10-11 06:33:29 +08:00
|
|
|
//===- MachineFunction.cpp ------------------------------------------------===//
|
2004-09-06 02:41:35 +08:00
|
|
|
//
|
2019-01-19 16:50:56 +08:00
|
|
|
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
|
|
|
// See https://llvm.org/LICENSE.txt for license information.
|
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|
|
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
2004-09-06 02:41:35 +08:00
|
|
|
//
|
2003-10-21 03:43:21 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
2004-09-06 02:41:35 +08:00
|
|
|
//
|
2002-10-28 09:16:38 +08:00
|
|
|
// Collect native machine code information for a function. This allows
|
|
|
|
// target-specific information about the generated code to be stored with each
|
|
|
|
// function.
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|
|
//
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|
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|
//===----------------------------------------------------------------------===//
|
2002-02-03 15:54:50 +08:00
|
|
|
|
2012-01-27 09:47:28 +08:00
|
|
|
#include "llvm/CodeGen/MachineFunction.h"
|
2017-10-11 06:33:29 +08:00
|
|
|
#include "llvm/ADT/BitVector.h"
|
|
|
|
#include "llvm/ADT/DenseMap.h"
|
|
|
|
#include "llvm/ADT/DenseSet.h"
|
2012-12-04 00:50:05 +08:00
|
|
|
#include "llvm/ADT/STLExtras.h"
|
|
|
|
#include "llvm/ADT/SmallString.h"
|
2017-10-11 06:33:29 +08:00
|
|
|
#include "llvm/ADT/SmallVector.h"
|
|
|
|
#include "llvm/ADT/StringRef.h"
|
|
|
|
#include "llvm/ADT/Twine.h"
|
2012-12-04 00:50:05 +08:00
|
|
|
#include "llvm/Analysis/ConstantFolding.h"
|
2015-12-03 07:06:39 +08:00
|
|
|
#include "llvm/Analysis/EHPersonalities.h"
|
2017-10-11 06:33:29 +08:00
|
|
|
#include "llvm/CodeGen/MachineBasicBlock.h"
|
2007-12-31 12:13:23 +08:00
|
|
|
#include "llvm/CodeGen/MachineConstantPool.h"
|
2002-12-29 05:08:26 +08:00
|
|
|
#include "llvm/CodeGen/MachineFrameInfo.h"
|
2007-12-31 12:13:23 +08:00
|
|
|
#include "llvm/CodeGen/MachineInstr.h"
|
2006-04-23 02:53:45 +08:00
|
|
|
#include "llvm/CodeGen/MachineJumpTableInfo.h"
|
2017-10-11 06:33:29 +08:00
|
|
|
#include "llvm/CodeGen/MachineMemOperand.h"
|
2010-04-05 13:49:50 +08:00
|
|
|
#include "llvm/CodeGen/MachineModuleInfo.h"
|
2007-12-31 12:13:23 +08:00
|
|
|
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
2015-08-12 07:09:45 +08:00
|
|
|
#include "llvm/CodeGen/PseudoSourceValue.h"
|
2017-11-17 09:07:10 +08:00
|
|
|
#include "llvm/CodeGen/TargetFrameLowering.h"
|
2020-03-17 06:56:02 +08:00
|
|
|
#include "llvm/CodeGen/TargetInstrInfo.h"
|
2017-11-17 09:07:10 +08:00
|
|
|
#include "llvm/CodeGen/TargetLowering.h"
|
|
|
|
#include "llvm/CodeGen/TargetRegisterInfo.h"
|
|
|
|
#include "llvm/CodeGen/TargetSubtargetInfo.h"
|
2018-06-19 08:26:39 +08:00
|
|
|
#include "llvm/CodeGen/WasmEHFuncInfo.h"
|
2015-11-18 05:10:25 +08:00
|
|
|
#include "llvm/CodeGen/WinEHFuncInfo.h"
|
2018-04-30 22:59:11 +08:00
|
|
|
#include "llvm/Config/llvm-config.h"
|
2017-10-11 06:33:29 +08:00
|
|
|
#include "llvm/IR/Attributes.h"
|
|
|
|
#include "llvm/IR/BasicBlock.h"
|
|
|
|
#include "llvm/IR/Constant.h"
|
2013-01-02 19:36:10 +08:00
|
|
|
#include "llvm/IR/DataLayout.h"
|
2017-10-11 06:33:29 +08:00
|
|
|
#include "llvm/IR/DerivedTypes.h"
|
2013-01-02 19:36:10 +08:00
|
|
|
#include "llvm/IR/Function.h"
|
2017-10-11 06:33:29 +08:00
|
|
|
#include "llvm/IR/GlobalValue.h"
|
|
|
|
#include "llvm/IR/Instruction.h"
|
|
|
|
#include "llvm/IR/Instructions.h"
|
|
|
|
#include "llvm/IR/Metadata.h"
|
2015-07-08 02:20:57 +08:00
|
|
|
#include "llvm/IR/Module.h"
|
2015-06-27 06:04:20 +08:00
|
|
|
#include "llvm/IR/ModuleSlotTracker.h"
|
2017-10-11 06:33:29 +08:00
|
|
|
#include "llvm/IR/Value.h"
|
2010-01-26 13:58:28 +08:00
|
|
|
#include "llvm/MC/MCContext.h"
|
2017-10-11 06:33:29 +08:00
|
|
|
#include "llvm/MC/MCSymbol.h"
|
|
|
|
#include "llvm/MC/SectionKind.h"
|
|
|
|
#include "llvm/Support/Casting.h"
|
|
|
|
#include "llvm/Support/CommandLine.h"
|
|
|
|
#include "llvm/Support/Compiler.h"
|
|
|
|
#include "llvm/Support/DOTGraphTraits.h"
|
|
|
|
#include "llvm/Support/ErrorHandling.h"
|
2006-10-04 04:19:23 +08:00
|
|
|
#include "llvm/Support/GraphWriter.h"
|
2008-08-24 06:23:09 +08:00
|
|
|
#include "llvm/Support/raw_ostream.h"
|
2012-12-04 00:50:05 +08:00
|
|
|
#include "llvm/Target/TargetMachine.h"
|
2017-10-11 06:33:29 +08:00
|
|
|
#include <algorithm>
|
|
|
|
#include <cassert>
|
|
|
|
#include <cstddef>
|
|
|
|
#include <cstdint>
|
|
|
|
#include <iterator>
|
|
|
|
#include <string>
|
2020-03-17 06:56:02 +08:00
|
|
|
#include <type_traits>
|
2017-10-11 06:33:29 +08:00
|
|
|
#include <utility>
|
|
|
|
#include <vector>
|
|
|
|
|
2022-01-12 20:35:36 +08:00
|
|
|
#include "LiveDebugValues/LiveDebugValues.h"
|
|
|
|
|
2003-12-20 17:17:07 +08:00
|
|
|
using namespace llvm;
|
2002-02-03 15:54:50 +08:00
|
|
|
|
2014-04-22 06:55:11 +08:00
|
|
|
#define DEBUG_TYPE "codegen"
|
|
|
|
|
[LLVM][Alignment] Make functions using log of alignment explicit
Summary:
This patch renames functions that takes or returns alignment as log2, this patch will help with the transition to llvm::Align.
The renaming makes it explicit that we deal with log(alignment) instead of a power of two alignment.
A few renames uncovered dubious assignments:
- `MirParser`/`MirPrinter` was expecting powers of two but `MachineFunction` and `MachineBasicBlock` were using deal with log2(align). This patch fixes it and updates the documentation.
- `MachineBlockPlacement` exposes two flags (`align-all-blocks` and `align-all-nofallthru-blocks`) supposedly interpreted as power of two alignments, internally these values are interpreted as log2(align). This patch updates the documentation,
- `MachineFunctionexposes` exposes `align-all-functions` also interpreted as power of two alignment, internally this value is interpreted as log2(align). This patch updates the documentation,
Reviewers: lattner, thegameg, courbet
Subscribers: dschuff, arsenm, jyknight, dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, javed.absar, hiraditya, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, dexonsmith, PkmX, jocewei, jsji, Jim, s.egerton, llvm-commits, courbet
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65945
llvm-svn: 371045
2019-09-05 18:00:22 +08:00
|
|
|
static cl::opt<unsigned> AlignAllFunctions(
|
|
|
|
"align-all-functions",
|
|
|
|
cl::desc("Force the alignment of all functions in log2 format (e.g. 4 "
|
|
|
|
"means align on 16B boundaries)."),
|
|
|
|
cl::init(0), cl::Hidden);
|
2015-12-30 02:18:07 +08:00
|
|
|
|
2016-08-20 06:31:45 +08:00
|
|
|
static const char *getPropertyName(MachineFunctionProperties::Property Prop) {
|
2017-10-11 06:33:29 +08:00
|
|
|
using P = MachineFunctionProperties::Property;
|
|
|
|
|
2021-12-06 03:55:20 +08:00
|
|
|
// clang-format off
|
2016-08-20 06:31:45 +08:00
|
|
|
switch(Prop) {
|
2016-08-27 07:49:01 +08:00
|
|
|
case P::FailedISel: return "FailedISel";
|
2016-08-20 06:31:45 +08:00
|
|
|
case P::IsSSA: return "IsSSA";
|
|
|
|
case P::Legalized: return "Legalized";
|
2016-08-24 05:19:49 +08:00
|
|
|
case P::NoPHIs: return "NoPHIs";
|
2016-08-25 09:27:13 +08:00
|
|
|
case P::NoVRegs: return "NoVRegs";
|
2016-08-20 06:31:45 +08:00
|
|
|
case P::RegBankSelected: return "RegBankSelected";
|
|
|
|
case P::Selected: return "Selected";
|
|
|
|
case P::TracksLiveness: return "TracksLiveness";
|
2020-06-09 15:39:42 +08:00
|
|
|
case P::TiedOpsRewritten: return "TiedOpsRewritten";
|
2021-10-15 18:26:48 +08:00
|
|
|
case P::FailsVerification: return "FailsVerification";
|
2021-12-06 03:55:20 +08:00
|
|
|
case P::TracksDebugUserValues: return "TracksDebugUserValues";
|
2016-08-20 06:31:45 +08:00
|
|
|
}
|
2021-12-06 03:55:20 +08:00
|
|
|
// clang-format on
|
2016-08-20 07:03:28 +08:00
|
|
|
llvm_unreachable("Invalid machine function property");
|
2016-08-20 06:31:45 +08:00
|
|
|
}
|
|
|
|
|
2022-04-20 00:34:23 +08:00
|
|
|
void setUnsafeStackSize(const Function &F, MachineFrameInfo &FrameInfo) {
|
|
|
|
if (!F.hasFnAttribute(Attribute::SafeStack))
|
|
|
|
return;
|
|
|
|
|
|
|
|
auto *Existing =
|
|
|
|
dyn_cast_or_null<MDTuple>(F.getMetadata(LLVMContext::MD_annotation));
|
|
|
|
|
|
|
|
if (!Existing || Existing->getNumOperands() != 2)
|
|
|
|
return;
|
|
|
|
|
|
|
|
auto *MetadataName = "unsafe-stack-size";
|
|
|
|
if (auto &N = Existing->getOperand(0)) {
|
|
|
|
if (cast<MDString>(N.get())->getString() == MetadataName) {
|
|
|
|
if (auto &Op = Existing->getOperand(1)) {
|
|
|
|
auto Val = mdconst::extract<ConstantInt>(Op)->getZExtValue();
|
|
|
|
FrameInfo.setUnsafeStackSize(Val);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-09-21 07:01:56 +08:00
|
|
|
// Pin the vtable to this file.
|
|
|
|
void MachineFunction::Delegate::anchor() {}
|
|
|
|
|
2016-08-20 06:31:45 +08:00
|
|
|
void MachineFunctionProperties::print(raw_ostream &OS) const {
|
|
|
|
const char *Separator = "";
|
|
|
|
for (BitVector::size_type I = 0; I < Properties.size(); ++I) {
|
|
|
|
if (!Properties[I])
|
2016-04-22 06:19:24 +08:00
|
|
|
continue;
|
2016-08-20 06:31:45 +08:00
|
|
|
OS << Separator << getPropertyName(static_cast<Property>(I));
|
|
|
|
Separator = ", ";
|
2016-03-30 04:28:20 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-01-26 12:35:26 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
2002-10-28 09:12:41 +08:00
|
|
|
// MachineFunction implementation
|
2010-01-26 12:35:26 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
2005-01-30 02:41:25 +08:00
|
|
|
|
2015-06-13 23:32:45 +08:00
|
|
|
// Out-of-line virtual method.
|
2017-10-11 06:33:29 +08:00
|
|
|
MachineFunctionInfo::~MachineFunctionInfo() = default;
|
2009-09-16 06:44:26 +08:00
|
|
|
|
2016-08-31 02:40:47 +08:00
|
|
|
void ilist_alloc_traits<MachineBasicBlock>::deleteNode(MachineBasicBlock *MBB) {
|
2021-12-09 09:36:37 +08:00
|
|
|
MBB->getParent()->deleteMachineBasicBlock(MBB);
|
2004-05-24 14:11:51 +08:00
|
|
|
}
|
2002-10-28 09:12:41 +08:00
|
|
|
|
2016-04-10 07:34:42 +08:00
|
|
|
static inline unsigned getFnStackAlignment(const TargetSubtargetInfo *STI,
|
2017-12-16 06:22:46 +08:00
|
|
|
const Function &F) {
|
2021-08-19 01:43:17 +08:00
|
|
|
if (auto MA = F.getFnStackAlign())
|
|
|
|
return MA->value();
|
[Alignment][NFC] Use TFL::getStackAlign()
Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790
Reviewers: courbet
Subscribers: dylanmckay, sdardis, nemanjai, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, Jim, lenary, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D76551
2020-03-22 04:41:33 +08:00
|
|
|
return STI->getFrameLowering()->getStackAlign().value();
|
2016-04-10 07:34:42 +08:00
|
|
|
}
|
|
|
|
|
2020-04-04 06:55:15 +08:00
|
|
|
MachineFunction::MachineFunction(Function &F, const LLVMTargetMachine &Target,
|
2017-12-16 06:22:46 +08:00
|
|
|
const TargetSubtargetInfo &STI,
|
2014-10-15 02:53:16 +08:00
|
|
|
unsigned FunctionNum, MachineModuleInfo &mmi)
|
2017-12-16 06:22:46 +08:00
|
|
|
: F(F), Target(Target), STI(&STI), Ctx(mmi.getContext()), MMI(mmi) {
|
2016-08-27 06:32:53 +08:00
|
|
|
FunctionNumber = FunctionNum;
|
|
|
|
init();
|
|
|
|
}
|
|
|
|
|
2019-01-16 08:40:37 +08:00
|
|
|
void MachineFunction::handleInsertion(MachineInstr &MI) {
|
2018-09-21 07:01:56 +08:00
|
|
|
if (TheDelegate)
|
|
|
|
TheDelegate->MF_HandleInsertion(MI);
|
|
|
|
}
|
|
|
|
|
2019-01-16 08:40:37 +08:00
|
|
|
void MachineFunction::handleRemoval(MachineInstr &MI) {
|
2018-09-21 07:01:56 +08:00
|
|
|
if (TheDelegate)
|
|
|
|
TheDelegate->MF_HandleRemoval(MI);
|
|
|
|
}
|
|
|
|
|
2016-08-27 06:32:53 +08:00
|
|
|
void MachineFunction::init() {
|
2016-04-12 07:32:13 +08:00
|
|
|
// Assume the function starts in SSA form with correct liveness.
|
2016-04-05 02:03:29 +08:00
|
|
|
Properties.set(MachineFunctionProperties::Property::IsSSA);
|
2016-04-12 07:32:13 +08:00
|
|
|
Properties.set(MachineFunctionProperties::Property::TracksLiveness);
|
2014-10-08 15:51:41 +08:00
|
|
|
if (STI->getRegisterInfo())
|
2014-08-12 16:00:56 +08:00
|
|
|
RegInfo = new (Allocator) MachineRegisterInfo(this);
|
2008-10-13 20:37:16 +08:00
|
|
|
else
|
2014-04-14 08:51:57 +08:00
|
|
|
RegInfo = nullptr;
|
2013-06-18 04:41:25 +08:00
|
|
|
|
2014-04-14 08:51:57 +08:00
|
|
|
MFInfo = nullptr;
|
2016-04-12 01:54:03 +08:00
|
|
|
// We can realign the stack if the target supports it and the user hasn't
|
|
|
|
// explicitly asked us not to.
|
|
|
|
bool CanRealignSP = STI->getFrameLowering()->isStackRealignable() &&
|
2017-12-16 06:22:46 +08:00
|
|
|
!F.hasFnAttribute("no-realign-stack");
|
2016-04-12 01:54:03 +08:00
|
|
|
FrameInfo = new (Allocator) MachineFrameInfo(
|
2017-12-16 06:22:46 +08:00
|
|
|
getFnStackAlignment(STI, F), /*StackRealignable=*/CanRealignSP,
|
2019-07-16 12:46:31 +08:00
|
|
|
/*ForcedRealign=*/CanRealignSP &&
|
2017-12-16 06:22:46 +08:00
|
|
|
F.hasFnAttribute(Attribute::StackAlignment));
|
2013-06-18 04:41:25 +08:00
|
|
|
|
2022-04-20 00:34:23 +08:00
|
|
|
setUnsafeStackSize(F, *FrameInfo);
|
|
|
|
|
2017-12-16 06:22:46 +08:00
|
|
|
if (F.hasFnAttribute(Attribute::StackAlignment))
|
2020-03-19 00:04:10 +08:00
|
|
|
FrameInfo->ensureMaxAlignment(*F.getFnStackAlign());
|
2013-06-18 04:41:25 +08:00
|
|
|
|
2015-07-08 02:20:57 +08:00
|
|
|
ConstantPool = new (Allocator) MachineConstantPool(getDataLayout());
|
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
Summary:
This catches malformed mir files which specify alignment as log2 instead of pow2.
See https://reviews.llvm.org/D65945 for reference,
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790
Reviewers: courbet
Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67433
llvm-svn: 371608
2019-09-11 19:16:48 +08:00
|
|
|
Alignment = STI->getTargetLowering()->getMinFunctionAlignment();
|
2013-06-18 04:41:25 +08:00
|
|
|
|
2017-12-16 06:22:46 +08:00
|
|
|
// FIXME: Shouldn't use pref alignment if explicit alignment is set on F.
|
2019-04-05 06:40:06 +08:00
|
|
|
// FIXME: Use Function::hasOptSize().
|
2017-12-16 06:22:46 +08:00
|
|
|
if (!F.hasFnAttribute(Attribute::OptimizeForSize))
|
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
Summary:
This catches malformed mir files which specify alignment as log2 instead of pow2.
See https://reviews.llvm.org/D65945 for reference,
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790
Reviewers: courbet
Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67433
llvm-svn: 371608
2019-09-11 19:16:48 +08:00
|
|
|
Alignment = std::max(Alignment,
|
|
|
|
STI->getTargetLowering()->getPrefFunctionAlignment());
|
2013-06-18 04:41:25 +08:00
|
|
|
|
2015-12-30 02:18:07 +08:00
|
|
|
if (AlignAllFunctions)
|
2019-09-27 20:54:21 +08:00
|
|
|
Alignment = Align(1ULL << AlignAllFunctions);
|
2015-12-30 02:18:07 +08:00
|
|
|
|
2014-04-14 08:51:57 +08:00
|
|
|
JumpTableInfo = nullptr;
|
2015-08-17 18:58:03 +08:00
|
|
|
|
2015-11-18 05:10:25 +08:00
|
|
|
if (isFuncletEHPersonality(classifyEHPersonality(
|
2017-12-16 06:22:46 +08:00
|
|
|
F.hasPersonalityFn() ? F.getPersonalityFn() : nullptr))) {
|
2015-11-18 05:10:25 +08:00
|
|
|
WinEHInfo = new (Allocator) WinEHFuncInfo();
|
|
|
|
}
|
|
|
|
|
2018-06-19 08:26:39 +08:00
|
|
|
if (isScopedEHPersonality(classifyEHPersonality(
|
|
|
|
F.hasPersonalityFn() ? F.getPersonalityFn() : nullptr))) {
|
|
|
|
WasmEHInfo = new (Allocator) WasmEHFuncInfo();
|
|
|
|
}
|
|
|
|
|
2016-08-27 06:32:53 +08:00
|
|
|
assert(Target.isCompatibleDataLayout(getDataLayout()) &&
|
2015-08-17 18:58:03 +08:00
|
|
|
"Can't create a MachineFunction using a Module with a "
|
|
|
|
"Target-incompatible DataLayout attached\n");
|
|
|
|
|
2017-09-15 04:53:51 +08:00
|
|
|
PSVManager =
|
2019-08-15 23:54:37 +08:00
|
|
|
std::make_unique<PseudoSourceValueManager>(*(getSubtarget().
|
2017-09-15 04:53:51 +08:00
|
|
|
getInstrInfo()));
|
2002-12-25 13:03:22 +08:00
|
|
|
}
|
|
|
|
|
2004-09-06 02:41:35 +08:00
|
|
|
MachineFunction::~MachineFunction() {
|
2016-08-27 06:32:53 +08:00
|
|
|
clear();
|
|
|
|
}
|
|
|
|
|
|
|
|
void MachineFunction::clear() {
|
|
|
|
Properties.reset();
|
2013-01-05 13:05:51 +08:00
|
|
|
// Don't call destructors on MachineInstr and MachineOperand. All of their
|
|
|
|
// memory comes from the BumpPtrAllocator which is about to be purged.
|
|
|
|
//
|
|
|
|
// Do call MachineBasicBlock destructors, it contains std::vectors.
|
|
|
|
for (iterator I = begin(), E = end(); I != E; I = BasicBlocks.erase(I))
|
|
|
|
I->Insts.clearAndLeakNodesUnsafely();
|
2018-05-01 02:58:57 +08:00
|
|
|
MBBNumbering.clear();
|
2013-01-05 13:05:51 +08:00
|
|
|
|
2008-07-08 07:14:23 +08:00
|
|
|
InstructionRecycler.clear(Allocator);
|
2013-01-05 13:00:09 +08:00
|
|
|
OperandRecycler.clear(Allocator);
|
2008-07-08 07:14:23 +08:00
|
|
|
BasicBlockRecycler.clear(Allocator);
|
2017-09-06 04:14:58 +08:00
|
|
|
CodeViewAnnotations.clear();
|
2017-03-10 05:12:06 +08:00
|
|
|
VariableDbgInfos.clear();
|
2009-06-25 08:32:48 +08:00
|
|
|
if (RegInfo) {
|
|
|
|
RegInfo->~MachineRegisterInfo();
|
|
|
|
Allocator.Deallocate(RegInfo);
|
|
|
|
}
|
2008-07-08 07:14:23 +08:00
|
|
|
if (MFInfo) {
|
2009-06-25 08:32:48 +08:00
|
|
|
MFInfo->~MachineFunctionInfo();
|
|
|
|
Allocator.Deallocate(MFInfo);
|
2008-07-08 07:14:23 +08:00
|
|
|
}
|
2012-06-20 07:37:57 +08:00
|
|
|
|
|
|
|
FrameInfo->~MachineFrameInfo();
|
|
|
|
Allocator.Deallocate(FrameInfo);
|
|
|
|
|
|
|
|
ConstantPool->~MachineConstantPool();
|
|
|
|
Allocator.Deallocate(ConstantPool);
|
|
|
|
|
2010-01-26 07:26:13 +08:00
|
|
|
if (JumpTableInfo) {
|
|
|
|
JumpTableInfo->~MachineJumpTableInfo();
|
|
|
|
Allocator.Deallocate(JumpTableInfo);
|
|
|
|
}
|
2015-11-18 05:10:25 +08:00
|
|
|
|
|
|
|
if (WinEHInfo) {
|
|
|
|
WinEHInfo->~WinEHFuncInfo();
|
|
|
|
Allocator.Deallocate(WinEHInfo);
|
|
|
|
}
|
2018-09-29 04:54:04 +08:00
|
|
|
|
|
|
|
if (WasmEHInfo) {
|
|
|
|
WasmEHInfo->~WasmEHFuncInfo();
|
|
|
|
Allocator.Deallocate(WasmEHInfo);
|
|
|
|
}
|
2002-10-30 08:48:05 +08:00
|
|
|
}
|
|
|
|
|
2015-07-08 02:20:57 +08:00
|
|
|
const DataLayout &MachineFunction::getDataLayout() const {
|
2017-12-16 06:22:46 +08:00
|
|
|
return F.getParent()->getDataLayout();
|
2015-07-08 02:20:57 +08:00
|
|
|
}
|
|
|
|
|
2015-06-13 23:32:45 +08:00
|
|
|
/// Get the JumpTableInfo for this function.
|
|
|
|
/// If it does not already exist, allocate one.
|
2010-01-26 07:26:13 +08:00
|
|
|
MachineJumpTableInfo *MachineFunction::
|
|
|
|
getOrCreateJumpTableInfo(unsigned EntryKind) {
|
|
|
|
if (JumpTableInfo) return JumpTableInfo;
|
2012-06-20 07:37:57 +08:00
|
|
|
|
2010-03-19 02:49:47 +08:00
|
|
|
JumpTableInfo = new (Allocator)
|
2010-01-26 07:26:13 +08:00
|
|
|
MachineJumpTableInfo((MachineJumpTableInfo::JTEntryKind)EntryKind);
|
|
|
|
return JumpTableInfo;
|
|
|
|
}
|
2006-10-04 03:18:57 +08:00
|
|
|
|
2019-10-30 07:16:05 +08:00
|
|
|
DenormalMode MachineFunction::getDenormalMode(const fltSemantics &FPType) const {
|
2020-09-18 05:50:42 +08:00
|
|
|
return F.getDenormalMode(FPType);
|
2019-10-30 07:16:05 +08:00
|
|
|
}
|
|
|
|
|
2014-04-11 06:58:43 +08:00
|
|
|
/// Should we be emitting segmented stack stuff for the function
|
2016-01-20 06:31:12 +08:00
|
|
|
bool MachineFunction::shouldSplitStack() const {
|
2017-12-16 06:22:58 +08:00
|
|
|
return getFunction().hasFnAttribute("split-stack");
|
2014-04-11 06:58:43 +08:00
|
|
|
}
|
|
|
|
|
2019-04-12 14:31:59 +08:00
|
|
|
LLVM_NODISCARD unsigned
|
|
|
|
MachineFunction::addFrameInst(const MCCFIInstruction &Inst) {
|
|
|
|
FrameInstructions.push_back(Inst);
|
|
|
|
return FrameInstructions.size() - 1;
|
|
|
|
}
|
|
|
|
|
2015-06-13 23:32:45 +08:00
|
|
|
/// This discards all of the MachineBasicBlock numbers and recomputes them.
|
|
|
|
/// This guarantees that the MBB numbers are sequential, dense, and match the
|
|
|
|
/// ordering of the blocks within the function. If a specific MachineBasicBlock
|
|
|
|
/// is specified, only that block and those after it are renumbered.
|
2006-10-04 03:18:57 +08:00
|
|
|
void MachineFunction::RenumberBlocks(MachineBasicBlock *MBB) {
|
|
|
|
if (empty()) { MBBNumbering.clear(); return; }
|
|
|
|
MachineFunction::iterator MBBI, E = end();
|
2014-04-14 08:51:57 +08:00
|
|
|
if (MBB == nullptr)
|
2006-10-04 03:18:57 +08:00
|
|
|
MBBI = begin();
|
|
|
|
else
|
2015-10-10 03:40:45 +08:00
|
|
|
MBBI = MBB->getIterator();
|
2012-06-20 07:37:57 +08:00
|
|
|
|
2006-10-04 03:18:57 +08:00
|
|
|
// Figure out the block number this should have.
|
|
|
|
unsigned BlockNo = 0;
|
2006-10-04 04:19:23 +08:00
|
|
|
if (MBBI != begin())
|
2014-03-02 20:27:27 +08:00
|
|
|
BlockNo = std::prev(MBBI)->getNumber() + 1;
|
2012-06-20 07:37:57 +08:00
|
|
|
|
2006-10-04 03:18:57 +08:00
|
|
|
for (; MBBI != E; ++MBBI, ++BlockNo) {
|
|
|
|
if (MBBI->getNumber() != (int)BlockNo) {
|
|
|
|
// Remove use of the old number.
|
|
|
|
if (MBBI->getNumber() != -1) {
|
|
|
|
assert(MBBNumbering[MBBI->getNumber()] == &*MBBI &&
|
|
|
|
"MBB number mismatch!");
|
2014-04-14 08:51:57 +08:00
|
|
|
MBBNumbering[MBBI->getNumber()] = nullptr;
|
2006-10-04 03:18:57 +08:00
|
|
|
}
|
2012-06-20 07:37:57 +08:00
|
|
|
|
2006-10-04 03:18:57 +08:00
|
|
|
// If BlockNo is already taken, set that block's number to -1.
|
|
|
|
if (MBBNumbering[BlockNo])
|
|
|
|
MBBNumbering[BlockNo]->setNumber(-1);
|
|
|
|
|
2015-10-10 03:40:45 +08:00
|
|
|
MBBNumbering[BlockNo] = &*MBBI;
|
2006-10-04 03:18:57 +08:00
|
|
|
MBBI->setNumber(BlockNo);
|
|
|
|
}
|
2012-06-20 07:37:57 +08:00
|
|
|
}
|
2006-10-04 03:18:57 +08:00
|
|
|
|
|
|
|
// Okay, all the blocks are renumbered. If we have compactified the block
|
|
|
|
// numbering, shrink MBBNumbering now.
|
|
|
|
assert(BlockNo <= MBBNumbering.size() && "Mismatch!");
|
|
|
|
MBBNumbering.resize(BlockNo);
|
|
|
|
}
|
|
|
|
|
2020-04-14 03:14:42 +08:00
|
|
|
/// This method iterates over the basic blocks and assigns their IsBeginSection
|
|
|
|
/// and IsEndSection fields. This must be called after MBB layout is finalized
|
|
|
|
/// and the SectionID's are assigned to MBBs.
|
|
|
|
void MachineFunction::assignBeginEndSections() {
|
|
|
|
front().setIsBeginSection();
|
|
|
|
auto CurrentSectionID = front().getSectionID();
|
|
|
|
for (auto MBBI = std::next(begin()), E = end(); MBBI != E; ++MBBI) {
|
|
|
|
if (MBBI->getSectionID() == CurrentSectionID)
|
|
|
|
continue;
|
|
|
|
MBBI->setIsBeginSection();
|
|
|
|
std::prev(MBBI)->setIsEndSection();
|
|
|
|
CurrentSectionID = MBBI->getSectionID();
|
|
|
|
}
|
|
|
|
back().setIsEndSection();
|
|
|
|
}
|
|
|
|
|
2015-06-13 23:32:45 +08:00
|
|
|
/// Allocate a new MachineInstr. Use this instead of `new MachineInstr'.
|
2016-06-12 23:39:02 +08:00
|
|
|
MachineInstr *MachineFunction::CreateMachineInstr(const MCInstrDesc &MCID,
|
2021-12-07 09:33:13 +08:00
|
|
|
DebugLoc DL,
|
2020-09-20 11:41:25 +08:00
|
|
|
bool NoImplicit) {
|
2008-07-08 07:14:23 +08:00
|
|
|
return new (InstructionRecycler.Allocate<MachineInstr>(Allocator))
|
2021-12-07 09:33:13 +08:00
|
|
|
MachineInstr(*this, MCID, std::move(DL), NoImplicit);
|
2008-07-08 07:14:23 +08:00
|
|
|
}
|
|
|
|
|
2015-06-13 23:32:45 +08:00
|
|
|
/// Create a new MachineInstr which is a copy of the 'Orig' instruction,
|
|
|
|
/// identical in all ways except the instruction has no parent, prev, or next.
|
2008-07-08 07:14:23 +08:00
|
|
|
MachineInstr *
|
|
|
|
MachineFunction::CloneMachineInstr(const MachineInstr *Orig) {
|
|
|
|
return new (InstructionRecycler.Allocate<MachineInstr>(Allocator))
|
|
|
|
MachineInstr(*this, *Orig);
|
|
|
|
}
|
|
|
|
|
2021-12-09 13:12:54 +08:00
|
|
|
MachineInstr &MachineFunction::cloneMachineInstrBundle(
|
|
|
|
MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore,
|
|
|
|
const MachineInstr &Orig) {
|
2017-08-23 07:56:30 +08:00
|
|
|
MachineInstr *FirstClone = nullptr;
|
|
|
|
MachineBasicBlock::const_instr_iterator I = Orig.getIterator();
|
2017-10-11 06:33:29 +08:00
|
|
|
while (true) {
|
2017-08-23 07:56:30 +08:00
|
|
|
MachineInstr *Cloned = CloneMachineInstr(&*I);
|
|
|
|
MBB.insert(InsertBefore, Cloned);
|
|
|
|
if (FirstClone == nullptr) {
|
|
|
|
FirstClone = Cloned;
|
|
|
|
} else {
|
|
|
|
Cloned->bundleWithPred();
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!I->isBundledWithSucc())
|
|
|
|
break;
|
|
|
|
++I;
|
|
|
|
}
|
2020-04-08 04:09:29 +08:00
|
|
|
// Copy over call site info to the cloned instruction if needed. If Orig is in
|
|
|
|
// a bundle, copyCallSiteInfo takes care of finding the call instruction in
|
|
|
|
// the bundle.
|
|
|
|
if (Orig.shouldUpdateCallSiteInfo())
|
|
|
|
copyCallSiteInfo(&Orig, FirstClone);
|
2017-08-23 07:56:30 +08:00
|
|
|
return *FirstClone;
|
|
|
|
}
|
|
|
|
|
2015-06-13 23:32:45 +08:00
|
|
|
/// Delete the given MachineInstr.
|
2008-07-08 07:14:23 +08:00
|
|
|
///
|
2013-01-05 13:05:51 +08:00
|
|
|
/// This function also serves as the MachineInstr destructor - the real
|
|
|
|
/// ~MachineInstr() destructor must be empty.
|
2021-12-09 12:35:33 +08:00
|
|
|
void MachineFunction::deleteMachineInstr(MachineInstr *MI) {
|
2019-06-27 21:10:29 +08:00
|
|
|
// Verify that a call site info is at valid state. This assertion should
|
|
|
|
// be triggered during the implementation of support for the
|
|
|
|
// call site info of a new architecture. If the assertion is triggered,
|
|
|
|
// back trace will tell where to insert a call to updateCallSiteInfo().
|
2020-02-27 18:44:53 +08:00
|
|
|
assert((!MI->isCandidateForCallSiteEntry() ||
|
2019-06-27 21:10:29 +08:00
|
|
|
CallSitesInfo.find(MI) == CallSitesInfo.end()) &&
|
|
|
|
"Call site info was not updated!");
|
2013-01-05 13:00:09 +08:00
|
|
|
// Strip it for parts. The operand array and the MI object itself are
|
|
|
|
// independently recyclable.
|
|
|
|
if (MI->Operands)
|
|
|
|
deallocateOperandArray(MI->CapOperands, MI->Operands);
|
2013-01-05 13:05:51 +08:00
|
|
|
// Don't call ~MachineInstr() which must be trivial anyway because
|
|
|
|
// ~MachineFunction drops whole lists of MachineInstrs wihout calling their
|
|
|
|
// destructors.
|
2008-07-08 07:14:23 +08:00
|
|
|
InstructionRecycler.Deallocate(Allocator, MI);
|
|
|
|
}
|
|
|
|
|
2015-06-13 23:32:45 +08:00
|
|
|
/// Allocate a new MachineBasicBlock. Use this instead of
|
|
|
|
/// `new MachineBasicBlock'.
|
2008-07-08 07:14:23 +08:00
|
|
|
MachineBasicBlock *
|
|
|
|
MachineFunction::CreateMachineBasicBlock(const BasicBlock *bb) {
|
|
|
|
return new (BasicBlockRecycler.Allocate<MachineBasicBlock>(Allocator))
|
|
|
|
MachineBasicBlock(*this, bb);
|
|
|
|
}
|
2006-10-04 03:18:57 +08:00
|
|
|
|
2015-06-13 23:32:45 +08:00
|
|
|
/// Delete the given MachineBasicBlock.
|
2021-12-09 09:36:37 +08:00
|
|
|
void MachineFunction::deleteMachineBasicBlock(MachineBasicBlock *MBB) {
|
2008-07-08 07:14:23 +08:00
|
|
|
assert(MBB->getParent() == this && "MBB parent mismatch!");
|
2020-11-17 00:33:06 +08:00
|
|
|
// Clean up any references to MBB in jump tables before deleting it.
|
|
|
|
if (JumpTableInfo)
|
|
|
|
JumpTableInfo->RemoveMBBFromJumpTables(MBB);
|
2008-07-08 07:14:23 +08:00
|
|
|
MBB->~MachineBasicBlock();
|
|
|
|
BasicBlockRecycler.Deallocate(Allocator, MBB);
|
|
|
|
}
|
|
|
|
|
2016-07-16 02:26:59 +08:00
|
|
|
MachineMemOperand *MachineFunction::getMachineMemOperand(
|
|
|
|
MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s,
|
2020-03-30 17:38:44 +08:00
|
|
|
Align base_alignment, const AAMDNodes &AAInfo, const MDNode *Ranges,
|
2017-07-12 06:23:00 +08:00
|
|
|
SyncScope::ID SSID, AtomicOrdering Ordering,
|
2016-10-16 06:01:18 +08:00
|
|
|
AtomicOrdering FailureOrdering) {
|
2016-07-15 01:07:44 +08:00
|
|
|
return new (Allocator)
|
2016-10-16 06:01:18 +08:00
|
|
|
MachineMemOperand(PtrInfo, f, s, base_alignment, AAInfo, Ranges,
|
2017-07-12 06:23:00 +08:00
|
|
|
SSID, Ordering, FailureOrdering);
|
2009-09-26 04:36:54 +08:00
|
|
|
}
|
|
|
|
|
2021-05-20 10:06:14 +08:00
|
|
|
MachineMemOperand *MachineFunction::getMachineMemOperand(
|
|
|
|
MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy,
|
|
|
|
Align base_alignment, const AAMDNodes &AAInfo, const MDNode *Ranges,
|
|
|
|
SyncScope::ID SSID, AtomicOrdering Ordering,
|
|
|
|
AtomicOrdering FailureOrdering) {
|
|
|
|
return new (Allocator)
|
|
|
|
MachineMemOperand(PtrInfo, f, MemTy, base_alignment, AAInfo, Ranges, SSID,
|
|
|
|
Ordering, FailureOrdering);
|
|
|
|
}
|
|
|
|
|
2020-07-14 20:50:21 +08:00
|
|
|
MachineMemOperand *MachineFunction::getMachineMemOperand(
|
2021-06-09 05:10:51 +08:00
|
|
|
const MachineMemOperand *MMO, const MachinePointerInfo &PtrInfo, uint64_t Size) {
|
2021-06-22 07:34:02 +08:00
|
|
|
return new (Allocator)
|
|
|
|
MachineMemOperand(PtrInfo, MMO->getFlags(), Size, MMO->getBaseAlign(),
|
|
|
|
AAMDNodes(), nullptr, MMO->getSyncScopeID(),
|
|
|
|
MMO->getSuccessOrdering(), MMO->getFailureOrdering());
|
2020-07-14 20:50:21 +08:00
|
|
|
}
|
|
|
|
|
2021-05-20 10:06:14 +08:00
|
|
|
MachineMemOperand *MachineFunction::getMachineMemOperand(
|
|
|
|
const MachineMemOperand *MMO, const MachinePointerInfo &PtrInfo, LLT Ty) {
|
|
|
|
return new (Allocator)
|
|
|
|
MachineMemOperand(PtrInfo, MMO->getFlags(), Ty, MMO->getBaseAlign(),
|
|
|
|
AAMDNodes(), nullptr, MMO->getSyncScopeID(),
|
|
|
|
MMO->getSuccessOrdering(), MMO->getFailureOrdering());
|
|
|
|
}
|
|
|
|
|
2009-09-26 04:36:54 +08:00
|
|
|
MachineMemOperand *
|
|
|
|
MachineFunction::getMachineMemOperand(const MachineMemOperand *MMO,
|
2021-05-20 10:06:14 +08:00
|
|
|
int64_t Offset, LLT Ty) {
|
2019-01-31 09:49:58 +08:00
|
|
|
const MachinePointerInfo &PtrInfo = MMO->getPointerInfo();
|
|
|
|
|
|
|
|
// If there is no pointer value, the offset isn't tracked so we need to adjust
|
|
|
|
// the base alignment.
|
[Alignment][NFC] MachineMemOperand::getAlign/getBaseAlign
Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790
Reviewers: courbet
Subscribers: arsenm, dschuff, sdardis, nemanjai, jvesely, nhaehnle, sbc100, jgravelle-google, hiraditya, aheejin, kbarton, jrtc27, atanasyan, jfb, kerbowa, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D76925
2020-03-27 21:51:59 +08:00
|
|
|
Align Alignment = PtrInfo.V.isNull()
|
|
|
|
? commonAlignment(MMO->getBaseAlign(), Offset)
|
|
|
|
: MMO->getBaseAlign();
|
2019-01-31 09:49:58 +08:00
|
|
|
|
2020-08-09 00:22:40 +08:00
|
|
|
// Do not preserve ranges, since we don't necessarily know what the high bits
|
|
|
|
// are anymore.
|
2021-06-22 07:34:02 +08:00
|
|
|
return new (Allocator) MachineMemOperand(
|
2021-05-20 10:06:14 +08:00
|
|
|
PtrInfo.getWithOffset(Offset), MMO->getFlags(), Ty, Alignment,
|
2021-06-22 07:34:02 +08:00
|
|
|
MMO->getAAInfo(), nullptr, MMO->getSyncScopeID(),
|
|
|
|
MMO->getSuccessOrdering(), MMO->getFailureOrdering());
|
2009-09-26 04:36:54 +08:00
|
|
|
}
|
|
|
|
|
2017-08-01 11:32:15 +08:00
|
|
|
MachineMemOperand *
|
|
|
|
MachineFunction::getMachineMemOperand(const MachineMemOperand *MMO,
|
|
|
|
const AAMDNodes &AAInfo) {
|
|
|
|
MachinePointerInfo MPI = MMO->getValue() ?
|
|
|
|
MachinePointerInfo(MMO->getValue(), MMO->getOffset()) :
|
|
|
|
MachinePointerInfo(MMO->getPseudoValue(), MMO->getOffset());
|
|
|
|
|
[Alignment][NFC] MachineMemOperand::getAlign/getBaseAlign
Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790
Reviewers: courbet
Subscribers: arsenm, dschuff, sdardis, nemanjai, jvesely, nhaehnle, sbc100, jgravelle-google, hiraditya, aheejin, kbarton, jrtc27, atanasyan, jfb, kerbowa, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D76925
2020-03-27 21:51:59 +08:00
|
|
|
return new (Allocator) MachineMemOperand(
|
2020-03-30 17:38:44 +08:00
|
|
|
MPI, MMO->getFlags(), MMO->getSize(), MMO->getBaseAlign(), AAInfo,
|
2021-06-22 07:34:02 +08:00
|
|
|
MMO->getRanges(), MMO->getSyncScopeID(), MMO->getSuccessOrdering(),
|
[Alignment][NFC] MachineMemOperand::getAlign/getBaseAlign
Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790
Reviewers: courbet
Subscribers: arsenm, dschuff, sdardis, nemanjai, jvesely, nhaehnle, sbc100, jgravelle-google, hiraditya, aheejin, kbarton, jrtc27, atanasyan, jfb, kerbowa, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D76925
2020-03-27 21:51:59 +08:00
|
|
|
MMO->getFailureOrdering());
|
2017-08-01 11:32:15 +08:00
|
|
|
}
|
|
|
|
|
2019-06-13 20:58:55 +08:00
|
|
|
MachineMemOperand *
|
|
|
|
MachineFunction::getMachineMemOperand(const MachineMemOperand *MMO,
|
|
|
|
MachineMemOperand::Flags Flags) {
|
|
|
|
return new (Allocator) MachineMemOperand(
|
2020-03-30 17:38:44 +08:00
|
|
|
MMO->getPointerInfo(), Flags, MMO->getSize(), MMO->getBaseAlign(),
|
2019-06-13 20:58:55 +08:00
|
|
|
MMO->getAAInfo(), MMO->getRanges(), MMO->getSyncScopeID(),
|
2021-06-22 07:34:02 +08:00
|
|
|
MMO->getSuccessOrdering(), MMO->getFailureOrdering());
|
2019-06-13 20:58:55 +08:00
|
|
|
}
|
|
|
|
|
2019-10-29 05:53:32 +08:00
|
|
|
MachineInstr::ExtraInfo *MachineFunction::createMIExtraInfo(
|
|
|
|
ArrayRef<MachineMemOperand *> MMOs, MCSymbol *PreInstrSymbol,
|
|
|
|
MCSymbol *PostInstrSymbol, MDNode *HeapAllocMarker) {
|
2018-08-17 05:30:05 +08:00
|
|
|
return MachineInstr::ExtraInfo::create(Allocator, MMOs, PreInstrSymbol,
|
2019-10-29 05:53:32 +08:00
|
|
|
PostInstrSymbol, HeapAllocMarker);
|
2009-10-10 02:10:05 +08:00
|
|
|
}
|
|
|
|
|
2015-07-22 00:59:53 +08:00
|
|
|
const char *MachineFunction::createExternalSymbolName(StringRef Name) {
|
|
|
|
char *Dest = Allocator.Allocate<char>(Name.size() + 1);
|
2018-11-17 09:44:25 +08:00
|
|
|
llvm::copy(Name, Dest);
|
2015-07-22 00:59:53 +08:00
|
|
|
Dest[Name.size()] = 0;
|
|
|
|
return Dest;
|
|
|
|
}
|
|
|
|
|
2018-07-26 08:27:47 +08:00
|
|
|
uint32_t *MachineFunction::allocateRegMask() {
|
|
|
|
unsigned NumRegs = getSubtarget().getRegisterInfo()->getNumRegs();
|
|
|
|
unsigned Size = MachineOperand::getRegMaskSize(NumRegs);
|
|
|
|
uint32_t *Mask = Allocator.Allocate<uint32_t>(Size);
|
|
|
|
memset(Mask, 0, Size * sizeof(Mask[0]));
|
|
|
|
return Mask;
|
|
|
|
}
|
|
|
|
|
2020-01-14 07:32:45 +08:00
|
|
|
ArrayRef<int> MachineFunction::allocateShuffleMask(ArrayRef<int> Mask) {
|
|
|
|
int* AllocMask = Allocator.Allocate<int>(Mask.size());
|
|
|
|
copy(Mask, AllocMask);
|
|
|
|
return {AllocMask, Mask.size()};
|
|
|
|
}
|
|
|
|
|
2017-10-15 22:32:27 +08:00
|
|
|
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
|
2016-01-30 04:50:44 +08:00
|
|
|
LLVM_DUMP_METHOD void MachineFunction::dump() const {
|
2010-01-05 07:39:17 +08:00
|
|
|
print(dbgs());
|
2008-07-08 07:14:23 +08:00
|
|
|
}
|
2012-09-07 03:06:06 +08:00
|
|
|
#endif
|
2002-10-30 08:48:05 +08:00
|
|
|
|
2012-08-22 14:07:19 +08:00
|
|
|
StringRef MachineFunction::getName() const {
|
2017-12-16 06:22:58 +08:00
|
|
|
return getFunction().getName();
|
2012-08-22 14:07:19 +08:00
|
|
|
}
|
|
|
|
|
2016-05-06 02:14:43 +08:00
|
|
|
void MachineFunction::print(raw_ostream &OS, const SlotIndexes *Indexes) const {
|
2012-08-23 01:18:53 +08:00
|
|
|
OS << "# Machine code for function " << getName() << ": ";
|
2016-03-30 04:28:20 +08:00
|
|
|
getProperties().print(OS);
|
2016-09-29 09:47:42 +08:00
|
|
|
OS << '\n';
|
2002-12-29 04:37:16 +08:00
|
|
|
|
|
|
|
// Print Frame Information
|
2008-07-08 07:14:23 +08:00
|
|
|
FrameInfo->print(*this, OS);
|
2012-06-20 07:37:57 +08:00
|
|
|
|
2006-04-23 02:53:45 +08:00
|
|
|
// Print JumpTable Information
|
2010-01-26 07:26:13 +08:00
|
|
|
if (JumpTableInfo)
|
|
|
|
JumpTableInfo->print(OS);
|
2003-01-13 08:23:03 +08:00
|
|
|
|
|
|
|
// Print Constant Pool
|
2009-08-23 09:12:47 +08:00
|
|
|
ConstantPool->print(OS);
|
2012-06-20 07:37:57 +08:00
|
|
|
|
2014-08-05 10:39:49 +08:00
|
|
|
const TargetRegisterInfo *TRI = getSubtarget().getRegisterInfo();
|
2012-06-20 07:37:57 +08:00
|
|
|
|
2008-10-13 20:37:16 +08:00
|
|
|
if (RegInfo && !RegInfo->livein_empty()) {
|
2009-11-01 04:19:03 +08:00
|
|
|
OS << "Function Live Ins: ";
|
2007-12-31 12:13:23 +08:00
|
|
|
for (MachineRegisterInfo::livein_iterator
|
|
|
|
I = RegInfo->livein_begin(), E = RegInfo->livein_end(); I != E; ++I) {
|
2017-11-28 20:42:37 +08:00
|
|
|
OS << printReg(I->first, TRI);
|
2006-05-16 13:55:30 +08:00
|
|
|
if (I->second)
|
2017-11-28 20:42:37 +08:00
|
|
|
OS << " in " << printReg(I->second, TRI);
|
2014-03-02 20:27:27 +08:00
|
|
|
if (std::next(I) != E)
|
2009-11-01 04:19:03 +08:00
|
|
|
OS << ", ";
|
2005-09-01 06:34:59 +08:00
|
|
|
}
|
2009-08-23 09:12:47 +08:00
|
|
|
OS << '\n';
|
2005-09-01 06:34:59 +08:00
|
|
|
}
|
2012-06-20 07:37:57 +08:00
|
|
|
|
2017-12-16 06:22:58 +08:00
|
|
|
ModuleSlotTracker MST(getFunction().getParent());
|
|
|
|
MST.incorporateFunction(getFunction());
|
2014-05-01 02:29:51 +08:00
|
|
|
for (const auto &BB : *this) {
|
2009-11-01 04:19:03 +08:00
|
|
|
OS << '\n';
|
2018-02-26 23:23:42 +08:00
|
|
|
// If we print the whole function, print it at its most verbose level.
|
|
|
|
BB.print(OS, MST, Indexes, /*IsStandalone=*/true);
|
2009-11-01 04:19:03 +08:00
|
|
|
}
|
2004-03-30 05:58:31 +08:00
|
|
|
|
2012-08-23 01:18:53 +08:00
|
|
|
OS << "\n# End machine code for function " << getName() << ".\n\n";
|
2002-10-30 08:48:05 +08:00
|
|
|
}
|
|
|
|
|
2019-10-31 16:55:57 +08:00
|
|
|
/// True if this function needs frame moves for debug or exceptions.
|
|
|
|
bool MachineFunction::needsFrameMoves() const {
|
|
|
|
return getMMI().hasDebugInfo() ||
|
|
|
|
getTarget().Options.ForceDwarfFrameSection ||
|
|
|
|
F.needsUnwindTableEntry();
|
|
|
|
}
|
|
|
|
|
2004-07-08 08:47:58 +08:00
|
|
|
namespace llvm {
|
2017-10-11 06:33:29 +08:00
|
|
|
|
2004-09-06 02:41:35 +08:00
|
|
|
template<>
|
|
|
|
struct DOTGraphTraits<const MachineFunction*> : public DefaultDOTGraphTraits {
|
2017-10-11 06:33:29 +08:00
|
|
|
DOTGraphTraits(bool isSimple = false) : DefaultDOTGraphTraits(isSimple) {}
|
2009-11-30 20:38:13 +08:00
|
|
|
|
2004-09-06 02:41:35 +08:00
|
|
|
static std::string getGraphName(const MachineFunction *F) {
|
2015-03-28 01:51:30 +08:00
|
|
|
return ("CFG for '" + F->getName() + "' function").str();
|
2004-09-06 02:41:35 +08:00
|
|
|
}
|
2004-07-08 08:47:58 +08:00
|
|
|
|
2009-11-30 20:38:47 +08:00
|
|
|
std::string getNodeLabel(const MachineBasicBlock *Node,
|
|
|
|
const MachineFunction *Graph) {
|
2009-08-23 11:13:20 +08:00
|
|
|
std::string OutStr;
|
|
|
|
{
|
|
|
|
raw_string_ostream OSS(OutStr);
|
2010-10-30 09:26:19 +08:00
|
|
|
|
|
|
|
if (isSimple()) {
|
2017-12-05 01:18:51 +08:00
|
|
|
OSS << printMBBReference(*Node);
|
2010-10-30 09:26:19 +08:00
|
|
|
if (const BasicBlock *BB = Node->getBasicBlock())
|
|
|
|
OSS << ": " << BB->getName();
|
|
|
|
} else
|
2009-08-23 11:13:20 +08:00
|
|
|
Node->print(OSS);
|
2004-09-06 02:41:35 +08:00
|
|
|
}
|
2004-07-08 08:47:58 +08:00
|
|
|
|
2004-09-06 02:41:35 +08:00
|
|
|
if (OutStr[0] == '\n') OutStr.erase(OutStr.begin());
|
2004-07-08 08:47:58 +08:00
|
|
|
|
2004-09-06 02:41:35 +08:00
|
|
|
// Process string output to make it nicer...
|
|
|
|
for (unsigned i = 0; i != OutStr.length(); ++i)
|
|
|
|
if (OutStr[i] == '\n') { // Left justify
|
|
|
|
OutStr[i] = '\\';
|
|
|
|
OutStr.insert(OutStr.begin()+i+1, 'l');
|
|
|
|
}
|
|
|
|
return OutStr;
|
|
|
|
}
|
|
|
|
};
|
2017-10-11 06:33:29 +08:00
|
|
|
|
|
|
|
} // end namespace llvm
|
2004-07-08 08:47:58 +08:00
|
|
|
|
|
|
|
void MachineFunction::viewCFG() const
|
|
|
|
{
|
2005-10-12 20:09:05 +08:00
|
|
|
#ifndef NDEBUG
|
2012-08-23 01:18:53 +08:00
|
|
|
ViewGraph(this, "mf" + getName());
|
2006-06-28 00:49:46 +08:00
|
|
|
#else
|
2010-07-08 01:28:45 +08:00
|
|
|
errs() << "MachineFunction::viewCFG is only available in debug builds on "
|
2009-08-23 16:50:52 +08:00
|
|
|
<< "systems with Graphviz or gv!\n";
|
2006-06-28 00:49:46 +08:00
|
|
|
#endif // NDEBUG
|
2004-07-08 08:47:58 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void MachineFunction::viewCFGOnly() const
|
|
|
|
{
|
2009-06-25 01:37:09 +08:00
|
|
|
#ifndef NDEBUG
|
2012-08-23 01:18:53 +08:00
|
|
|
ViewGraph(this, "mf" + getName(), true);
|
2009-06-25 01:37:09 +08:00
|
|
|
#else
|
2010-07-08 01:28:45 +08:00
|
|
|
errs() << "MachineFunction::viewCFGOnly is only available in debug builds on "
|
2009-08-23 16:50:52 +08:00
|
|
|
<< "systems with Graphviz or gv!\n";
|
2009-06-25 01:37:09 +08:00
|
|
|
#endif // NDEBUG
|
2004-07-08 08:47:58 +08:00
|
|
|
}
|
|
|
|
|
2015-06-13 23:32:45 +08:00
|
|
|
/// Add the specified physical register as a live-in value and
|
2009-04-21 02:36:57 +08:00
|
|
|
/// create a corresponding virtual register for it.
|
2020-05-20 01:01:19 +08:00
|
|
|
Register MachineFunction::addLiveIn(MCRegister PReg,
|
2011-02-22 07:21:26 +08:00
|
|
|
const TargetRegisterClass *RC) {
|
2010-05-25 05:33:37 +08:00
|
|
|
MachineRegisterInfo &MRI = getRegInfo();
|
2020-05-20 01:01:19 +08:00
|
|
|
Register VReg = MRI.getLiveInVirtReg(PReg);
|
2010-05-25 05:33:37 +08:00
|
|
|
if (VReg) {
|
2013-12-12 08:15:47 +08:00
|
|
|
const TargetRegisterClass *VRegRC = MRI.getRegClass(VReg);
|
|
|
|
(void)VRegRC;
|
|
|
|
// A physical register can be added several times.
|
|
|
|
// Between two calls, the register class of the related virtual register
|
|
|
|
// may have been constrained to match some operation constraints.
|
|
|
|
// In that case, check that the current register class includes the
|
|
|
|
// physical register and is a sub class of the specified RC.
|
|
|
|
assert((VRegRC == RC || (VRegRC->contains(PReg) &&
|
|
|
|
RC->hasSubClassEq(VRegRC))) &&
|
|
|
|
"Register class mismatch!");
|
2010-05-25 05:33:37 +08:00
|
|
|
return VReg;
|
|
|
|
}
|
|
|
|
VReg = MRI.createVirtualRegister(RC);
|
|
|
|
MRI.addLiveIn(PReg, VReg);
|
2009-04-21 02:36:57 +08:00
|
|
|
return VReg;
|
|
|
|
}
|
|
|
|
|
2015-06-13 23:32:45 +08:00
|
|
|
/// Return the MCSymbol for the specified non-empty jump table.
|
2010-06-30 06:34:52 +08:00
|
|
|
/// If isLinkerPrivate is specified, an 'l' label is returned, otherwise a
|
|
|
|
/// normal 'L' label is returned.
|
2014-06-25 20:40:56 +08:00
|
|
|
MCSymbol *MachineFunction::getJTISymbol(unsigned JTI, MCContext &Ctx,
|
2010-06-30 06:34:52 +08:00
|
|
|
bool isLinkerPrivate) const {
|
2015-07-08 02:20:57 +08:00
|
|
|
const DataLayout &DL = getDataLayout();
|
2010-01-26 14:28:43 +08:00
|
|
|
assert(JumpTableInfo && "No jump tables");
|
2010-01-27 18:27:10 +08:00
|
|
|
assert(JTI < JumpTableInfo->getJumpTables().size() && "Invalid JTI!");
|
2012-06-20 07:37:57 +08:00
|
|
|
|
2016-10-01 13:57:55 +08:00
|
|
|
StringRef Prefix = isLinkerPrivate ? DL.getLinkerPrivateGlobalPrefix()
|
|
|
|
: DL.getPrivateGlobalPrefix();
|
2014-06-27 06:52:05 +08:00
|
|
|
SmallString<60> Name;
|
|
|
|
raw_svector_ostream(Name)
|
|
|
|
<< Prefix << "JTI" << getFunctionNumber() << '_' << JTI;
|
2015-05-19 02:43:14 +08:00
|
|
|
return Ctx.getOrCreateSymbol(Name);
|
2010-01-26 14:28:43 +08:00
|
|
|
}
|
|
|
|
|
2015-06-13 23:32:45 +08:00
|
|
|
/// Return a function-local symbol to represent the PIC base.
|
2010-11-15 06:48:15 +08:00
|
|
|
MCSymbol *MachineFunction::getPICBaseSymbol() const {
|
2015-07-08 02:20:57 +08:00
|
|
|
const DataLayout &DL = getDataLayout();
|
|
|
|
return Ctx.getOrCreateSymbol(Twine(DL.getPrivateGlobalPrefix()) +
|
|
|
|
Twine(getFunctionNumber()) + "$pb");
|
2010-11-15 06:48:15 +08:00
|
|
|
}
|
2010-01-26 14:28:43 +08:00
|
|
|
|
2016-12-02 03:32:15 +08:00
|
|
|
/// \name Exception Handling
|
|
|
|
/// \{
|
|
|
|
|
|
|
|
LandingPadInfo &
|
|
|
|
MachineFunction::getOrCreateLandingPadInfo(MachineBasicBlock *LandingPad) {
|
|
|
|
unsigned N = LandingPads.size();
|
|
|
|
for (unsigned i = 0; i < N; ++i) {
|
|
|
|
LandingPadInfo &LP = LandingPads[i];
|
|
|
|
if (LP.LandingPadBlock == LandingPad)
|
|
|
|
return LP;
|
|
|
|
}
|
|
|
|
|
|
|
|
LandingPads.push_back(LandingPadInfo(LandingPad));
|
|
|
|
return LandingPads[N];
|
|
|
|
}
|
|
|
|
|
|
|
|
void MachineFunction::addInvoke(MachineBasicBlock *LandingPad,
|
|
|
|
MCSymbol *BeginLabel, MCSymbol *EndLabel) {
|
|
|
|
LandingPadInfo &LP = getOrCreateLandingPadInfo(LandingPad);
|
|
|
|
LP.BeginLabels.push_back(BeginLabel);
|
|
|
|
LP.EndLabels.push_back(EndLabel);
|
|
|
|
}
|
|
|
|
|
|
|
|
MCSymbol *MachineFunction::addLandingPad(MachineBasicBlock *LandingPad) {
|
|
|
|
MCSymbol *LandingPadLabel = Ctx.createTempSymbol();
|
|
|
|
LandingPadInfo &LP = getOrCreateLandingPadInfo(LandingPad);
|
|
|
|
LP.LandingPadLabel = LandingPadLabel;
|
2018-09-26 03:56:44 +08:00
|
|
|
|
|
|
|
const Instruction *FirstI = LandingPad->getBasicBlock()->getFirstNonPHI();
|
|
|
|
if (const auto *LPI = dyn_cast<LandingPadInst>(FirstI)) {
|
|
|
|
if (const auto *PF =
|
|
|
|
dyn_cast<Function>(F.getPersonalityFn()->stripPointerCasts()))
|
|
|
|
getMMI().addPersonality(PF);
|
|
|
|
|
|
|
|
if (LPI->isCleanup())
|
|
|
|
addCleanup(LandingPad);
|
|
|
|
|
|
|
|
// FIXME: New EH - Add the clauses in reverse order. This isn't 100%
|
2018-09-29 17:22:25 +08:00
|
|
|
// correct, but we need to do it this way because of how the DWARF EH
|
|
|
|
// emitter processes the clauses.
|
2018-09-26 03:56:44 +08:00
|
|
|
for (unsigned I = LPI->getNumClauses(); I != 0; --I) {
|
|
|
|
Value *Val = LPI->getClause(I - 1);
|
|
|
|
if (LPI->isCatch(I - 1)) {
|
|
|
|
addCatchTypeInfo(LandingPad,
|
|
|
|
dyn_cast<GlobalValue>(Val->stripPointerCasts()));
|
|
|
|
} else {
|
|
|
|
// Add filters in a list.
|
|
|
|
auto *CVal = cast<Constant>(Val);
|
|
|
|
SmallVector<const GlobalValue *, 4> FilterList;
|
2021-11-15 01:32:38 +08:00
|
|
|
for (const Use &U : CVal->operands())
|
|
|
|
FilterList.push_back(cast<GlobalValue>(U->stripPointerCasts()));
|
2018-09-26 03:56:44 +08:00
|
|
|
|
|
|
|
addFilterTypeInfo(LandingPad, FilterList);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
Reland "[WebAssembly] LSDA info generation"
Summary:
This adds support for LSDA (exception table) generation for wasm EH.
Wasm EH mostly follows the structure of Itanium-style exception tables,
with one exception: a call site table entry in wasm EH corresponds to
not a call site but a landing pad.
In wasm EH, the VM is responsible for stack unwinding. After an
exception occurs and the stack is unwound, the control flow is
transferred to wasm 'catch' instruction by the VM, after which the
personality function is called from the compiler-generated code. (Refer
to WasmEHPrepare pass for more information on this part.)
This patch:
- Changes wasm.landingpad.index intrinsic to take a token argument, to
make this 1:1 match with a catchpad instruction
- Stores landingpad index info and catch type info MachineFunction in
before instruction selection
- Lowers wasm.lsda intrinsic to an MCSymbol pointing to the start of an
exception table
- Adds WasmException class with overridden methods for table generation
- Adds support for LSDA section in Wasm object writer
Reviewers: dschuff, sbc100, rnk
Subscribers: mgorny, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D52748
llvm-svn: 345345
2018-10-26 07:55:10 +08:00
|
|
|
} else if (const auto *CPI = dyn_cast<CatchPadInst>(FirstI)) {
|
|
|
|
for (unsigned I = CPI->getNumArgOperands(); I != 0; --I) {
|
|
|
|
Value *TypeInfo = CPI->getArgOperand(I - 1)->stripPointerCasts();
|
|
|
|
addCatchTypeInfo(LandingPad, dyn_cast<GlobalValue>(TypeInfo));
|
|
|
|
}
|
2018-09-26 03:56:44 +08:00
|
|
|
|
|
|
|
} else {
|
|
|
|
assert(isa<CleanupPadInst>(FirstI) && "Invalid landingpad!");
|
|
|
|
}
|
|
|
|
|
2016-12-02 03:32:15 +08:00
|
|
|
return LandingPadLabel;
|
|
|
|
}
|
|
|
|
|
|
|
|
void MachineFunction::addCatchTypeInfo(MachineBasicBlock *LandingPad,
|
|
|
|
ArrayRef<const GlobalValue *> TyInfo) {
|
|
|
|
LandingPadInfo &LP = getOrCreateLandingPadInfo(LandingPad);
|
2021-12-13 08:13:49 +08:00
|
|
|
for (const GlobalValue *GV : llvm::reverse(TyInfo))
|
|
|
|
LP.TypeIds.push_back(getTypeIDFor(GV));
|
2016-12-02 03:32:15 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void MachineFunction::addFilterTypeInfo(MachineBasicBlock *LandingPad,
|
|
|
|
ArrayRef<const GlobalValue *> TyInfo) {
|
|
|
|
LandingPadInfo &LP = getOrCreateLandingPadInfo(LandingPad);
|
|
|
|
std::vector<unsigned> IdsInFilter(TyInfo.size());
|
|
|
|
for (unsigned I = 0, E = TyInfo.size(); I != E; ++I)
|
|
|
|
IdsInFilter[I] = getTypeIDFor(TyInfo[I]);
|
|
|
|
LP.TypeIds.push_back(getFilterIDFor(IdsInFilter));
|
|
|
|
}
|
|
|
|
|
Reland "[WebAssembly] LSDA info generation"
Summary:
This adds support for LSDA (exception table) generation for wasm EH.
Wasm EH mostly follows the structure of Itanium-style exception tables,
with one exception: a call site table entry in wasm EH corresponds to
not a call site but a landing pad.
In wasm EH, the VM is responsible for stack unwinding. After an
exception occurs and the stack is unwound, the control flow is
transferred to wasm 'catch' instruction by the VM, after which the
personality function is called from the compiler-generated code. (Refer
to WasmEHPrepare pass for more information on this part.)
This patch:
- Changes wasm.landingpad.index intrinsic to take a token argument, to
make this 1:1 match with a catchpad instruction
- Stores landingpad index info and catch type info MachineFunction in
before instruction selection
- Lowers wasm.lsda intrinsic to an MCSymbol pointing to the start of an
exception table
- Adds WasmException class with overridden methods for table generation
- Adds support for LSDA section in Wasm object writer
Reviewers: dschuff, sbc100, rnk
Subscribers: mgorny, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D52748
llvm-svn: 345345
2018-10-26 07:55:10 +08:00
|
|
|
void MachineFunction::tidyLandingPads(DenseMap<MCSymbol *, uintptr_t> *LPMap,
|
|
|
|
bool TidyIfNoBeginLabels) {
|
2016-12-02 03:32:15 +08:00
|
|
|
for (unsigned i = 0; i != LandingPads.size(); ) {
|
|
|
|
LandingPadInfo &LandingPad = LandingPads[i];
|
|
|
|
if (LandingPad.LandingPadLabel &&
|
|
|
|
!LandingPad.LandingPadLabel->isDefined() &&
|
|
|
|
(!LPMap || (*LPMap)[LandingPad.LandingPadLabel] == 0))
|
|
|
|
LandingPad.LandingPadLabel = nullptr;
|
|
|
|
|
|
|
|
// Special case: we *should* emit LPs with null LP MBB. This indicates
|
|
|
|
// "nounwind" case.
|
|
|
|
if (!LandingPad.LandingPadLabel && LandingPad.LandingPadBlock) {
|
|
|
|
LandingPads.erase(LandingPads.begin() + i);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
Reland "[WebAssembly] LSDA info generation"
Summary:
This adds support for LSDA (exception table) generation for wasm EH.
Wasm EH mostly follows the structure of Itanium-style exception tables,
with one exception: a call site table entry in wasm EH corresponds to
not a call site but a landing pad.
In wasm EH, the VM is responsible for stack unwinding. After an
exception occurs and the stack is unwound, the control flow is
transferred to wasm 'catch' instruction by the VM, after which the
personality function is called from the compiler-generated code. (Refer
to WasmEHPrepare pass for more information on this part.)
This patch:
- Changes wasm.landingpad.index intrinsic to take a token argument, to
make this 1:1 match with a catchpad instruction
- Stores landingpad index info and catch type info MachineFunction in
before instruction selection
- Lowers wasm.lsda intrinsic to an MCSymbol pointing to the start of an
exception table
- Adds WasmException class with overridden methods for table generation
- Adds support for LSDA section in Wasm object writer
Reviewers: dschuff, sbc100, rnk
Subscribers: mgorny, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D52748
llvm-svn: 345345
2018-10-26 07:55:10 +08:00
|
|
|
if (TidyIfNoBeginLabels) {
|
|
|
|
for (unsigned j = 0, e = LandingPads[i].BeginLabels.size(); j != e; ++j) {
|
|
|
|
MCSymbol *BeginLabel = LandingPad.BeginLabels[j];
|
|
|
|
MCSymbol *EndLabel = LandingPad.EndLabels[j];
|
|
|
|
if ((BeginLabel->isDefined() || (LPMap && (*LPMap)[BeginLabel] != 0)) &&
|
|
|
|
(EndLabel->isDefined() || (LPMap && (*LPMap)[EndLabel] != 0)))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
LandingPad.BeginLabels.erase(LandingPad.BeginLabels.begin() + j);
|
|
|
|
LandingPad.EndLabels.erase(LandingPad.EndLabels.begin() + j);
|
|
|
|
--j;
|
|
|
|
--e;
|
|
|
|
}
|
2016-12-02 03:32:15 +08:00
|
|
|
|
Reland "[WebAssembly] LSDA info generation"
Summary:
This adds support for LSDA (exception table) generation for wasm EH.
Wasm EH mostly follows the structure of Itanium-style exception tables,
with one exception: a call site table entry in wasm EH corresponds to
not a call site but a landing pad.
In wasm EH, the VM is responsible for stack unwinding. After an
exception occurs and the stack is unwound, the control flow is
transferred to wasm 'catch' instruction by the VM, after which the
personality function is called from the compiler-generated code. (Refer
to WasmEHPrepare pass for more information on this part.)
This patch:
- Changes wasm.landingpad.index intrinsic to take a token argument, to
make this 1:1 match with a catchpad instruction
- Stores landingpad index info and catch type info MachineFunction in
before instruction selection
- Lowers wasm.lsda intrinsic to an MCSymbol pointing to the start of an
exception table
- Adds WasmException class with overridden methods for table generation
- Adds support for LSDA section in Wasm object writer
Reviewers: dschuff, sbc100, rnk
Subscribers: mgorny, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D52748
llvm-svn: 345345
2018-10-26 07:55:10 +08:00
|
|
|
// Remove landing pads with no try-ranges.
|
|
|
|
if (LandingPads[i].BeginLabels.empty()) {
|
|
|
|
LandingPads.erase(LandingPads.begin() + i);
|
|
|
|
continue;
|
|
|
|
}
|
2016-12-02 03:32:15 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// If there is no landing pad, ensure that the list of typeids is empty.
|
|
|
|
// If the only typeid is a cleanup, this is the same as having no typeids.
|
|
|
|
if (!LandingPad.LandingPadBlock ||
|
|
|
|
(LandingPad.TypeIds.size() == 1 && !LandingPad.TypeIds[0]))
|
|
|
|
LandingPad.TypeIds.clear();
|
|
|
|
++i;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void MachineFunction::addCleanup(MachineBasicBlock *LandingPad) {
|
|
|
|
LandingPadInfo &LP = getOrCreateLandingPadInfo(LandingPad);
|
|
|
|
LP.TypeIds.push_back(0);
|
|
|
|
}
|
|
|
|
|
|
|
|
void MachineFunction::addSEHCatchHandler(MachineBasicBlock *LandingPad,
|
|
|
|
const Function *Filter,
|
|
|
|
const BlockAddress *RecoverBA) {
|
|
|
|
LandingPadInfo &LP = getOrCreateLandingPadInfo(LandingPad);
|
|
|
|
SEHHandler Handler;
|
|
|
|
Handler.FilterOrFinally = Filter;
|
|
|
|
Handler.RecoverBA = RecoverBA;
|
|
|
|
LP.SEHHandlers.push_back(Handler);
|
|
|
|
}
|
|
|
|
|
|
|
|
void MachineFunction::addSEHCleanupHandler(MachineBasicBlock *LandingPad,
|
|
|
|
const Function *Cleanup) {
|
|
|
|
LandingPadInfo &LP = getOrCreateLandingPadInfo(LandingPad);
|
|
|
|
SEHHandler Handler;
|
|
|
|
Handler.FilterOrFinally = Cleanup;
|
|
|
|
Handler.RecoverBA = nullptr;
|
|
|
|
LP.SEHHandlers.push_back(Handler);
|
|
|
|
}
|
|
|
|
|
|
|
|
void MachineFunction::setCallSiteLandingPad(MCSymbol *Sym,
|
|
|
|
ArrayRef<unsigned> Sites) {
|
|
|
|
LPadToCallSiteMap[Sym].append(Sites.begin(), Sites.end());
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned MachineFunction::getTypeIDFor(const GlobalValue *TI) {
|
|
|
|
for (unsigned i = 0, N = TypeInfos.size(); i != N; ++i)
|
|
|
|
if (TypeInfos[i] == TI) return i + 1;
|
|
|
|
|
|
|
|
TypeInfos.push_back(TI);
|
|
|
|
return TypeInfos.size();
|
|
|
|
}
|
|
|
|
|
|
|
|
int MachineFunction::getFilterIDFor(std::vector<unsigned> &TyIds) {
|
|
|
|
// If the new filter coincides with the tail of an existing filter, then
|
|
|
|
// re-use the existing filter. Folding filters more than this requires
|
|
|
|
// re-ordering filters and/or their elements - probably not worth it.
|
2021-02-16 06:46:10 +08:00
|
|
|
for (unsigned i : FilterEnds) {
|
|
|
|
unsigned j = TyIds.size();
|
2016-12-02 03:32:15 +08:00
|
|
|
|
|
|
|
while (i && j)
|
|
|
|
if (FilterIds[--i] != TyIds[--j])
|
|
|
|
goto try_next;
|
|
|
|
|
|
|
|
if (!j)
|
|
|
|
// The new filter coincides with range [i, end) of the existing filter.
|
|
|
|
return -(1 + i);
|
|
|
|
|
|
|
|
try_next:;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Add the new filter.
|
|
|
|
int FilterID = -(1 + FilterIds.size());
|
|
|
|
FilterIds.reserve(FilterIds.size() + TyIds.size() + 1);
|
2020-12-29 11:55:16 +08:00
|
|
|
llvm::append_range(FilterIds, TyIds);
|
2016-12-02 03:32:15 +08:00
|
|
|
FilterEnds.push_back(FilterIds.size());
|
|
|
|
FilterIds.push_back(0); // terminator
|
|
|
|
return FilterID;
|
|
|
|
}
|
|
|
|
|
2019-11-14 07:33:12 +08:00
|
|
|
MachineFunction::CallSiteInfoMap::iterator
|
|
|
|
MachineFunction::getCallSiteInfo(const MachineInstr *MI) {
|
2020-02-10 16:49:14 +08:00
|
|
|
assert(MI->isCandidateForCallSiteEntry() &&
|
|
|
|
"Call site info refers only to call (MI) candidates");
|
2020-02-20 20:43:01 +08:00
|
|
|
|
2020-03-09 18:02:35 +08:00
|
|
|
if (!Target.Options.EmitCallSiteInfo)
|
2019-11-14 07:33:12 +08:00
|
|
|
return CallSitesInfo.end();
|
|
|
|
return CallSitesInfo.find(MI);
|
|
|
|
}
|
|
|
|
|
2020-02-27 18:44:53 +08:00
|
|
|
/// Return the call machine instruction or find a call within bundle.
|
|
|
|
static const MachineInstr *getCallInstr(const MachineInstr *MI) {
|
|
|
|
if (!MI->isBundle())
|
|
|
|
return MI;
|
2019-06-27 21:10:29 +08:00
|
|
|
|
2020-02-27 18:44:53 +08:00
|
|
|
for (auto &BMI : make_range(getBundleStart(MI->getIterator()),
|
|
|
|
getBundleEnd(MI->getIterator())))
|
|
|
|
if (BMI.isCandidateForCallSiteEntry())
|
|
|
|
return &BMI;
|
2019-10-08 23:43:12 +08:00
|
|
|
|
2020-02-27 18:44:53 +08:00
|
|
|
llvm_unreachable("Unexpected bundle without a call site candidate");
|
2019-10-08 23:43:12 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void MachineFunction::eraseCallSiteInfo(const MachineInstr *MI) {
|
2020-02-27 18:44:53 +08:00
|
|
|
assert(MI->shouldUpdateCallSiteInfo() &&
|
|
|
|
"Call site info refers only to call (MI) candidates or "
|
|
|
|
"candidates inside bundles");
|
|
|
|
|
|
|
|
const MachineInstr *CallMI = getCallInstr(MI);
|
|
|
|
CallSiteInfoMap::iterator CSIt = getCallSiteInfo(CallMI);
|
2019-10-08 23:43:12 +08:00
|
|
|
if (CSIt == CallSitesInfo.end())
|
|
|
|
return;
|
|
|
|
CallSitesInfo.erase(CSIt);
|
|
|
|
}
|
|
|
|
|
|
|
|
void MachineFunction::copyCallSiteInfo(const MachineInstr *Old,
|
|
|
|
const MachineInstr *New) {
|
2020-02-27 18:44:53 +08:00
|
|
|
assert(Old->shouldUpdateCallSiteInfo() &&
|
|
|
|
"Call site info refers only to call (MI) candidates or "
|
|
|
|
"candidates inside bundles");
|
2020-02-10 16:49:14 +08:00
|
|
|
|
|
|
|
if (!New->isCandidateForCallSiteEntry())
|
|
|
|
return eraseCallSiteInfo(Old);
|
2019-10-08 23:43:12 +08:00
|
|
|
|
2020-02-27 18:44:53 +08:00
|
|
|
const MachineInstr *OldCallMI = getCallInstr(Old);
|
|
|
|
CallSiteInfoMap::iterator CSIt = getCallSiteInfo(OldCallMI);
|
2019-10-08 23:43:12 +08:00
|
|
|
if (CSIt == CallSitesInfo.end())
|
|
|
|
return;
|
|
|
|
|
|
|
|
CallSiteInfo CSInfo = CSIt->second;
|
|
|
|
CallSitesInfo[New] = CSInfo;
|
2019-06-27 21:10:29 +08:00
|
|
|
}
|
|
|
|
|
2020-02-27 18:44:53 +08:00
|
|
|
void MachineFunction::moveCallSiteInfo(const MachineInstr *Old,
|
|
|
|
const MachineInstr *New) {
|
|
|
|
assert(Old->shouldUpdateCallSiteInfo() &&
|
|
|
|
"Call site info refers only to call (MI) candidates or "
|
|
|
|
"candidates inside bundles");
|
|
|
|
|
|
|
|
if (!New->isCandidateForCallSiteEntry())
|
|
|
|
return eraseCallSiteInfo(Old);
|
|
|
|
|
|
|
|
const MachineInstr *OldCallMI = getCallInstr(Old);
|
|
|
|
CallSiteInfoMap::iterator CSIt = getCallSiteInfo(OldCallMI);
|
|
|
|
if (CSIt == CallSitesInfo.end())
|
|
|
|
return;
|
|
|
|
|
|
|
|
CallSiteInfo CSInfo = std::move(CSIt->second);
|
|
|
|
CallSitesInfo.erase(CSIt);
|
|
|
|
CallSitesInfo[New] = CSInfo;
|
|
|
|
}
|
|
|
|
|
2020-10-14 17:47:44 +08:00
|
|
|
void MachineFunction::setDebugInstrNumberingCount(unsigned Num) {
|
|
|
|
DebugInstrNumberingCount = Num;
|
|
|
|
}
|
|
|
|
|
[DebugInstrRef] Support recording of instruction reference substitutions
Add a table recording "substitutions" between pairs of <instruction,
operand> numbers, from old pairs to new pairs. Post-isel optimizations are
able to record the outcome of an optimization in this way. For example, if
there were a divide instruction that generated the quotient and remainder,
and it were replaced by one that only generated the quotient:
$rax, $rcx = DIV-AND-REMAINDER $rdx, $rsi, debug-instr-num 1
DBG_INSTR_REF 1, 0
DBG_INSTR_REF 1, 1
Became:
$rax = DIV $rdx, $rsi, debug-instr-num 2
DBG_INSTR_REF 1, 0
DBG_INSTR_REF 1, 1
We could enter a substitution from <1, 0> to <2, 0>, and no substitution
for <1, 1> as it's no longer generated.
This approach means that if an instruction or value is deleted once we've
left SSA form, all variables that used the value implicitly become
"optimized out", something that isn't true of the current DBG_VALUE
approach.
Differential Revision: https://reviews.llvm.org/D85749
2020-10-15 18:20:29 +08:00
|
|
|
void MachineFunction::makeDebugValueSubstitution(DebugInstrOperandPair A,
|
[DebugInfo][InstrRef][1/4] Support transformations that widen values
Very late in compilation, backends like X86 will perform optimisations like
this:
$cx = MOV16rm $rax, ...
->
$rcx = MOV64rm $rax, ...
Widening the load from 16 bits to 64 bits. SEeing how the lower 16 bits
remain the same, this doesn't affect execution. However, any debug
instruction reference to the defined operand now refers to a 64 bit value,
nto a 16 bit one, which might be unexpected. Elsewhere in codegen, there's
often this pattern:
CALL64pcrel32 @foo, implicit-def $rax
%0:gr64 = COPY $rax
%1:gr32 = COPY %0.sub_32bit
Where we want to refer to the definition of $eax by the call, but don't
want to refer the copies (they don't define values in the way
LiveDebugValues sees it). To solve this, add a subregister field to the
existing "substitutions" facility, so that we can describe a field within
a larger value definition. I would imagine that this would be used most
often when a value is widened, and we need to refer to the original,
narrower definition.
Differential Revision: https://reviews.llvm.org/D88891
2021-07-01 17:59:22 +08:00
|
|
|
DebugInstrOperandPair B,
|
|
|
|
unsigned Subreg) {
|
|
|
|
// Catch any accidental self-loops.
|
|
|
|
assert(A.first != B.first);
|
2021-10-25 22:09:42 +08:00
|
|
|
// Don't allow any substitutions _from_ the memory operand number.
|
|
|
|
assert(A.second != DebugOperandMemNumber);
|
|
|
|
|
2021-07-09 22:32:30 +08:00
|
|
|
DebugValueSubstitutions.push_back({A, B, Subreg});
|
[DebugInstrRef] Support recording of instruction reference substitutions
Add a table recording "substitutions" between pairs of <instruction,
operand> numbers, from old pairs to new pairs. Post-isel optimizations are
able to record the outcome of an optimization in this way. For example, if
there were a divide instruction that generated the quotient and remainder,
and it were replaced by one that only generated the quotient:
$rax, $rcx = DIV-AND-REMAINDER $rdx, $rsi, debug-instr-num 1
DBG_INSTR_REF 1, 0
DBG_INSTR_REF 1, 1
Became:
$rax = DIV $rdx, $rsi, debug-instr-num 2
DBG_INSTR_REF 1, 0
DBG_INSTR_REF 1, 1
We could enter a substitution from <1, 0> to <2, 0>, and no substitution
for <1, 1> as it's no longer generated.
This approach means that if an instruction or value is deleted once we've
left SSA form, all variables that used the value implicitly become
"optimized out", something that isn't true of the current DBG_VALUE
approach.
Differential Revision: https://reviews.llvm.org/D85749
2020-10-15 18:20:29 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void MachineFunction::substituteDebugValuesForInst(const MachineInstr &Old,
|
2020-10-21 21:28:28 +08:00
|
|
|
MachineInstr &New,
|
|
|
|
unsigned MaxOperand) {
|
[DebugInstrRef] Support recording of instruction reference substitutions
Add a table recording "substitutions" between pairs of <instruction,
operand> numbers, from old pairs to new pairs. Post-isel optimizations are
able to record the outcome of an optimization in this way. For example, if
there were a divide instruction that generated the quotient and remainder,
and it were replaced by one that only generated the quotient:
$rax, $rcx = DIV-AND-REMAINDER $rdx, $rsi, debug-instr-num 1
DBG_INSTR_REF 1, 0
DBG_INSTR_REF 1, 1
Became:
$rax = DIV $rdx, $rsi, debug-instr-num 2
DBG_INSTR_REF 1, 0
DBG_INSTR_REF 1, 1
We could enter a substitution from <1, 0> to <2, 0>, and no substitution
for <1, 1> as it's no longer generated.
This approach means that if an instruction or value is deleted once we've
left SSA form, all variables that used the value implicitly become
"optimized out", something that isn't true of the current DBG_VALUE
approach.
Differential Revision: https://reviews.llvm.org/D85749
2020-10-15 18:20:29 +08:00
|
|
|
// If the Old instruction wasn't tracked at all, there is no work to do.
|
|
|
|
unsigned OldInstrNum = Old.peekDebugInstrNum();
|
|
|
|
if (!OldInstrNum)
|
|
|
|
return;
|
|
|
|
|
|
|
|
// Iterate over all operands looking for defs to create substitutions for.
|
|
|
|
// Avoid creating new instr numbers unless we create a new substitution.
|
|
|
|
// While this has no functional effect, it risks confusing someone reading
|
|
|
|
// MIR output.
|
2020-10-21 21:28:28 +08:00
|
|
|
// Examine all the operands, or the first N specified by the caller.
|
|
|
|
MaxOperand = std::min(MaxOperand, Old.getNumOperands());
|
2021-07-20 17:43:21 +08:00
|
|
|
for (unsigned int I = 0; I < MaxOperand; ++I) {
|
[DebugInstrRef] Support recording of instruction reference substitutions
Add a table recording "substitutions" between pairs of <instruction,
operand> numbers, from old pairs to new pairs. Post-isel optimizations are
able to record the outcome of an optimization in this way. For example, if
there were a divide instruction that generated the quotient and remainder,
and it were replaced by one that only generated the quotient:
$rax, $rcx = DIV-AND-REMAINDER $rdx, $rsi, debug-instr-num 1
DBG_INSTR_REF 1, 0
DBG_INSTR_REF 1, 1
Became:
$rax = DIV $rdx, $rsi, debug-instr-num 2
DBG_INSTR_REF 1, 0
DBG_INSTR_REF 1, 1
We could enter a substitution from <1, 0> to <2, 0>, and no substitution
for <1, 1> as it's no longer generated.
This approach means that if an instruction or value is deleted once we've
left SSA form, all variables that used the value implicitly become
"optimized out", something that isn't true of the current DBG_VALUE
approach.
Differential Revision: https://reviews.llvm.org/D85749
2020-10-15 18:20:29 +08:00
|
|
|
const auto &OldMO = Old.getOperand(I);
|
2020-10-21 21:28:28 +08:00
|
|
|
auto &NewMO = New.getOperand(I);
|
|
|
|
(void)NewMO;
|
[DebugInstrRef] Support recording of instruction reference substitutions
Add a table recording "substitutions" between pairs of <instruction,
operand> numbers, from old pairs to new pairs. Post-isel optimizations are
able to record the outcome of an optimization in this way. For example, if
there were a divide instruction that generated the quotient and remainder,
and it were replaced by one that only generated the quotient:
$rax, $rcx = DIV-AND-REMAINDER $rdx, $rsi, debug-instr-num 1
DBG_INSTR_REF 1, 0
DBG_INSTR_REF 1, 1
Became:
$rax = DIV $rdx, $rsi, debug-instr-num 2
DBG_INSTR_REF 1, 0
DBG_INSTR_REF 1, 1
We could enter a substitution from <1, 0> to <2, 0>, and no substitution
for <1, 1> as it's no longer generated.
This approach means that if an instruction or value is deleted once we've
left SSA form, all variables that used the value implicitly become
"optimized out", something that isn't true of the current DBG_VALUE
approach.
Differential Revision: https://reviews.llvm.org/D85749
2020-10-15 18:20:29 +08:00
|
|
|
|
|
|
|
if (!OldMO.isReg() || !OldMO.isDef())
|
|
|
|
continue;
|
2020-10-21 21:28:28 +08:00
|
|
|
assert(NewMO.isDef());
|
[DebugInstrRef] Support recording of instruction reference substitutions
Add a table recording "substitutions" between pairs of <instruction,
operand> numbers, from old pairs to new pairs. Post-isel optimizations are
able to record the outcome of an optimization in this way. For example, if
there were a divide instruction that generated the quotient and remainder,
and it were replaced by one that only generated the quotient:
$rax, $rcx = DIV-AND-REMAINDER $rdx, $rsi, debug-instr-num 1
DBG_INSTR_REF 1, 0
DBG_INSTR_REF 1, 1
Became:
$rax = DIV $rdx, $rsi, debug-instr-num 2
DBG_INSTR_REF 1, 0
DBG_INSTR_REF 1, 1
We could enter a substitution from <1, 0> to <2, 0>, and no substitution
for <1, 1> as it's no longer generated.
This approach means that if an instruction or value is deleted once we've
left SSA form, all variables that used the value implicitly become
"optimized out", something that isn't true of the current DBG_VALUE
approach.
Differential Revision: https://reviews.llvm.org/D85749
2020-10-15 18:20:29 +08:00
|
|
|
|
|
|
|
unsigned NewInstrNum = New.getDebugInstrNum();
|
|
|
|
makeDebugValueSubstitution(std::make_pair(OldInstrNum, I),
|
|
|
|
std::make_pair(NewInstrNum, I));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-05-03 16:42:27 +08:00
|
|
|
auto MachineFunction::salvageCopySSA(
|
|
|
|
MachineInstr &MI, DenseMap<Register, DebugInstrOperandPair> &DbgPHICache)
|
|
|
|
-> DebugInstrOperandPair {
|
|
|
|
const TargetInstrInfo &TII = *getSubtarget().getInstrInfo();
|
|
|
|
|
|
|
|
// Check whether this copy-like instruction has already been salvaged into
|
|
|
|
// an operand pair.
|
|
|
|
Register Dest;
|
|
|
|
if (auto CopyDstSrc = TII.isCopyInstr(MI)) {
|
|
|
|
Dest = CopyDstSrc->Destination->getReg();
|
|
|
|
} else {
|
|
|
|
assert(MI.isSubregToReg());
|
|
|
|
Dest = MI.getOperand(0).getReg();
|
|
|
|
}
|
|
|
|
|
|
|
|
auto CacheIt = DbgPHICache.find(Dest);
|
|
|
|
if (CacheIt != DbgPHICache.end())
|
|
|
|
return CacheIt->second;
|
|
|
|
|
|
|
|
// Calculate the instruction number to use, or install a DBG_PHI.
|
|
|
|
auto OperandPair = salvageCopySSAImpl(MI);
|
|
|
|
DbgPHICache.insert({Dest, OperandPair});
|
|
|
|
return OperandPair;
|
|
|
|
}
|
|
|
|
|
|
|
|
auto MachineFunction::salvageCopySSAImpl(MachineInstr &MI)
|
[DebugInfo][InstrRef][3/4] Produce DBG_INSTR_REFs for all variable locations
This patch emits DBG_INSTR_REFs for two remaining flavours of variable
locations that weren't supported: copies, and inter-block VRegs. There are
still some locations that must be represented by DBG_VALUE such as
constants, but they're mostly independent of optimisations.
For variable locations that refer to values defined in different blocks,
vregs are allocated before isel begins, but the defining instruction
might not exist until late in isel. To get around this, emit
DBG_INSTR_REFs in a "half done" state, where the first operand refers to a
VReg. Then at the end of isel, patch these back up to refer to
instructions, using the finalizeDebugInstrRefs method.
Copies are something that I complained about the original RFC, and I
really don't want to have to put instruction numbers on copies. They don't
define a value: they move them. To address this isel, salvageCopySSA
interprets:
* COPYs,
* SUBREG_TO_REG,
* Anything that isCopyInstr thinks is a copy.
And follows chains of copies back to the defining instruction that they
read from. This relies on any physical registers that COPYs read being
defined in the same block, or being entry-block arguments. For the former
we can put an instruction number on the defining instruction; for the
latter we can drop a DBG_PHI that reads the incoming value.
Differential Revision: https://reviews.llvm.org/D88896
2021-06-02 22:14:37 +08:00
|
|
|
-> DebugInstrOperandPair {
|
|
|
|
MachineRegisterInfo &MRI = getRegInfo();
|
|
|
|
const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
|
|
|
|
const TargetInstrInfo &TII = *getSubtarget().getInstrInfo();
|
|
|
|
|
|
|
|
// Chase the value read by a copy-like instruction back to the instruction
|
|
|
|
// that ultimately _defines_ that value. This may pass:
|
|
|
|
// * Through multiple intermediate copies, including subregister moves /
|
|
|
|
// copies,
|
|
|
|
// * Copies from physical registers that must then be traced back to the
|
|
|
|
// defining instruction,
|
|
|
|
// * Or, physical registers may be live-in to (only) the entry block, which
|
|
|
|
// requires a DBG_PHI to be created.
|
|
|
|
// We can pursue this problem in that order: trace back through copies,
|
|
|
|
// optionally through a physical register, to a defining instruction. We
|
|
|
|
// should never move from physreg to vreg. As we're still in SSA form, no need
|
|
|
|
// to worry about partial definitions of registers.
|
|
|
|
|
|
|
|
// Helper lambda to interpret a copy-like instruction. Takes instruction,
|
|
|
|
// returns the register read and any subregister identifying which part is
|
|
|
|
// read.
|
|
|
|
auto GetRegAndSubreg =
|
|
|
|
[&](const MachineInstr &Cpy) -> std::pair<Register, unsigned> {
|
|
|
|
Register NewReg, OldReg;
|
|
|
|
unsigned SubReg;
|
|
|
|
if (Cpy.isCopy()) {
|
|
|
|
OldReg = Cpy.getOperand(0).getReg();
|
|
|
|
NewReg = Cpy.getOperand(1).getReg();
|
|
|
|
SubReg = Cpy.getOperand(1).getSubReg();
|
|
|
|
} else if (Cpy.isSubregToReg()) {
|
|
|
|
OldReg = Cpy.getOperand(0).getReg();
|
|
|
|
NewReg = Cpy.getOperand(2).getReg();
|
|
|
|
SubReg = Cpy.getOperand(3).getImm();
|
|
|
|
} else {
|
|
|
|
auto CopyDetails = *TII.isCopyInstr(Cpy);
|
|
|
|
const MachineOperand &Src = *CopyDetails.Source;
|
|
|
|
const MachineOperand &Dest = *CopyDetails.Destination;
|
|
|
|
OldReg = Dest.getReg();
|
|
|
|
NewReg = Src.getReg();
|
|
|
|
SubReg = Src.getSubReg();
|
|
|
|
}
|
|
|
|
|
|
|
|
return {NewReg, SubReg};
|
|
|
|
};
|
|
|
|
|
|
|
|
// First seek either the defining instruction, or a copy from a physreg.
|
|
|
|
// During search, the current state is the current copy instruction, and which
|
|
|
|
// register we've read. Accumulate qualifying subregisters into SubregsSeen;
|
|
|
|
// deal with those later.
|
|
|
|
auto State = GetRegAndSubreg(MI);
|
|
|
|
auto CurInst = MI.getIterator();
|
|
|
|
SmallVector<unsigned, 4> SubregsSeen;
|
|
|
|
while (true) {
|
|
|
|
// If we've found a copy from a physreg, first portion of search is over.
|
|
|
|
if (!State.first.isVirtual())
|
|
|
|
break;
|
|
|
|
|
|
|
|
// Record any subregister qualifier.
|
|
|
|
if (State.second)
|
|
|
|
SubregsSeen.push_back(State.second);
|
|
|
|
|
|
|
|
assert(MRI.hasOneDef(State.first));
|
|
|
|
MachineInstr &Inst = *MRI.def_begin(State.first)->getParent();
|
|
|
|
CurInst = Inst.getIterator();
|
|
|
|
|
|
|
|
// Any non-copy instruction is the defining instruction we're seeking.
|
|
|
|
if (!Inst.isCopyLike() && !TII.isCopyInstr(Inst))
|
|
|
|
break;
|
|
|
|
State = GetRegAndSubreg(Inst);
|
|
|
|
};
|
|
|
|
|
|
|
|
// Helper lambda to apply additional subregister substitutions to a known
|
|
|
|
// instruction/operand pair. Adds new (fake) substitutions so that we can
|
|
|
|
// record the subregister. FIXME: this isn't very space efficient if multiple
|
|
|
|
// values are tracked back through the same copies; cache something later.
|
|
|
|
auto ApplySubregisters =
|
|
|
|
[&](DebugInstrOperandPair P) -> DebugInstrOperandPair {
|
|
|
|
for (unsigned Subreg : reverse(SubregsSeen)) {
|
|
|
|
// Fetch a new instruction number, not attached to an actual instruction.
|
|
|
|
unsigned NewInstrNumber = getNewDebugInstrNum();
|
|
|
|
// Add a substitution from the "new" number to the known one, with a
|
|
|
|
// qualifying subreg.
|
|
|
|
makeDebugValueSubstitution({NewInstrNumber, 0}, P, Subreg);
|
|
|
|
// Return the new number; to find the underlying value, consumers need to
|
|
|
|
// deal with the qualifying subreg.
|
|
|
|
P = {NewInstrNumber, 0};
|
|
|
|
}
|
|
|
|
return P;
|
|
|
|
};
|
|
|
|
|
|
|
|
// If we managed to find the defining instruction after COPYs, return an
|
|
|
|
// instruction / operand pair after adding subregister qualifiers.
|
|
|
|
if (State.first.isVirtual()) {
|
|
|
|
// Virtual register def -- we can just look up where this happens.
|
|
|
|
MachineInstr *Inst = MRI.def_begin(State.first)->getParent();
|
|
|
|
for (auto &MO : Inst->operands()) {
|
|
|
|
if (!MO.isReg() || !MO.isDef() || MO.getReg() != State.first)
|
|
|
|
continue;
|
|
|
|
return ApplySubregisters(
|
|
|
|
{Inst->getDebugInstrNum(), Inst->getOperandNo(&MO)});
|
|
|
|
}
|
|
|
|
|
|
|
|
llvm_unreachable("Vreg def with no corresponding operand?");
|
|
|
|
}
|
|
|
|
|
|
|
|
// Our search ended in a copy from a physreg: walk back up the function
|
|
|
|
// looking for whatever defines the physreg.
|
|
|
|
assert(CurInst->isCopyLike() || TII.isCopyInstr(*CurInst));
|
|
|
|
State = GetRegAndSubreg(*CurInst);
|
|
|
|
Register RegToSeek = State.first;
|
|
|
|
|
|
|
|
auto RMII = CurInst->getReverseIterator();
|
|
|
|
auto PrevInstrs = make_range(RMII, CurInst->getParent()->instr_rend());
|
|
|
|
for (auto &ToExamine : PrevInstrs) {
|
|
|
|
for (auto &MO : ToExamine.operands()) {
|
|
|
|
// Test for operand that defines something aliasing RegToSeek.
|
|
|
|
if (!MO.isReg() || !MO.isDef() ||
|
|
|
|
!TRI.regsOverlap(RegToSeek, MO.getReg()))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
return ApplySubregisters(
|
|
|
|
{ToExamine.getDebugInstrNum(), ToExamine.getOperandNo(&MO)});
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-07-26 22:00:08 +08:00
|
|
|
MachineBasicBlock &InsertBB = *CurInst->getParent();
|
|
|
|
|
[DebugInfo][InstrRef][3/4] Produce DBG_INSTR_REFs for all variable locations
This patch emits DBG_INSTR_REFs for two remaining flavours of variable
locations that weren't supported: copies, and inter-block VRegs. There are
still some locations that must be represented by DBG_VALUE such as
constants, but they're mostly independent of optimisations.
For variable locations that refer to values defined in different blocks,
vregs are allocated before isel begins, but the defining instruction
might not exist until late in isel. To get around this, emit
DBG_INSTR_REFs in a "half done" state, where the first operand refers to a
VReg. Then at the end of isel, patch these back up to refer to
instructions, using the finalizeDebugInstrRefs method.
Copies are something that I complained about the original RFC, and I
really don't want to have to put instruction numbers on copies. They don't
define a value: they move them. To address this isel, salvageCopySSA
interprets:
* COPYs,
* SUBREG_TO_REG,
* Anything that isCopyInstr thinks is a copy.
And follows chains of copies back to the defining instruction that they
read from. This relies on any physical registers that COPYs read being
defined in the same block, or being entry-block arguments. For the former
we can put an instruction number on the defining instruction; for the
latter we can drop a DBG_PHI that reads the incoming value.
Differential Revision: https://reviews.llvm.org/D88896
2021-06-02 22:14:37 +08:00
|
|
|
// We reached the start of the block before finding a defining instruction.
|
2022-03-05 00:39:22 +08:00
|
|
|
// There are numerous scenarios where this can happen:
|
|
|
|
// * Constant physical registers,
|
|
|
|
// * Several intrinsics that allow LLVM-IR to read arbitary registers,
|
|
|
|
// * Arguments in the entry block,
|
|
|
|
// * Exception handling landing pads.
|
|
|
|
// Validating all of them is too difficult, so just insert a DBG_PHI reading
|
|
|
|
// the variable value at this position, rather than checking it makes sense.
|
[DebugInfo][InstrRef][3/4] Produce DBG_INSTR_REFs for all variable locations
This patch emits DBG_INSTR_REFs for two remaining flavours of variable
locations that weren't supported: copies, and inter-block VRegs. There are
still some locations that must be represented by DBG_VALUE such as
constants, but they're mostly independent of optimisations.
For variable locations that refer to values defined in different blocks,
vregs are allocated before isel begins, but the defining instruction
might not exist until late in isel. To get around this, emit
DBG_INSTR_REFs in a "half done" state, where the first operand refers to a
VReg. Then at the end of isel, patch these back up to refer to
instructions, using the finalizeDebugInstrRefs method.
Copies are something that I complained about the original RFC, and I
really don't want to have to put instruction numbers on copies. They don't
define a value: they move them. To address this isel, salvageCopySSA
interprets:
* COPYs,
* SUBREG_TO_REG,
* Anything that isCopyInstr thinks is a copy.
And follows chains of copies back to the defining instruction that they
read from. This relies on any physical registers that COPYs read being
defined in the same block, or being entry-block arguments. For the former
we can put an instruction number on the defining instruction; for the
latter we can drop a DBG_PHI that reads the incoming value.
Differential Revision: https://reviews.llvm.org/D88896
2021-06-02 22:14:37 +08:00
|
|
|
|
|
|
|
// Create DBG_PHI for specified physreg.
|
2021-07-26 22:00:08 +08:00
|
|
|
auto Builder = BuildMI(InsertBB, InsertBB.getFirstNonPHI(), DebugLoc(),
|
[DebugInfo][InstrRef][3/4] Produce DBG_INSTR_REFs for all variable locations
This patch emits DBG_INSTR_REFs for two remaining flavours of variable
locations that weren't supported: copies, and inter-block VRegs. There are
still some locations that must be represented by DBG_VALUE such as
constants, but they're mostly independent of optimisations.
For variable locations that refer to values defined in different blocks,
vregs are allocated before isel begins, but the defining instruction
might not exist until late in isel. To get around this, emit
DBG_INSTR_REFs in a "half done" state, where the first operand refers to a
VReg. Then at the end of isel, patch these back up to refer to
instructions, using the finalizeDebugInstrRefs method.
Copies are something that I complained about the original RFC, and I
really don't want to have to put instruction numbers on copies. They don't
define a value: they move them. To address this isel, salvageCopySSA
interprets:
* COPYs,
* SUBREG_TO_REG,
* Anything that isCopyInstr thinks is a copy.
And follows chains of copies back to the defining instruction that they
read from. This relies on any physical registers that COPYs read being
defined in the same block, or being entry-block arguments. For the former
we can put an instruction number on the defining instruction; for the
latter we can drop a DBG_PHI that reads the incoming value.
Differential Revision: https://reviews.llvm.org/D88896
2021-06-02 22:14:37 +08:00
|
|
|
TII.get(TargetOpcode::DBG_PHI));
|
2021-10-07 23:02:30 +08:00
|
|
|
Builder.addReg(State.first);
|
[DebugInfo][InstrRef][3/4] Produce DBG_INSTR_REFs for all variable locations
This patch emits DBG_INSTR_REFs for two remaining flavours of variable
locations that weren't supported: copies, and inter-block VRegs. There are
still some locations that must be represented by DBG_VALUE such as
constants, but they're mostly independent of optimisations.
For variable locations that refer to values defined in different blocks,
vregs are allocated before isel begins, but the defining instruction
might not exist until late in isel. To get around this, emit
DBG_INSTR_REFs in a "half done" state, where the first operand refers to a
VReg. Then at the end of isel, patch these back up to refer to
instructions, using the finalizeDebugInstrRefs method.
Copies are something that I complained about the original RFC, and I
really don't want to have to put instruction numbers on copies. They don't
define a value: they move them. To address this isel, salvageCopySSA
interprets:
* COPYs,
* SUBREG_TO_REG,
* Anything that isCopyInstr thinks is a copy.
And follows chains of copies back to the defining instruction that they
read from. This relies on any physical registers that COPYs read being
defined in the same block, or being entry-block arguments. For the former
we can put an instruction number on the defining instruction; for the
latter we can drop a DBG_PHI that reads the incoming value.
Differential Revision: https://reviews.llvm.org/D88896
2021-06-02 22:14:37 +08:00
|
|
|
unsigned NewNum = getNewDebugInstrNum();
|
|
|
|
Builder.addImm(NewNum);
|
|
|
|
return ApplySubregisters({NewNum, 0u});
|
|
|
|
}
|
|
|
|
|
|
|
|
void MachineFunction::finalizeDebugInstrRefs() {
|
|
|
|
auto *TII = getSubtarget().getInstrInfo();
|
|
|
|
|
2021-11-24 18:20:03 +08:00
|
|
|
auto MakeUndefDbgValue = [&](MachineInstr &MI) {
|
[DebugInfo][InstrRef][3/4] Produce DBG_INSTR_REFs for all variable locations
This patch emits DBG_INSTR_REFs for two remaining flavours of variable
locations that weren't supported: copies, and inter-block VRegs. There are
still some locations that must be represented by DBG_VALUE such as
constants, but they're mostly independent of optimisations.
For variable locations that refer to values defined in different blocks,
vregs are allocated before isel begins, but the defining instruction
might not exist until late in isel. To get around this, emit
DBG_INSTR_REFs in a "half done" state, where the first operand refers to a
VReg. Then at the end of isel, patch these back up to refer to
instructions, using the finalizeDebugInstrRefs method.
Copies are something that I complained about the original RFC, and I
really don't want to have to put instruction numbers on copies. They don't
define a value: they move them. To address this isel, salvageCopySSA
interprets:
* COPYs,
* SUBREG_TO_REG,
* Anything that isCopyInstr thinks is a copy.
And follows chains of copies back to the defining instruction that they
read from. This relies on any physical registers that COPYs read being
defined in the same block, or being entry-block arguments. For the former
we can put an instruction number on the defining instruction; for the
latter we can drop a DBG_PHI that reads the incoming value.
Differential Revision: https://reviews.llvm.org/D88896
2021-06-02 22:14:37 +08:00
|
|
|
const MCInstrDesc &RefII = TII->get(TargetOpcode::DBG_VALUE);
|
|
|
|
MI.setDesc(RefII);
|
2021-11-24 18:20:03 +08:00
|
|
|
MI.getOperand(0).setReg(0);
|
[DebugInfo][InstrRef][3/4] Produce DBG_INSTR_REFs for all variable locations
This patch emits DBG_INSTR_REFs for two remaining flavours of variable
locations that weren't supported: copies, and inter-block VRegs. There are
still some locations that must be represented by DBG_VALUE such as
constants, but they're mostly independent of optimisations.
For variable locations that refer to values defined in different blocks,
vregs are allocated before isel begins, but the defining instruction
might not exist until late in isel. To get around this, emit
DBG_INSTR_REFs in a "half done" state, where the first operand refers to a
VReg. Then at the end of isel, patch these back up to refer to
instructions, using the finalizeDebugInstrRefs method.
Copies are something that I complained about the original RFC, and I
really don't want to have to put instruction numbers on copies. They don't
define a value: they move them. To address this isel, salvageCopySSA
interprets:
* COPYs,
* SUBREG_TO_REG,
* Anything that isCopyInstr thinks is a copy.
And follows chains of copies back to the defining instruction that they
read from. This relies on any physical registers that COPYs read being
defined in the same block, or being entry-block arguments. For the former
we can put an instruction number on the defining instruction; for the
latter we can drop a DBG_PHI that reads the incoming value.
Differential Revision: https://reviews.llvm.org/D88896
2021-06-02 22:14:37 +08:00
|
|
|
MI.getOperand(1).ChangeToRegister(0, false);
|
|
|
|
};
|
|
|
|
|
2022-05-03 16:42:27 +08:00
|
|
|
DenseMap<Register, DebugInstrOperandPair> ArgDbgPHIs;
|
[DebugInfo][InstrRef][3/4] Produce DBG_INSTR_REFs for all variable locations
This patch emits DBG_INSTR_REFs for two remaining flavours of variable
locations that weren't supported: copies, and inter-block VRegs. There are
still some locations that must be represented by DBG_VALUE such as
constants, but they're mostly independent of optimisations.
For variable locations that refer to values defined in different blocks,
vregs are allocated before isel begins, but the defining instruction
might not exist until late in isel. To get around this, emit
DBG_INSTR_REFs in a "half done" state, where the first operand refers to a
VReg. Then at the end of isel, patch these back up to refer to
instructions, using the finalizeDebugInstrRefs method.
Copies are something that I complained about the original RFC, and I
really don't want to have to put instruction numbers on copies. They don't
define a value: they move them. To address this isel, salvageCopySSA
interprets:
* COPYs,
* SUBREG_TO_REG,
* Anything that isCopyInstr thinks is a copy.
And follows chains of copies back to the defining instruction that they
read from. This relies on any physical registers that COPYs read being
defined in the same block, or being entry-block arguments. For the former
we can put an instruction number on the defining instruction; for the
latter we can drop a DBG_PHI that reads the incoming value.
Differential Revision: https://reviews.llvm.org/D88896
2021-06-02 22:14:37 +08:00
|
|
|
for (auto &MBB : *this) {
|
|
|
|
for (auto &MI : MBB) {
|
|
|
|
if (!MI.isDebugRef() || !MI.getOperand(0).isReg())
|
|
|
|
continue;
|
|
|
|
|
|
|
|
Register Reg = MI.getOperand(0).getReg();
|
|
|
|
|
|
|
|
// Some vregs can be deleted as redundant in the meantime. Mark those
|
2021-11-24 18:20:03 +08:00
|
|
|
// as DBG_VALUE $noreg. Additionally, some normal instructions are
|
|
|
|
// quickly deleted, leaving dangling references to vregs with no def.
|
|
|
|
if (Reg == 0 || !RegInfo->hasOneDef(Reg)) {
|
|
|
|
MakeUndefDbgValue(MI);
|
[DebugInfo][InstrRef][3/4] Produce DBG_INSTR_REFs for all variable locations
This patch emits DBG_INSTR_REFs for two remaining flavours of variable
locations that weren't supported: copies, and inter-block VRegs. There are
still some locations that must be represented by DBG_VALUE such as
constants, but they're mostly independent of optimisations.
For variable locations that refer to values defined in different blocks,
vregs are allocated before isel begins, but the defining instruction
might not exist until late in isel. To get around this, emit
DBG_INSTR_REFs in a "half done" state, where the first operand refers to a
VReg. Then at the end of isel, patch these back up to refer to
instructions, using the finalizeDebugInstrRefs method.
Copies are something that I complained about the original RFC, and I
really don't want to have to put instruction numbers on copies. They don't
define a value: they move them. To address this isel, salvageCopySSA
interprets:
* COPYs,
* SUBREG_TO_REG,
* Anything that isCopyInstr thinks is a copy.
And follows chains of copies back to the defining instruction that they
read from. This relies on any physical registers that COPYs read being
defined in the same block, or being entry-block arguments. For the former
we can put an instruction number on the defining instruction; for the
latter we can drop a DBG_PHI that reads the incoming value.
Differential Revision: https://reviews.llvm.org/D88896
2021-06-02 22:14:37 +08:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
assert(Reg.isVirtual());
|
|
|
|
MachineInstr &DefMI = *RegInfo->def_instr_begin(Reg);
|
|
|
|
|
|
|
|
// If we've found a copy-like instruction, follow it back to the
|
|
|
|
// instruction that defines the source value, see salvageCopySSA docs
|
|
|
|
// for why this is important.
|
|
|
|
if (DefMI.isCopyLike() || TII->isCopyInstr(DefMI)) {
|
2022-05-03 16:42:27 +08:00
|
|
|
auto Result = salvageCopySSA(DefMI, ArgDbgPHIs);
|
[DebugInfo][InstrRef][3/4] Produce DBG_INSTR_REFs for all variable locations
This patch emits DBG_INSTR_REFs for two remaining flavours of variable
locations that weren't supported: copies, and inter-block VRegs. There are
still some locations that must be represented by DBG_VALUE such as
constants, but they're mostly independent of optimisations.
For variable locations that refer to values defined in different blocks,
vregs are allocated before isel begins, but the defining instruction
might not exist until late in isel. To get around this, emit
DBG_INSTR_REFs in a "half done" state, where the first operand refers to a
VReg. Then at the end of isel, patch these back up to refer to
instructions, using the finalizeDebugInstrRefs method.
Copies are something that I complained about the original RFC, and I
really don't want to have to put instruction numbers on copies. They don't
define a value: they move them. To address this isel, salvageCopySSA
interprets:
* COPYs,
* SUBREG_TO_REG,
* Anything that isCopyInstr thinks is a copy.
And follows chains of copies back to the defining instruction that they
read from. This relies on any physical registers that COPYs read being
defined in the same block, or being entry-block arguments. For the former
we can put an instruction number on the defining instruction; for the
latter we can drop a DBG_PHI that reads the incoming value.
Differential Revision: https://reviews.llvm.org/D88896
2021-06-02 22:14:37 +08:00
|
|
|
MI.getOperand(0).ChangeToImmediate(Result.first);
|
|
|
|
MI.getOperand(1).setImm(Result.second);
|
|
|
|
} else {
|
|
|
|
// Otherwise, identify the operand number that the VReg refers to.
|
|
|
|
unsigned OperandIdx = 0;
|
|
|
|
for (const auto &MO : DefMI.operands()) {
|
|
|
|
if (MO.isReg() && MO.isDef() && MO.getReg() == Reg)
|
|
|
|
break;
|
|
|
|
++OperandIdx;
|
|
|
|
}
|
|
|
|
assert(OperandIdx < DefMI.getNumOperands());
|
|
|
|
|
|
|
|
// Morph this instr ref to point at the given instruction and operand.
|
|
|
|
unsigned ID = DefMI.getDebugInstrNum();
|
|
|
|
MI.getOperand(0).ChangeToImmediate(ID);
|
|
|
|
MI.getOperand(1).setImm(OperandIdx);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-08-25 21:56:05 +08:00
|
|
|
bool MachineFunction::useDebugInstrRef() const {
|
|
|
|
// Disable instr-ref at -O0: it's very slow (in compile time). We can still
|
|
|
|
// have optimized code inlined into this unoptimized code, however with
|
|
|
|
// fewer and less aggressive optimizations happening, coverage and accuracy
|
|
|
|
// should not suffer.
|
|
|
|
if (getTarget().getOptLevel() == CodeGenOpt::None)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Don't use instr-ref if this function is marked optnone.
|
|
|
|
if (F.hasFnAttribute(Attribute::OptimizeNone))
|
|
|
|
return false;
|
|
|
|
|
2022-01-12 20:35:36 +08:00
|
|
|
if (llvm::debuginfoShouldUseDebugInstrRef(getTarget().getTargetTriple()))
|
2021-08-25 21:56:05 +08:00
|
|
|
return true;
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2021-10-25 22:09:42 +08:00
|
|
|
// Use one million as a high / reserved number.
|
|
|
|
const unsigned MachineFunction::DebugOperandMemNumber = 1000000;
|
|
|
|
|
2016-12-02 03:32:15 +08:00
|
|
|
/// \}
|
|
|
|
|
2006-04-23 02:53:45 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// MachineJumpTableInfo implementation
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2015-06-13 23:32:45 +08:00
|
|
|
/// Return the size of each entry in the jump table.
|
2012-10-09 00:38:25 +08:00
|
|
|
unsigned MachineJumpTableInfo::getEntrySize(const DataLayout &TD) const {
|
2010-01-26 07:26:13 +08:00
|
|
|
// The size of a jump table entry is 4 bytes unless the entry is just the
|
|
|
|
// address of a block, in which case it is the pointer size.
|
|
|
|
switch (getEntryKind()) {
|
|
|
|
case MachineJumpTableInfo::EK_BlockAddress:
|
Revert the majority of the next patch in the address space series:
r165941: Resubmit the changes to llvm core to update the functions to
support different pointer sizes on a per address space basis.
Despite this commit log, this change primarily changed stuff outside of
VMCore, and those changes do not carry any tests for correctness (or
even plausibility), and we have consistently found questionable or flat
out incorrect cases in these changes. Most of them are probably correct,
but we need to devise a system that makes it more clear when we have
handled the address space concerns correctly, and ideally each pass that
gets updated would receive an accompanying test case that exercises that
pass specificaly w.r.t. alternate address spaces.
However, from this commit, I have retained the new C API entry points.
Those were an orthogonal change that probably should have been split
apart, but they seem entirely good.
In several places the changes were very obvious cleanups with no actual
multiple address space code added; these I have not reverted when
I spotted them.
In a few other places there were merge conflicts due to a cleaner
solution being implemented later, often not using address spaces at all.
In those cases, I've preserved the new code which isn't address space
dependent.
This is part of my ongoing effort to clean out the partial address space
code which carries high risk and low test coverage, and not likely to be
finished before the 3.2 release looms closer. Duncan and I would both
like to see the above issues addressed before we return to these
changes.
llvm-svn: 167222
2012-11-01 17:14:31 +08:00
|
|
|
return TD.getPointerSize();
|
2012-02-03 12:33:00 +08:00
|
|
|
case MachineJumpTableInfo::EK_GPRel64BlockAddress:
|
|
|
|
return 8;
|
2010-01-26 07:26:13 +08:00
|
|
|
case MachineJumpTableInfo::EK_GPRel32BlockAddress:
|
|
|
|
case MachineJumpTableInfo::EK_LabelDifference32:
|
2010-01-26 12:05:28 +08:00
|
|
|
case MachineJumpTableInfo::EK_Custom32:
|
2010-01-26 07:26:13 +08:00
|
|
|
return 4;
|
2010-03-11 22:58:16 +08:00
|
|
|
case MachineJumpTableInfo::EK_Inline:
|
|
|
|
return 0;
|
2010-01-26 07:26:13 +08:00
|
|
|
}
|
2012-02-06 16:17:43 +08:00
|
|
|
llvm_unreachable("Unknown jump table encoding!");
|
2010-01-26 07:26:13 +08:00
|
|
|
}
|
|
|
|
|
2015-06-13 23:32:45 +08:00
|
|
|
/// Return the alignment of each entry in the jump table.
|
2012-10-09 00:38:25 +08:00
|
|
|
unsigned MachineJumpTableInfo::getEntryAlignment(const DataLayout &TD) const {
|
2010-01-26 07:26:13 +08:00
|
|
|
// The alignment of a jump table entry is the alignment of int32 unless the
|
|
|
|
// entry is just the address of a block, in which case it is the pointer
|
|
|
|
// alignment.
|
|
|
|
switch (getEntryKind()) {
|
|
|
|
case MachineJumpTableInfo::EK_BlockAddress:
|
2019-09-23 20:41:36 +08:00
|
|
|
return TD.getPointerABIAlignment(0).value();
|
2012-02-03 12:33:00 +08:00
|
|
|
case MachineJumpTableInfo::EK_GPRel64BlockAddress:
|
2019-09-23 20:41:36 +08:00
|
|
|
return TD.getABIIntegerTypeAlignment(64).value();
|
2010-01-26 07:26:13 +08:00
|
|
|
case MachineJumpTableInfo::EK_GPRel32BlockAddress:
|
|
|
|
case MachineJumpTableInfo::EK_LabelDifference32:
|
2010-01-26 12:05:28 +08:00
|
|
|
case MachineJumpTableInfo::EK_Custom32:
|
2019-09-23 20:41:36 +08:00
|
|
|
return TD.getABIIntegerTypeAlignment(32).value();
|
2010-03-11 22:58:16 +08:00
|
|
|
case MachineJumpTableInfo::EK_Inline:
|
|
|
|
return 1;
|
2010-01-26 07:26:13 +08:00
|
|
|
}
|
2012-02-06 16:17:43 +08:00
|
|
|
llvm_unreachable("Unknown jump table encoding!");
|
2010-01-26 07:26:13 +08:00
|
|
|
}
|
|
|
|
|
2015-06-13 23:32:45 +08:00
|
|
|
/// Create a new jump table entry in the jump table info.
|
Fix pr6543: svn r88806 changed MachineJumpTableInfo::getJumpTableIndex() to
always create a new jump table. The intention was to avoid merging jump
tables in SelectionDAGBuilder, and to wait for the branch folding pass to
merge tables. Unfortunately, the same getJumpTableIndex() method is also
used to merge tables in branch folding, so as a result of this change
branch tables are never merged. Worse, the branch folding code is expecting
getJumpTableIndex to always return the index of an existing table, but with
this change, it never does so. In at least some cases, e.g., pr6543, this
creates references to non-existent tables.
I've fixed the problem by adding a new createJumpTableIndex function, which
will always create a new table, and I've changed getJumpTableIndex to only
look at existing tables.
llvm-svn: 98845
2010-03-19 02:42:41 +08:00
|
|
|
unsigned MachineJumpTableInfo::createJumpTableIndex(
|
2006-10-29 02:17:09 +08:00
|
|
|
const std::vector<MachineBasicBlock*> &DestBBs) {
|
2006-10-29 02:11:20 +08:00
|
|
|
assert(!DestBBs.empty() && "Cannot create an empty jump table!");
|
2006-04-23 02:53:45 +08:00
|
|
|
JumpTables.push_back(MachineJumpTableEntry(DestBBs));
|
|
|
|
return JumpTables.size()-1;
|
|
|
|
}
|
|
|
|
|
2015-06-13 23:32:45 +08:00
|
|
|
/// If Old is the target of any jump tables, update the jump tables to branch
|
|
|
|
/// to New instead.
|
2010-01-26 13:58:28 +08:00
|
|
|
bool MachineJumpTableInfo::ReplaceMBBInJumpTables(MachineBasicBlock *Old,
|
|
|
|
MachineBasicBlock *New) {
|
2009-04-15 09:18:49 +08:00
|
|
|
assert(Old != New && "Not making a change?");
|
|
|
|
bool MadeChange = false;
|
2009-11-15 04:09:13 +08:00
|
|
|
for (size_t i = 0, e = JumpTables.size(); i != e; ++i)
|
|
|
|
ReplaceMBBInJumpTable(i, Old, New);
|
|
|
|
return MadeChange;
|
|
|
|
}
|
|
|
|
|
2020-11-17 00:33:06 +08:00
|
|
|
/// If MBB is present in any jump tables, remove it.
|
|
|
|
bool MachineJumpTableInfo::RemoveMBBFromJumpTables(MachineBasicBlock *MBB) {
|
|
|
|
bool MadeChange = false;
|
|
|
|
for (MachineJumpTableEntry &JTE : JumpTables) {
|
|
|
|
auto removeBeginItr = std::remove(JTE.MBBs.begin(), JTE.MBBs.end(), MBB);
|
|
|
|
MadeChange |= (removeBeginItr != JTE.MBBs.end());
|
|
|
|
JTE.MBBs.erase(removeBeginItr, JTE.MBBs.end());
|
|
|
|
}
|
|
|
|
return MadeChange;
|
|
|
|
}
|
|
|
|
|
2015-06-13 23:32:45 +08:00
|
|
|
/// If Old is a target of the jump tables, update the jump table to branch to
|
|
|
|
/// New instead.
|
2010-01-26 13:58:28 +08:00
|
|
|
bool MachineJumpTableInfo::ReplaceMBBInJumpTable(unsigned Idx,
|
|
|
|
MachineBasicBlock *Old,
|
|
|
|
MachineBasicBlock *New) {
|
2009-11-15 04:09:13 +08:00
|
|
|
assert(Old != New && "Not making a change?");
|
|
|
|
bool MadeChange = false;
|
|
|
|
MachineJumpTableEntry &JTE = JumpTables[Idx];
|
2021-11-23 12:33:27 +08:00
|
|
|
for (MachineBasicBlock *&MBB : JTE.MBBs)
|
|
|
|
if (MBB == Old) {
|
|
|
|
MBB = New;
|
2009-11-15 04:09:13 +08:00
|
|
|
MadeChange = true;
|
|
|
|
}
|
2009-04-15 09:18:49 +08:00
|
|
|
return MadeChange;
|
|
|
|
}
|
2006-04-23 02:53:45 +08:00
|
|
|
|
2009-08-23 09:12:47 +08:00
|
|
|
void MachineJumpTableInfo::print(raw_ostream &OS) const {
|
2009-11-01 04:19:03 +08:00
|
|
|
if (JumpTables.empty()) return;
|
|
|
|
|
|
|
|
OS << "Jump Tables:\n";
|
|
|
|
|
2006-04-23 02:53:45 +08:00
|
|
|
for (unsigned i = 0, e = JumpTables.size(); i != e; ++i) {
|
2019-06-26 23:11:31 +08:00
|
|
|
OS << printJumpTableEntryReference(i) << ':';
|
2021-11-23 12:33:27 +08:00
|
|
|
for (const MachineBasicBlock *MBB : JumpTables[i].MBBs)
|
|
|
|
OS << ' ' << printMBBReference(*MBB);
|
2019-06-26 23:11:31 +08:00
|
|
|
if (i != e)
|
|
|
|
OS << '\n';
|
2006-04-23 02:53:45 +08:00
|
|
|
}
|
2009-11-01 04:19:03 +08:00
|
|
|
|
|
|
|
OS << '\n';
|
2006-04-23 02:53:45 +08:00
|
|
|
}
|
|
|
|
|
2017-10-15 22:32:27 +08:00
|
|
|
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
|
2016-01-30 04:50:44 +08:00
|
|
|
LLVM_DUMP_METHOD void MachineJumpTableInfo::dump() const { print(dbgs()); }
|
2012-09-07 03:06:06 +08:00
|
|
|
#endif
|
2006-04-23 02:53:45 +08:00
|
|
|
|
2017-12-13 18:30:59 +08:00
|
|
|
Printable llvm::printJumpTableEntryReference(unsigned Idx) {
|
|
|
|
return Printable([Idx](raw_ostream &OS) { OS << "%jump-table." << Idx; });
|
|
|
|
}
|
|
|
|
|
2003-01-13 08:23:03 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// MachineConstantPool implementation
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2017-10-11 06:33:29 +08:00
|
|
|
void MachineConstantPoolValue::anchor() {}
|
2011-12-20 10:50:00 +08:00
|
|
|
|
2021-01-05 11:22:45 +08:00
|
|
|
unsigned MachineConstantPoolValue::getSizeInBytes(const DataLayout &DL) const {
|
|
|
|
return DL.getTypeAllocSize(Ty);
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned MachineConstantPoolEntry::getSizeInBytes(const DataLayout &DL) const {
|
2006-09-14 13:50:57 +08:00
|
|
|
if (isMachineConstantPoolEntry())
|
2021-01-05 11:22:45 +08:00
|
|
|
return Val.MachineCPVal->getSizeInBytes(DL);
|
|
|
|
return DL.getTypeAllocSize(Val.ConstVal->getType());
|
2006-09-14 13:50:57 +08:00
|
|
|
}
|
|
|
|
|
2015-11-17 08:51:23 +08:00
|
|
|
bool MachineConstantPoolEntry::needsRelocation() const {
|
2009-07-22 07:34:23 +08:00
|
|
|
if (isMachineConstantPoolEntry())
|
2015-11-17 08:51:23 +08:00
|
|
|
return true;
|
2021-02-11 01:59:36 +08:00
|
|
|
return Val.ConstVal->needsDynamicRelocation();
|
2009-07-22 07:34:23 +08:00
|
|
|
}
|
|
|
|
|
2014-07-15 06:06:29 +08:00
|
|
|
SectionKind
|
|
|
|
MachineConstantPoolEntry::getSectionKind(const DataLayout *DL) const {
|
2015-11-17 08:51:23 +08:00
|
|
|
if (needsRelocation())
|
|
|
|
return SectionKind::getReadOnlyWithRel();
|
2021-01-05 11:22:45 +08:00
|
|
|
switch (getSizeInBytes(*DL)) {
|
2015-11-17 08:51:23 +08:00
|
|
|
case 4:
|
|
|
|
return SectionKind::getMergeableConst4();
|
|
|
|
case 8:
|
|
|
|
return SectionKind::getMergeableConst8();
|
|
|
|
case 16:
|
|
|
|
return SectionKind::getMergeableConst16();
|
2016-02-23 06:23:11 +08:00
|
|
|
case 32:
|
|
|
|
return SectionKind::getMergeableConst32();
|
2014-07-15 06:06:29 +08:00
|
|
|
default:
|
2015-11-17 08:51:23 +08:00
|
|
|
return SectionKind::getReadOnly();
|
2014-07-15 06:06:29 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-09-13 05:00:35 +08:00
|
|
|
MachineConstantPool::~MachineConstantPool() {
|
2016-09-26 15:26:24 +08:00
|
|
|
// A constant may be a member of both Constants and MachineCPVsSharingEntries,
|
|
|
|
// so keep track of which we've deleted to avoid double deletions.
|
|
|
|
DenseSet<MachineConstantPoolValue*> Deleted;
|
2021-12-05 00:48:04 +08:00
|
|
|
for (const MachineConstantPoolEntry &C : Constants)
|
|
|
|
if (C.isMachineConstantPoolEntry()) {
|
|
|
|
Deleted.insert(C.Val.MachineCPVal);
|
|
|
|
delete C.Val.MachineCPVal;
|
2016-09-26 15:26:24 +08:00
|
|
|
}
|
2021-02-16 06:46:10 +08:00
|
|
|
for (MachineConstantPoolValue *CPV : MachineCPVsSharingEntries) {
|
|
|
|
if (Deleted.count(CPV) == 0)
|
|
|
|
delete CPV;
|
2016-09-26 15:26:24 +08:00
|
|
|
}
|
2006-09-13 05:00:35 +08:00
|
|
|
}
|
|
|
|
|
2015-06-13 23:32:45 +08:00
|
|
|
/// Test whether the given two constants can be allocated the same constant pool
|
|
|
|
/// entry.
|
2010-04-15 09:51:59 +08:00
|
|
|
static bool CanShareConstantPoolEntry(const Constant *A, const Constant *B,
|
2015-07-08 02:20:57 +08:00
|
|
|
const DataLayout &DL) {
|
2009-10-28 09:12:16 +08:00
|
|
|
// Handle the trivial case quickly.
|
|
|
|
if (A == B) return true;
|
|
|
|
|
|
|
|
// If they have the same type but weren't the same constant, quickly
|
|
|
|
// reject them.
|
|
|
|
if (A->getType() == B->getType()) return false;
|
|
|
|
|
2012-01-27 09:46:00 +08:00
|
|
|
// We can't handle structs or arrays.
|
|
|
|
if (isa<StructType>(A->getType()) || isa<ArrayType>(A->getType()) ||
|
|
|
|
isa<StructType>(B->getType()) || isa<ArrayType>(B->getType()))
|
|
|
|
return false;
|
2014-06-25 20:40:56 +08:00
|
|
|
|
2009-10-28 09:12:16 +08:00
|
|
|
// For now, only support constants with the same size.
|
2015-07-08 02:20:57 +08:00
|
|
|
uint64_t StoreSize = DL.getTypeStoreSize(A->getType());
|
|
|
|
if (StoreSize != DL.getTypeStoreSize(B->getType()) || StoreSize > 128)
|
2009-10-28 09:12:16 +08:00
|
|
|
return false;
|
|
|
|
|
2012-01-27 09:46:00 +08:00
|
|
|
Type *IntTy = IntegerType::get(A->getContext(), StoreSize*8);
|
|
|
|
|
|
|
|
// Try constant folding a bitcast of both instructions to an integer. If we
|
|
|
|
// get two identical ConstantInt's, then we are good to share them. We use
|
|
|
|
// the constant folding APIs to do this so that we get the benefit of
|
2012-10-09 00:38:25 +08:00
|
|
|
// DataLayout.
|
2012-01-27 09:46:00 +08:00
|
|
|
if (isa<PointerType>(A->getType()))
|
2016-01-21 14:31:08 +08:00
|
|
|
A = ConstantFoldCastOperand(Instruction::PtrToInt,
|
|
|
|
const_cast<Constant *>(A), IntTy, DL);
|
2012-01-27 09:46:00 +08:00
|
|
|
else if (A->getType() != IntTy)
|
2016-01-21 14:31:08 +08:00
|
|
|
A = ConstantFoldCastOperand(Instruction::BitCast, const_cast<Constant *>(A),
|
|
|
|
IntTy, DL);
|
2012-01-27 09:46:00 +08:00
|
|
|
if (isa<PointerType>(B->getType()))
|
2016-01-21 14:31:08 +08:00
|
|
|
B = ConstantFoldCastOperand(Instruction::PtrToInt,
|
|
|
|
const_cast<Constant *>(B), IntTy, DL);
|
2012-01-27 09:46:00 +08:00
|
|
|
else if (B->getType() != IntTy)
|
2016-01-21 14:31:08 +08:00
|
|
|
B = ConstantFoldCastOperand(Instruction::BitCast, const_cast<Constant *>(B),
|
|
|
|
IntTy, DL);
|
2012-06-20 07:37:57 +08:00
|
|
|
|
2012-01-27 09:46:00 +08:00
|
|
|
return A == B;
|
2009-10-28 09:12:16 +08:00
|
|
|
}
|
|
|
|
|
2015-06-13 23:32:45 +08:00
|
|
|
/// Create a new entry in the constant pool or return an existing one.
|
|
|
|
/// User must specify the log2 of the minimum required alignment for the object.
|
2014-06-25 20:40:56 +08:00
|
|
|
unsigned MachineConstantPool::getConstantPoolIndex(const Constant *C,
|
2020-05-13 00:43:24 +08:00
|
|
|
Align Alignment) {
|
2006-02-09 12:46:04 +08:00
|
|
|
if (Alignment > PoolAlignment) PoolAlignment = Alignment;
|
2009-10-28 09:12:16 +08:00
|
|
|
|
2006-02-09 12:46:04 +08:00
|
|
|
// Check to see if we already have this constant.
|
|
|
|
//
|
|
|
|
// FIXME, this could be made much more efficient for large constant pools.
|
|
|
|
for (unsigned i = 0, e = Constants.size(); i != e; ++i)
|
2009-10-28 09:12:16 +08:00
|
|
|
if (!Constants[i].isMachineConstantPoolEntry() &&
|
2015-07-08 02:20:57 +08:00
|
|
|
CanShareConstantPoolEntry(Constants[i].Val.ConstVal, C, DL)) {
|
2020-05-13 00:43:24 +08:00
|
|
|
if (Constants[i].getAlign() < Alignment)
|
2009-10-28 09:12:16 +08:00
|
|
|
Constants[i].Alignment = Alignment;
|
2006-02-09 12:46:04 +08:00
|
|
|
return i;
|
2009-10-28 09:12:16 +08:00
|
|
|
}
|
2012-06-20 07:37:57 +08:00
|
|
|
|
2009-03-13 15:51:59 +08:00
|
|
|
Constants.push_back(MachineConstantPoolEntry(C, Alignment));
|
2006-02-09 12:46:04 +08:00
|
|
|
return Constants.size()-1;
|
|
|
|
}
|
|
|
|
|
2006-09-13 05:00:35 +08:00
|
|
|
unsigned MachineConstantPool::getConstantPoolIndex(MachineConstantPoolValue *V,
|
2020-05-13 00:43:24 +08:00
|
|
|
Align Alignment) {
|
2006-09-13 05:00:35 +08:00
|
|
|
if (Alignment > PoolAlignment) PoolAlignment = Alignment;
|
2012-06-20 07:37:57 +08:00
|
|
|
|
2006-09-13 05:00:35 +08:00
|
|
|
// Check to see if we already have this constant.
|
|
|
|
//
|
|
|
|
// FIXME, this could be made much more efficient for large constant pools.
|
|
|
|
int Idx = V->getExistingMachineCPValue(this, Alignment);
|
2011-02-22 16:54:30 +08:00
|
|
|
if (Idx != -1) {
|
|
|
|
MachineCPVsSharingEntries.insert(V);
|
2006-09-13 05:00:35 +08:00
|
|
|
return (unsigned)Idx;
|
2011-02-22 16:54:30 +08:00
|
|
|
}
|
2009-03-13 15:51:59 +08:00
|
|
|
|
|
|
|
Constants.push_back(MachineConstantPoolEntry(V, Alignment));
|
2006-09-13 05:00:35 +08:00
|
|
|
return Constants.size()-1;
|
|
|
|
}
|
|
|
|
|
2008-08-24 06:53:13 +08:00
|
|
|
void MachineConstantPool::print(raw_ostream &OS) const {
|
2009-11-01 04:19:03 +08:00
|
|
|
if (Constants.empty()) return;
|
|
|
|
|
|
|
|
OS << "Constant Pool:\n";
|
2006-02-01 06:23:14 +08:00
|
|
|
for (unsigned i = 0, e = Constants.size(); i != e; ++i) {
|
2009-11-01 04:19:03 +08:00
|
|
|
OS << " cp#" << i << ": ";
|
2006-09-13 05:00:35 +08:00
|
|
|
if (Constants[i].isMachineConstantPoolEntry())
|
|
|
|
Constants[i].Val.MachineCPVal->print(OS);
|
|
|
|
else
|
2014-01-09 10:29:41 +08:00
|
|
|
Constants[i].Val.ConstVal->printAsOperand(OS, /*PrintType=*/false);
|
2020-05-13 00:43:24 +08:00
|
|
|
OS << ", align=" << Constants[i].getAlign().value();
|
2006-02-01 06:23:14 +08:00
|
|
|
OS << "\n";
|
|
|
|
}
|
2003-01-13 08:23:03 +08:00
|
|
|
}
|
|
|
|
|
2017-10-15 22:32:27 +08:00
|
|
|
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
|
2016-01-30 04:50:44 +08:00
|
|
|
LLVM_DUMP_METHOD void MachineConstantPool::dump() const { print(dbgs()); }
|
2012-09-07 03:06:06 +08:00
|
|
|
#endif
|