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llvm-project/llvm/test/CodeGen/Thumb2/float-intrinsics-double.ll

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[ARM] Allow selecting VRINT[APMXZR] and VCVT[BT] instructions for FPv5 Currently, we only codegen the VRINT[APMXZR] and VCVT[BT] instructions when targeting ARMv8, but they are actually present on any target with FP-ARMv8. Note that FP-ARMv8 is called FPv5 when is is part of an M-profile core, but they have the same instructions so we model them both as FPARMv8 in the ARM backend. llvm-svn: 218763
2014-10-01 21:13:18 +08:00
; RUN: llc < %s -mtriple=thumbv7-none-eabi -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=NONE
; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4 | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=SP
; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=VFP -check-prefix=FP-ARMv8
[ARM] Replace fp-only-sp and d16 with fp64 and d32. Those two subtarget features were awkward because their semantics are reversed: each one indicates the _lack_ of support for something in the architecture, rather than the presence. As a consequence, you don't get the behavior you want if you combine two sets of feature bits. Each SubtargetFeature for an FP architecture version now comes in four versions, one for each combination of those options. So you can still say (for example) '+vfp2' in a feature string and it will mean what it's always meant, but there's a new string '+vfp2d16sp' meaning the version without those extra options. A lot of this change is just mechanically replacing positive checks for the old features with negative checks for the new ones. But one more interesting change is that I've rearranged getFPUFeatures() so that the main FPU feature is appended to the output list *before* rather than after the features derived from the Restriction field, so that -fp64 and -d32 can override defaults added by the main feature. Reviewers: dmgreen, samparker, SjoerdMeijer Subscribers: srhines, javed.absar, eraman, kristof.beyls, hiraditya, zzheng, Petar.Avramovic, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D60691 llvm-svn: 361845
2019-05-29 00:13:20 +08:00
; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 -mattr=-fp64 | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=SP
[ARM] Allow selecting VRINT[APMXZR] and VCVT[BT] instructions for FPv5 Currently, we only codegen the VRINT[APMXZR] and VCVT[BT] instructions when targeting ARMv8, but they are actually present on any target with FP-ARMv8. Note that FP-ARMv8 is called FPv5 when is is part of an M-profile core, but they have the same instructions so we model them both as FPARMv8 in the ARM backend. llvm-svn: 218763
2014-10-01 21:13:18 +08:00
; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=NEON -check-prefix=VFP4
; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a57 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=NEON -check-prefix=FP-ARMv8
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
declare double @llvm.sqrt.f64(double %Val)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
define double @sqrt_d(double %a) {
; CHECK-LABEL: sqrt_d:
; SOFT: {{(bl|b)}} sqrt
; HARD: vsqrt.f64 d0, d0
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
%1 = call double @llvm.sqrt.f64(double %a)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
ret double %1
}
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
declare double @llvm.powi.f64(double %Val, i32 %power)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
define double @powi_d(double %a, i32 %b) {
; CHECK-LABEL: powi_d:
; SOFT: {{(bl|b)}} __powidf2
ARM: match GCC's behaviour for builtins GCC changes the CC between the user-code and the builtins based on the value of `-target` rather than `-mfloat-abi`. When a HF target is used, the VFP variant of the AAPCS CC is used. Otherwise, the AAPCS variant is used. In all cases, the AEABI functions use the AAPCS CC. Adjust the calling convention based on the target. Resolves PR30543! llvm-svn: 291909
2017-01-14 00:25:33 +08:00
; HARD: b __powidf2
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
%1 = call double @llvm.powi.f64(double %a, i32 %b)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
ret double %1
}
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
declare double @llvm.sin.f64(double %Val)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
define double @sin_d(double %a) {
; CHECK-LABEL: sin_d:
; SOFT: {{(bl|b)}} sin
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
; HARD: b sin
%1 = call double @llvm.sin.f64(double %a)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
ret double %1
}
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
declare double @llvm.cos.f64(double %Val)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
define double @cos_d(double %a) {
; CHECK-LABEL: cos_d:
; SOFT: {{(bl|b)}} cos
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
; HARD: b cos
%1 = call double @llvm.cos.f64(double %a)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
ret double %1
}
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
declare double @llvm.pow.f64(double %Val, double %power)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
define double @pow_d(double %a, double %b) {
; CHECK-LABEL: pow_d:
; SOFT: {{(bl|b)}} pow
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
; HARD: b pow
%1 = call double @llvm.pow.f64(double %a, double %b)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
ret double %1
}
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
declare double @llvm.exp.f64(double %Val)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
define double @exp_d(double %a) {
; CHECK-LABEL: exp_d:
; SOFT: {{(bl|b)}} exp
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
; HARD: b exp
%1 = call double @llvm.exp.f64(double %a)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
ret double %1
}
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
declare double @llvm.exp2.f64(double %Val)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
define double @exp2_d(double %a) {
; CHECK-LABEL: exp2_d:
; SOFT: {{(bl|b)}} exp2
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
; HARD: b exp2
%1 = call double @llvm.exp2.f64(double %a)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
ret double %1
}
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
declare double @llvm.log.f64(double %Val)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
define double @log_d(double %a) {
; CHECK-LABEL: log_d:
; SOFT: {{(bl|b)}} log
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
; HARD: b log
%1 = call double @llvm.log.f64(double %a)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
ret double %1
}
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
declare double @llvm.log10.f64(double %Val)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
define double @log10_d(double %a) {
; CHECK-LABEL: log10_d:
; SOFT: {{(bl|b)}} log10
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
; HARD: b log10
%1 = call double @llvm.log10.f64(double %a)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
ret double %1
}
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
declare double @llvm.log2.f64(double %Val)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
define double @log2_d(double %a) {
; CHECK-LABEL: log2_d:
; SOFT: {{(bl|b)}} log2
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
; HARD: b log2
%1 = call double @llvm.log2.f64(double %a)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
ret double %1
}
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
declare double @llvm.fma.f64(double %a, double %b, double %c)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
define double @fma_d(double %a, double %b, double %c) {
; CHECK-LABEL: fma_d:
; SOFT: {{(bl|b)}} fma
; HARD: vfma.f64
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
%1 = call double @llvm.fma.f64(double %a, double %b, double %c)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
ret double %1
}
; FIXME: the FPv4-SP version is less efficient than the no-FPU version
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
declare double @llvm.fabs.f64(double %Val)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
define double @abs_d(double %a) {
; CHECK-LABEL: abs_d:
; NONE: bic r1, r1, #-2147483648
LegalizeDAG: Fix and improve FCOPYSIGN/FABS legalization - Factor out code to query and modify the sign bit of a floatingpoint value as an integer. This also works if none of the targets integer types is big enough to hold all bits of the floatingpoint value. - Legalize FABS(x) as FCOPYSIGN(x, 0.0) if FCOPYSIGN is available, otherwise perform bit manipulation on the sign bit. The previous code used "x >u 0 ? x : -x" which is incorrect for x being -0.0! It also takes 34 instructions on ARM Cortex-M4. With this patch we only require 5: vldr d0, LCPI0_0 vmov r2, r3, d0 lsrs r2, r3, #31 bfi r1, r2, #31, #1 bx lr (This could be further improved if the compiler would recognize that r2, r3 is zero). - Only lower FCOPYSIGN(x, y) = sign(x) ? -FABS(x) : FABS(x) if FABS is available otherwise perform bit manipulation on the sign bit. - Perform the sign(x) test by masking out the sign bit and comparing with 0 rather than shifting the sign bit to the highest position and testing for "<s 0". For x86 copysignl (on 80bit values) this gets us: testl $32768, %eax rather than: shlq $48, %rax sets %al testb %al, %al Differential Revision: http://reviews.llvm.org/D11172 llvm-svn: 252839
2015-11-12 09:02:47 +08:00
; SP: vldr d1, .LCPI{{.*}}
; SP: vmov r0, r1, d0
; SP: vmov r2, r3, d1
; SP: lsrs r2, r3, #31
; SP: bfi r1, r2, #31, #1
; SP: vmov d0, r0, r1
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
; DP: vabs.f64 d0, d0
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
%1 = call double @llvm.fabs.f64(double %a)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
ret double %1
}
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
declare double @llvm.copysign.f64(double %Mag, double %Sgn)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
define double @copysign_d(double %a, double %b) {
; CHECK-LABEL: copysign_d:
; SOFT: lsrs [[REG:r[0-9]+]], r3, #31
; SOFT: bfi r1, [[REG]], #31, #1
[ARM] Add support for Cortex-M7, FPv5-SP and FPv5-DP (LLVM) The Cortex-M7 has 3 options for its FPU: none, FPv5-SP-D16 and FPv5-DP-D16. FPv5 has the same instructions as FP-ARMv8, so it can be modelled using the same target feature, and all double-precision operations are already disabled by the fp-only-sp target features. llvm-svn: 218747
2014-10-01 17:02:17 +08:00
; VFP: lsrs [[REG:r[0-9]+]], r3, #31
; VFP: bfi r1, [[REG]], #31, #1
; NEON: vmov.i32 [[REG:d[0-9]+]], #0x80000000
; NEON: vshl.i64 [[REG]], [[REG]], #32
; NEON: vbsl [[REG]], d
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
%1 = call double @llvm.copysign.f64(double %a, double %b)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
ret double %1
}
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
declare double @llvm.floor.f64(double %Val)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
define double @floor_d(double %a) {
; CHECK-LABEL: floor_d:
; SOFT: {{(bl|b)}} floor
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
; VFP4: b floor
[ARM] Allow selecting VRINT[APMXZR] and VCVT[BT] instructions for FPv5 Currently, we only codegen the VRINT[APMXZR] and VCVT[BT] instructions when targeting ARMv8, but they are actually present on any target with FP-ARMv8. Note that FP-ARMv8 is called FPv5 when is is part of an M-profile core, but they have the same instructions so we model them both as FPARMv8 in the ARM backend. llvm-svn: 218763
2014-10-01 21:13:18 +08:00
; FP-ARMv8: vrintm.f64
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
%1 = call double @llvm.floor.f64(double %a)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
ret double %1
}
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
declare double @llvm.ceil.f64(double %Val)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
define double @ceil_d(double %a) {
; CHECK-LABEL: ceil_d:
; SOFT: {{(bl|b)}} ceil
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
; VFP4: b ceil
[ARM] Allow selecting VRINT[APMXZR] and VCVT[BT] instructions for FPv5 Currently, we only codegen the VRINT[APMXZR] and VCVT[BT] instructions when targeting ARMv8, but they are actually present on any target with FP-ARMv8. Note that FP-ARMv8 is called FPv5 when is is part of an M-profile core, but they have the same instructions so we model them both as FPARMv8 in the ARM backend. llvm-svn: 218763
2014-10-01 21:13:18 +08:00
; FP-ARMv8: vrintp.f64
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
%1 = call double @llvm.ceil.f64(double %a)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
ret double %1
}
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
declare double @llvm.trunc.f64(double %Val)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
define double @trunc_d(double %a) {
; CHECK-LABEL: trunc_d:
; SOFT: {{(bl|b)}} trunc
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
; FFP4: b trunc
[ARM] Allow selecting VRINT[APMXZR] and VCVT[BT] instructions for FPv5 Currently, we only codegen the VRINT[APMXZR] and VCVT[BT] instructions when targeting ARMv8, but they are actually present on any target with FP-ARMv8. Note that FP-ARMv8 is called FPv5 when is is part of an M-profile core, but they have the same instructions so we model them both as FPARMv8 in the ARM backend. llvm-svn: 218763
2014-10-01 21:13:18 +08:00
; FP-ARMv8: vrintz.f64
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
%1 = call double @llvm.trunc.f64(double %a)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
ret double %1
}
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
declare double @llvm.rint.f64(double %Val)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
define double @rint_d(double %a) {
; CHECK-LABEL: rint_d:
; SOFT: {{(bl|b)}} rint
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
; VFP4: b rint
[ARM] Allow selecting VRINT[APMXZR] and VCVT[BT] instructions for FPv5 Currently, we only codegen the VRINT[APMXZR] and VCVT[BT] instructions when targeting ARMv8, but they are actually present on any target with FP-ARMv8. Note that FP-ARMv8 is called FPv5 when is is part of an M-profile core, but they have the same instructions so we model them both as FPARMv8 in the ARM backend. llvm-svn: 218763
2014-10-01 21:13:18 +08:00
; FP-ARMv8: vrintx.f64
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
%1 = call double @llvm.rint.f64(double %a)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
ret double %1
}
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
declare double @llvm.nearbyint.f64(double %Val)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
define double @nearbyint_d(double %a) {
; CHECK-LABEL: nearbyint_d:
; SOFT: {{(bl|b)}} nearbyint
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
; VFP4: b nearbyint
[ARM] Allow selecting VRINT[APMXZR] and VCVT[BT] instructions for FPv5 Currently, we only codegen the VRINT[APMXZR] and VCVT[BT] instructions when targeting ARMv8, but they are actually present on any target with FP-ARMv8. Note that FP-ARMv8 is called FPv5 when is is part of an M-profile core, but they have the same instructions so we model them both as FPARMv8 in the ARM backend. llvm-svn: 218763
2014-10-01 21:13:18 +08:00
; FP-ARMv8: vrintr.f64
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
%1 = call double @llvm.nearbyint.f64(double %a)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
ret double %1
}
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
declare double @llvm.round.f64(double %Val)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
define double @round_d(double %a) {
; CHECK-LABEL: round_d:
; SOFT: {{(bl|b)}} round
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
; VFP4: b round
[ARM] Allow selecting VRINT[APMXZR] and VCVT[BT] instructions for FPv5 Currently, we only codegen the VRINT[APMXZR] and VCVT[BT] instructions when targeting ARMv8, but they are actually present on any target with FP-ARMv8. Note that FP-ARMv8 is called FPv5 when is is part of an M-profile core, but they have the same instructions so we model them both as FPARMv8 in the ARM backend. llvm-svn: 218763
2014-10-01 21:13:18 +08:00
; FP-ARMv8: vrinta.f64
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
%1 = call double @llvm.round.f64(double %a)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
ret double %1
}
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
declare double @llvm.fmuladd.f64(double %a, double %b, double %c)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
define double @fmuladd_d(double %a, double %b, double %c) {
; CHECK-LABEL: fmuladd_d:
; SOFT: bl __aeabi_dmul
; SOFT: bl __aeabi_dadd
[ARM] Allow selecting VRINT[APMXZR] and VCVT[BT] instructions for FPv5 Currently, we only codegen the VRINT[APMXZR] and VCVT[BT] instructions when targeting ARMv8, but they are actually present on any target with FP-ARMv8. Note that FP-ARMv8 is called FPv5 when is is part of an M-profile core, but they have the same instructions so we model them both as FPARMv8 in the ARM backend. llvm-svn: 218763
2014-10-01 21:13:18 +08:00
; VFP4: vmul.f64
; VFP4: vadd.f64
; FP-ARMv8: vmla.f64
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
%1 = call double @llvm.fmuladd.f64(double %a, double %b, double %c)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
ret double %1
}
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
declare i16 @llvm.convert.to.fp16.f64(double %a)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
define i16 @d_to_h(double %a) {
; CHECK-LABEL: d_to_h:
; SOFT: bl __aeabi_d2h
[ARM] Allow selecting VRINT[APMXZR] and VCVT[BT] instructions for FPv5 Currently, we only codegen the VRINT[APMXZR] and VCVT[BT] instructions when targeting ARMv8, but they are actually present on any target with FP-ARMv8. Note that FP-ARMv8 is called FPv5 when is is part of an M-profile core, but they have the same instructions so we model them both as FPARMv8 in the ARM backend. llvm-svn: 218763
2014-10-01 21:13:18 +08:00
; VFP4: bl __aeabi_d2h
; FP-ARMv8: vcvt{{[bt]}}.f16.f64
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
%1 = call i16 @llvm.convert.to.fp16.f64(double %a)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
ret i16 %1
}
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
declare double @llvm.convert.from.fp16.f64(i16 %a)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
define double @h_to_d(i16 %a) {
; CHECK-LABEL: h_to_d:
[ARM] Use correct half-precision functions in EABI mode The ARM RTABI defines the half- to single-precision float conversion functions with an __aeabi prefix, but libgcc only has them with a __gnu prefix. Therefore we need to emit the __aeabi version when compiling with an eabi or eabihf triple, and the __gnu version with a gnueabi or gnueabihf triple. llvm-svn: 249565
2015-10-08 00:58:49 +08:00
; NONE: bl __aeabi_h2f
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
; NONE: bl __aeabi_f2d
[ARM] Allow selecting VRINT[APMXZR] and VCVT[BT] instructions for FPv5 Currently, we only codegen the VRINT[APMXZR] and VCVT[BT] instructions when targeting ARMv8, but they are actually present on any target with FP-ARMv8. Note that FP-ARMv8 is called FPv5 when is is part of an M-profile core, but they have the same instructions so we model them both as FPARMv8 in the ARM backend. llvm-svn: 218763
2014-10-01 21:13:18 +08:00
; SP: vcvt{{[bt]}}.f32.f16
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
; SP: bl __aeabi_f2d
[ARM] Allow selecting VRINT[APMXZR] and VCVT[BT] instructions for FPv5 Currently, we only codegen the VRINT[APMXZR] and VCVT[BT] instructions when targeting ARMv8, but they are actually present on any target with FP-ARMv8. Note that FP-ARMv8 is called FPv5 when is is part of an M-profile core, but they have the same instructions so we model them both as FPARMv8 in the ARM backend. llvm-svn: 218763
2014-10-01 21:13:18 +08:00
; VFPv4: vcvt{{[bt]}}.f32.f16
; VFPv4: vcvt.f64.f32
; FP-ARMv8: vcvt{{[bt]}}.f64.f16
Revert "CodeGen: ensure that libcalls are always AAPCS CC" This reverts SVN r280683. Revert until I figure out why this is breaking lli tests. llvm-svn: 280778
2016-09-07 11:17:19 +08:00
%1 = call double @llvm.convert.from.fp16.f64(i16 %a)
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
ret double %1
}