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llvm-project/llvm/test/CodeGen/X86/2006-11-17-IllegalMove.ll

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[X86] Regenerate illegal move test Recommitting after fixing case-sensitive issue in the RUN command llvm-svn: 321868
2018-01-05 22:24:03 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
Remove llvm-upgrade and update tests. llvm-svn: 47432
2008-02-21 15:42:26 +08:00
add nounwind llvm-svn: 75407
2009-07-12 08:46:16 +08:00
define void @handle_vector_size_attribute() nounwind {
[X86] Regenerate illegal move test Recommitting after fixing case-sensitive issue in the RUN command llvm-svn: 321868
2018-01-05 22:24:03 +08:00
; CHECK-LABEL: handle_vector_size_attribute:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl 0, %eax
; CHECK-NEXT: decl %eax
Generalize MergeBlockIntoPredecessor. Replace uses of MergeBasicBlockIntoOnlyPred. Summary: Two utils methods have essentially the same functionality. This is an attempt to merge them into one. 1. lib/Transforms/Utils/Local.cpp : MergeBasicBlockIntoOnlyPred 2. lib/Transforms/Utils/BasicBlockUtils.cpp : MergeBlockIntoPredecessor Prior to the patch: 1. MergeBasicBlockIntoOnlyPred Updates either DomTree or DeferredDominance Moves all instructions from Pred to BB, deletes Pred Asserts BB has single predecessor If address was taken, replace the block address with constant 1 (?) 2. MergeBlockIntoPredecessor Updates DomTree, LoopInfo and MemoryDependenceResults Moves all instruction from BB to Pred, deletes BB Returns if doesn't have a single predecessor Returns if BB's address was taken After the patch: Method 2. MergeBlockIntoPredecessor is attempting to become the new default: Updates DomTree or DeferredDominance, and LoopInfo and MemoryDependenceResults Moves all instruction from BB to Pred, deletes BB Returns if doesn't have a single predecessor Returns if BB's address was taken Uses of MergeBasicBlockIntoOnlyPred that need to be replaced: 1. lib/Transforms/Scalar/LoopSimplifyCFG.cpp Updated in this patch. No challenges. 2. lib/CodeGen/CodeGenPrepare.cpp Updated in this patch. i. eliminateFallThrough is straightforward, but I added using a temporary array to avoid the iterator invalidation. ii. eliminateMostlyEmptyBlock(s) methods also now use a temporary array for blocks Some interesting aspects: - Since Pred is not deleted (BB is), the entry block does not need updating. - The entry block was being updated with the deleted block in eliminateMostlyEmptyBlock. Added assert to make obvious that BB=SinglePred. - isMergingEmptyBlockProfitable assumes BB is the one to be deleted. - eliminateMostlyEmptyBlock(BB) does not delete BB on one path, it deletes its unique predecessor instead. - adding some test owner as subscribers for the interesting tests modified: test/CodeGen/X86/avx-cmp.ll test/CodeGen/AMDGPU/nested-loop-conditions.ll test/CodeGen/AMDGPU/si-annotate-cf.ll test/CodeGen/X86/hoist-spill.ll test/CodeGen/X86/2006-11-17-IllegalMove.ll 3. lib/Transforms/Scalar/JumpThreading.cpp Not covered in this patch. It is the only use case using the DeferredDominance. I would defer to Brian Rzycki to make this replacement. Reviewers: chandlerc, spatel, davide, brzycki, bkramer, javed.absar Subscribers: qcolombet, sanjoy, nemanjai, nhaehnle, jlebar, tpr, kbarton, RKSimon, wmi, arsenm, llvm-commits Differential Revision: https://reviews.llvm.org/D48202 llvm-svn: 335183
2018-06-21 06:01:04 +08:00
; CHECK-NEXT: cmpl $1, %eax
; CHECK-NEXT: ja .LBB0_2
; CHECK-NEXT: # %bb.1: # %bb77
[X86] Regenerate illegal move test Recommitting after fixing case-sensitive issue in the RUN command llvm-svn: 321868
2018-01-05 22:24:03 +08:00
; CHECK-NEXT: movb 0, %al
; CHECK-NEXT: movzbl %al, %eax
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
; CHECK-NEXT: # kill: def $eax killed $eax def $ax
[X86] Make requested test changes from D50636 The tests were relying on X / X -> 1 and X % X -> 0 combines not happening in the DAG. llvm-svn: 340682
2018-08-25 22:16:03 +08:00
; CHECK-NEXT: divb 0
[X86] Regenerate illegal move test Recommitting after fixing case-sensitive issue in the RUN command llvm-svn: 321868
2018-01-05 22:24:03 +08:00
; CHECK-NEXT: movzbl %al, %eax
; CHECK-NEXT: cmpq %rax, %rax
; CHECK-NEXT: .LBB0_2: # %bb84
; CHECK-NEXT: retq
Add a x86-64 test case: movb %sil, %ah is illegal. llvm-svn: 31829
2006-11-18 04:41:55 +08:00
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp69 = load i32, i32* null ; <i32> [#uses=1]
Remove llvm-upgrade and update tests. llvm-svn: 47432
2008-02-21 15:42:26 +08:00
switch i32 %tmp69, label %bb84 [
i32 2, label %bb77
i32 1, label %bb77
Add a x86-64 test case: movb %sil, %ah is illegal. llvm-svn: 31829
2006-11-18 04:41:55 +08:00
]
bb77: ; preds = %entry, %entry
Remove llvm-upgrade and update tests. llvm-svn: 47432
2008-02-21 15:42:26 +08:00
%tmp99 = udiv i64 0, 0 ; <i64> [#uses=1]
[X86] Make requested test changes from D50636 The tests were relying on X / X -> 1 and X % X -> 0 combines not happening in the DAG. llvm-svn: 340682
2018-08-25 22:16:03 +08:00
%tmp = load volatile i8, i8* null ; <i8> [#uses=1]
Remove llvm-upgrade and update tests. llvm-svn: 47432
2008-02-21 15:42:26 +08:00
%tmp114 = icmp eq i64 0, 0 ; <i1> [#uses=1]
Eliminate the first have of the optimization which eliminates BRCOND when the condition is constant. This optimization shouldn't be necessary, because codegen shouldn't be able to find dead control paths that the IR-level optimizer can't find. And it's undesirable, because it encourages bugpoint to leave "br i1 false" branches in its output. And it wasn't updating the CFG. I updated all the tests I could, but some tests are too reduced and I wasn't able to meaningfully preserve them. llvm-svn: 106748
2010-06-24 23:04:11 +08:00
br label %cond_true115
Add a x86-64 test case: movb %sil, %ah is illegal. llvm-svn: 31829
2006-11-18 04:41:55 +08:00
bb84: ; preds = %entry
ret void
cond_true115: ; preds = %bb77
[X86] Make requested test changes from D50636 The tests were relying on X / X -> 1 and X % X -> 0 combines not happening in the DAG. llvm-svn: 340682
2018-08-25 22:16:03 +08:00
%tmp118 = load volatile i8, i8* null ; <i8> [#uses=1]
Eliminate the first have of the optimization which eliminates BRCOND when the condition is constant. This optimization shouldn't be necessary, because codegen shouldn't be able to find dead control paths that the IR-level optimizer can't find. And it's undesirable, because it encourages bugpoint to leave "br i1 false" branches in its output. And it wasn't updating the CFG. I updated all the tests I could, but some tests are too reduced and I wasn't able to meaningfully preserve them. llvm-svn: 106748
2010-06-24 23:04:11 +08:00
br label %cond_true120
Add a x86-64 test case: movb %sil, %ah is illegal. llvm-svn: 31829
2006-11-18 04:41:55 +08:00
cond_true120: ; preds = %cond_true115
Remove llvm-upgrade and update tests. llvm-svn: 47432
2008-02-21 15:42:26 +08:00
%tmp127 = udiv i8 %tmp, %tmp118 ; <i8> [#uses=1]
%tmp127.upgrd.1 = zext i8 %tmp127 to i64 ; <i64> [#uses=1]
Add a x86-64 test case: movb %sil, %ah is illegal. llvm-svn: 31829
2006-11-18 04:41:55 +08:00
br label %cond_next129
cond_next129: ; preds = %cond_true120, %cond_true115
Eliminate the first have of the optimization which eliminates BRCOND when the condition is constant. This optimization shouldn't be necessary, because codegen shouldn't be able to find dead control paths that the IR-level optimizer can't find. And it's undesirable, because it encourages bugpoint to leave "br i1 false" branches in its output. And it wasn't updating the CFG. I updated all the tests I could, but some tests are too reduced and I wasn't able to meaningfully preserve them. llvm-svn: 106748
2010-06-24 23:04:11 +08:00
%iftmp.30.0 = phi i64 [ %tmp127.upgrd.1, %cond_true120 ] ; <i64> [#uses=1]
Remove llvm-upgrade and update tests. llvm-svn: 47432
2008-02-21 15:42:26 +08:00
%tmp132 = icmp eq i64 %iftmp.30.0, %tmp99 ; <i1> [#uses=1]
br i1 %tmp132, label %cond_false148, label %cond_next136
Add a x86-64 test case: movb %sil, %ah is illegal. llvm-svn: 31829
2006-11-18 04:41:55 +08:00
cond_next136: ; preds = %cond_next129, %bb77
ret void
cond_false148: ; preds = %cond_next129
ret void
}