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llvm-project/llvm/test/CodeGen/Mips/inlineasmmemop.ll

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[mips] Handle 'M' and 'L' operand codes for memory operands Both operand codes now work the same way in case of register or memory operands. It print high-order or low-order word in a double-word register or memory location. llvm-svn: 324476
2018-02-07 20:36:33 +08:00
; RUN: llc -march=mips -relocation-model=pic < %s \
; RUN: | FileCheck --check-prefixes=CHECK,EB %s
; RUN: llc -march=mipsel -relocation-model=pic < %s \
; RUN: | FileCheck --check-prefixes=CHECK,EL %s
Re-apply 132758 and 132768 which were speculatively reverted in 132777. llvm-svn: 133494
2011-06-21 08:40:49 +08:00
Mips specific inline asm operand modifier 'D' Modifier 'D' is to use the second word of a double integer. We had previously implemented the pure register varient of the modifier and this patch implements the memory reference. #include "stdio.h" int b[8] = {0,1,2,3,4,5,6,7}; void main() { int i; // The first word. Notice, no 'D' {asm ( "lw %0,%1;" : "=r" (i) : "m" (*(b+4)) );} printf("%d\n",i); // The second word {asm ( "lw %0,%D1;" : "=r" (i) : "m" (*(b+4)) );} printf("%d\n",i); } llvm-svn: 179135
2013-04-10 07:19:50 +08:00
; Simple memory
Re-apply 132758 and 132768 which were speculatively reverted in 132777. llvm-svn: 133494
2011-06-21 08:40:49 +08:00
@g1 = external global i32
define i32 @f1(i32 %x) nounwind {
entry:
[mips] Set GCC-compatible MIPS asssembler options before inline asm blocks. Summary: When generating MIPS assembly, LLVM always overrides the default assembler options by emitting the '.set noreorder', '.set nomacro' and '.set noat' directives, while GCC uses the default options if an assembly-level function contains inline assembly code. This becomes a problem when the code generated by LLVM is interleaved with inline assembly which assumes GCC-like assembler options (from Linux, for example). This patch fixes these conflicts by setting the appropriate assembler options at the beginning of an inline asm block and popping them at the end. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6637 llvm-svn: 224425
2014-12-17 18:56:16 +08:00
; CHECK-LABEL: f1:
Re-apply 132758 and 132768 which were speculatively reverted in 132777. llvm-svn: 133494
2011-06-21 08:40:49 +08:00
; CHECK: #APP
[mips] Support 16-bit offsets for 'm' inline assembly memory constraint. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8435 llvm-svn: 233086
2015-03-24 23:19:14 +08:00
; CHECK: sw $4, [[OFFSET:[0-9]+]]($sp)
Re-apply 132758 and 132768 which were speculatively reverted in 132777. llvm-svn: 133494
2011-06-21 08:40:49 +08:00
; CHECK: #NO_APP
[mips] Support 16-bit offsets for 'm' inline assembly memory constraint. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8435 llvm-svn: 233086
2015-03-24 23:19:14 +08:00
; CHECK: lw $[[T1:[0-9]+]], %got(g1)
Re-apply 132758 and 132768 which were speculatively reverted in 132777. llvm-svn: 133494
2011-06-21 08:40:49 +08:00
; CHECK: #APP
[mips] Support 16-bit offsets for 'm' inline assembly memory constraint. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8435 llvm-svn: 233086
2015-03-24 23:19:14 +08:00
; CHECK: lw $[[T3:[0-9]+]], [[OFFSET]]($sp)
Re-apply 132758 and 132768 which were speculatively reverted in 132777. llvm-svn: 133494
2011-06-21 08:40:49 +08:00
; CHECK: #NO_APP
; CHECK: sw $[[T3]], 0($[[T1]])
%l1 = alloca i32, align 4
call void asm "sw $1, $0", "=*m,r"(i32* %l1, i32 %x) nounwind
%0 = call i32 asm "lw $0, $1", "=r,*m"(i32* %l1) nounwind
store i32 %0, i32* @g1, align 4
ret i32 %0
}
[mips] Set GCC-compatible MIPS asssembler options before inline asm blocks. Summary: When generating MIPS assembly, LLVM always overrides the default assembler options by emitting the '.set noreorder', '.set nomacro' and '.set noat' directives, while GCC uses the default options if an assembly-level function contains inline assembly code. This becomes a problem when the code generated by LLVM is interleaved with inline assembly which assumes GCC-like assembler options (from Linux, for example). This patch fixes these conflicts by setting the appropriate assembler options at the beginning of an inline asm block and popping them at the end. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6637 llvm-svn: 224425
2014-12-17 18:56:16 +08:00
; CHECK-LABEL: main:
[mips] Clean up the CodeGen/Mips/inlineasmmemop.ll test. NFC. Summary: Improve comments and remove a redundant attribute list. There are no functional changes (to the CHECK's or to the code). Part of these changes were suggested in http://reviews.llvm.org/D6637. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6705 llvm-svn: 224517
2014-12-18 21:03:51 +08:00
; "D": Second word of a double word. This works for any memory element
Mips specific inline asm memory operand modifier test case These changes are based on commit responses for r179135. llvm-svn: 179225
2013-04-11 06:02:32 +08:00
; double or single.
Mips specific inline asm operand modifier 'D' Modifier 'D' is to use the second word of a double integer. We had previously implemented the pure register varient of the modifier and this patch implements the memory reference. #include "stdio.h" int b[8] = {0,1,2,3,4,5,6,7}; void main() { int i; // The first word. Notice, no 'D' {asm ( "lw %0,%1;" : "=r" (i) : "m" (*(b+4)) );} printf("%d\n",i); // The second word {asm ( "lw %0,%D1;" : "=r" (i) : "m" (*(b+4)) );} printf("%d\n",i); } llvm-svn: 179135
2013-04-10 07:19:50 +08:00
; CHECK: #APP
[mips][ias] Remove spurious ';' from inline assembly test. IAS will not emit it. NFC at the moment but will prevent a test failure once IAS is enabled. llvm-svn: 253210
2015-11-16 22:19:32 +08:00
; CHECK: lw ${{[0-9]+}}, 16(${{[0-9]+}})
[mips] Set GCC-compatible MIPS asssembler options before inline asm blocks. Summary: When generating MIPS assembly, LLVM always overrides the default assembler options by emitting the '.set noreorder', '.set nomacro' and '.set noat' directives, while GCC uses the default options if an assembly-level function contains inline assembly code. This becomes a problem when the code generated by LLVM is interleaved with inline assembly which assumes GCC-like assembler options (from Linux, for example). This patch fixes these conflicts by setting the appropriate assembler options at the beginning of an inline asm block and popping them at the end. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6637 llvm-svn: 224425
2014-12-17 18:56:16 +08:00
; CHECK: #NO_APP
Mips specific inline asm operand modifier 'D' Modifier 'D' is to use the second word of a double integer. We had previously implemented the pure register varient of the modifier and this patch implements the memory reference. #include "stdio.h" int b[8] = {0,1,2,3,4,5,6,7}; void main() { int i; // The first word. Notice, no 'D' {asm ( "lw %0,%1;" : "=r" (i) : "m" (*(b+4)) );} printf("%d\n",i); // The second word {asm ( "lw %0,%D1;" : "=r" (i) : "m" (*(b+4)) );} printf("%d\n",i); } llvm-svn: 179135
2013-04-10 07:19:50 +08:00
[mips] Clean up the CodeGen/Mips/inlineasmmemop.ll test. NFC. Summary: Improve comments and remove a redundant attribute list. There are no functional changes (to the CHECK's or to the code). Part of these changes were suggested in http://reviews.llvm.org/D6637. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6705 llvm-svn: 224517
2014-12-18 21:03:51 +08:00
; No "D": First word of a double word. This works for any memory element
Mips specific inline asm memory operand modifier test case These changes are based on commit responses for r179135. llvm-svn: 179225
2013-04-11 06:02:32 +08:00
; double or single.
; CHECK: #APP
[mips][ias] Remove spurious ';' from inline assembly test. IAS will not emit it. NFC at the moment but will prevent a test failure once IAS is enabled. llvm-svn: 253210
2015-11-16 22:19:32 +08:00
; CHECK: lw ${{[0-9]+}}, 12(${{[0-9]+}})
[mips] Set GCC-compatible MIPS asssembler options before inline asm blocks. Summary: When generating MIPS assembly, LLVM always overrides the default assembler options by emitting the '.set noreorder', '.set nomacro' and '.set noat' directives, while GCC uses the default options if an assembly-level function contains inline assembly code. This becomes a problem when the code generated by LLVM is interleaved with inline assembly which assumes GCC-like assembler options (from Linux, for example). This patch fixes these conflicts by setting the appropriate assembler options at the beginning of an inline asm block and popping them at the end. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6637 llvm-svn: 224425
2014-12-17 18:56:16 +08:00
; CHECK: #NO_APP
Mips specific inline asm memory operand modifier test case These changes are based on commit responses for r179135. llvm-svn: 179225
2013-04-11 06:02:32 +08:00
[mips] Handle 'M' and 'L' operand codes for memory operands Both operand codes now work the same way in case of register or memory operands. It print high-order or low-order word in a double-word register or memory location. llvm-svn: 324476
2018-02-07 20:36:33 +08:00
; "M": High-order word of a double word.
; CHECK: #APP
; EB: lw ${{[0-9]+}}, 12(${{[0-9]+}})
; EL: lw ${{[0-9]+}}, 16(${{[0-9]+}})
; CHECK: #NO_APP
; "L": Low-order word of a double word.
; CHECK: #APP
; EB: lw ${{[0-9]+}}, 16(${{[0-9]+}})
; EL: lw ${{[0-9]+}}, 12(${{[0-9]+}})
; CHECK: #NO_APP
Mips specific inline asm operand modifier 'D' Modifier 'D' is to use the second word of a double integer. We had previously implemented the pure register varient of the modifier and this patch implements the memory reference. #include "stdio.h" int b[8] = {0,1,2,3,4,5,6,7}; void main() { int i; // The first word. Notice, no 'D' {asm ( "lw %0,%1;" : "=r" (i) : "m" (*(b+4)) );} printf("%d\n",i); // The second word {asm ( "lw %0,%D1;" : "=r" (i) : "m" (*(b+4)) );} printf("%d\n",i); } llvm-svn: 179135
2013-04-10 07:19:50 +08:00
@b = common global [20 x i32] zeroinitializer, align 4
Mips specific inline asm memory operand modifier test case These changes are based on commit responses for r179135. llvm-svn: 179225
2013-04-11 06:02:32 +08:00
define void @main() {
Mips specific inline asm operand modifier 'D' Modifier 'D' is to use the second word of a double integer. We had previously implemented the pure register varient of the modifier and this patch implements the memory reference. #include "stdio.h" int b[8] = {0,1,2,3,4,5,6,7}; void main() { int i; // The first word. Notice, no 'D' {asm ( "lw %0,%1;" : "=r" (i) : "m" (*(b+4)) );} printf("%d\n",i); // The second word {asm ( "lw %0,%D1;" : "=r" (i) : "m" (*(b+4)) );} printf("%d\n",i); } llvm-svn: 179135
2013-04-10 07:19:50 +08:00
entry:
[mips] Clean up the CodeGen/Mips/inlineasmmemop.ll test. NFC. Summary: Improve comments and remove a redundant attribute list. There are no functional changes (to the CHECK's or to the code). Part of these changes were suggested in http://reviews.llvm.org/D6637. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6705 llvm-svn: 224517
2014-12-18 21:03:51 +08:00
; Second word:
[mips][ias] Remove spurious ';' from inline assembly test. IAS will not emit it. NFC at the moment but will prevent a test failure once IAS is enabled. llvm-svn: 253210
2015-11-16 22:19:32 +08:00
tail call void asm sideeffect " lw $0, ${1:D}", "r,*m,~{$11}"(i32 undef, i32* getelementptr inbounds ([20 x i32], [20 x i32]* @b, i32 0, i32 3))
[mips] Clean up the CodeGen/Mips/inlineasmmemop.ll test. NFC. Summary: Improve comments and remove a redundant attribute list. There are no functional changes (to the CHECK's or to the code). Part of these changes were suggested in http://reviews.llvm.org/D6637. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6705 llvm-svn: 224517
2014-12-18 21:03:51 +08:00
; First word. Notice, no 'D':
[mips][ias] Remove spurious ';' from inline assembly test. IAS will not emit it. NFC at the moment but will prevent a test failure once IAS is enabled. llvm-svn: 253210
2015-11-16 22:19:32 +08:00
tail call void asm sideeffect " lw $0, ${1}", "r,*m,~{$11}"(i32 undef, i32* getelementptr inbounds ([20 x i32], [20 x i32]* @b, i32 0, i32 3))
[mips] Handle 'M' and 'L' operand codes for memory operands Both operand codes now work the same way in case of register or memory operands. It print high-order or low-order word in a double-word register or memory location. llvm-svn: 324476
2018-02-07 20:36:33 +08:00
; High-order part.
tail call void asm sideeffect " lw $0, ${1:M}", "r,*m,~{$11}"(i32 undef, i32* getelementptr inbounds ([20 x i32], [20 x i32]* @b, i32 0, i32 3))
; Low-order part.
tail call void asm sideeffect " lw $0, ${1:L}", "r,*m,~{$11}"(i32 undef, i32* getelementptr inbounds ([20 x i32], [20 x i32]* @b, i32 0, i32 3))
Mips specific inline asm operand modifier 'D' Modifier 'D' is to use the second word of a double integer. We had previously implemented the pure register varient of the modifier and this patch implements the memory reference. #include "stdio.h" int b[8] = {0,1,2,3,4,5,6,7}; void main() { int i; // The first word. Notice, no 'D' {asm ( "lw %0,%1;" : "=r" (i) : "m" (*(b+4)) );} printf("%d\n",i); // The second word {asm ( "lw %0,%D1;" : "=r" (i) : "m" (*(b+4)) );} printf("%d\n",i); } llvm-svn: 179135
2013-04-10 07:19:50 +08:00
ret void
}