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llvm-project/llvm/test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir

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MIR: Allow targets to serialize MachineFunctionInfo This has been a very painful missing feature that has made producing reduced testcases difficult. In particular the various registers determined for stack access during function lowering were necessary to avoid undefined register errors in a large percentage of cases. Implement a subset of the important fields that need to be preserved for AMDGPU. Most of the changes are to support targets parsing register fields and properly reporting errors. The biggest sort-of bug remaining is for fields that can be initialized from the IR section will be overwritten by a default initialized machineFunctionInfo section. Another remaining bug is the machineFunctionInfo section is still printed even if empty. llvm-svn: 356215
2019-03-15 06:54:43 +08:00
# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# CHECK: :8:27: incorrect register class for field
# CHECK: frameOffsetReg: '$vgpr0'
---
name: wrong_reg_class_frame_offset_reg
machineFunctionInfo:
frameOffsetReg: '$vgpr0'
body: |
bb.0:
S_ENDPGM
...