2012-05-04 05:52:53 +08:00
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//===----- HexagonPacketizer.cpp - vliw packetizer ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements a simple VLIW packetizer using DFA. The packetizer works on
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// machine basic blocks. For each instruction I in BB, the packetizer consults
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// the DFA to see if machine resources are available to execute I. If so, the
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// packetizer checks if I depends on any instruction J in the current packet.
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// If no dependency is found, I is added to current packet and machine resource
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// is marked as taken. If any dependency is found, a target API call is made to
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// prune the dependence.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/DFAPacketizer.h"
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2014-01-07 19:48:04 +08:00
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#include "Hexagon.h"
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#include "HexagonMachineFunctionInfo.h"
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#include "HexagonRegisterInfo.h"
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#include "HexagonSubtarget.h"
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#include "HexagonTargetMachine.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/LatencyPriorityQueue.h"
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2012-05-04 05:52:53 +08:00
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#include "llvm/CodeGen/MachineDominators.h"
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2014-01-07 19:48:04 +08:00
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunctionAnalysis.h"
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2012-05-04 05:52:53 +08:00
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#include "llvm/CodeGen/MachineFunctionPass.h"
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2014-01-07 19:48:04 +08:00
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2012-05-04 05:52:53 +08:00
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#include "llvm/CodeGen/MachineLoopInfo.h"
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2014-01-07 19:48:04 +08:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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2012-05-04 05:52:53 +08:00
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/CodeGen/ScheduleDAGInstrs.h"
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2013-03-02 01:37:13 +08:00
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#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
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2014-01-07 19:48:04 +08:00
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#include "llvm/CodeGen/SchedulerRegistry.h"
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2012-05-04 05:52:53 +08:00
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#include "llvm/MC/MCInstrItineraries.h"
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2013-03-02 01:37:13 +08:00
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#include "llvm/Support/CommandLine.h"
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2014-01-07 19:48:04 +08:00
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#include "llvm/Support/Compiler.h"
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2012-05-04 05:52:53 +08:00
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#include "llvm/Support/Debug.h"
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2014-01-07 19:48:04 +08:00
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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2012-05-04 05:52:53 +08:00
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#include <map>
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2013-05-02 23:39:30 +08:00
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#include <vector>
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2012-05-04 05:52:53 +08:00
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using namespace llvm;
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2014-04-22 10:41:26 +08:00
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#define DEBUG_TYPE "packets"
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2013-05-02 23:39:30 +08:00
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static cl::opt<bool> PacketizeVolatiles("hexagon-packetize-volatiles",
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cl::ZeroOrMore, cl::Hidden, cl::init(true),
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cl::desc("Allow non-solo packetization of volatile memory references"));
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namespace llvm {
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2015-06-16 03:05:35 +08:00
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FunctionPass *createHexagonPacketizer();
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2013-05-02 23:39:30 +08:00
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void initializeHexagonPacketizerPass(PassRegistry&);
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}
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2012-05-04 05:52:53 +08:00
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namespace {
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class HexagonPacketizer : public MachineFunctionPass {
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public:
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static char ID;
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2013-05-02 23:39:30 +08:00
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HexagonPacketizer() : MachineFunctionPass(ID) {
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initializeHexagonPacketizerPass(*PassRegistry::getPassRegistry());
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}
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2012-05-04 05:52:53 +08:00
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2014-04-29 15:58:16 +08:00
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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2012-05-04 05:52:53 +08:00
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AU.setPreservesCFG();
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AU.addRequired<MachineDominatorTree>();
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2013-05-02 23:39:30 +08:00
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AU.addRequired<MachineBranchProbabilityInfo>();
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2012-05-04 05:52:53 +08:00
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AU.addPreserved<MachineDominatorTree>();
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AU.addRequired<MachineLoopInfo>();
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AU.addPreserved<MachineLoopInfo>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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2014-04-29 15:58:16 +08:00
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const char *getPassName() const override {
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2012-05-04 05:52:53 +08:00
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return "Hexagon Packetizer";
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}
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2014-04-29 15:58:16 +08:00
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bool runOnMachineFunction(MachineFunction &Fn) override;
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2012-05-04 05:52:53 +08:00
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};
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char HexagonPacketizer::ID = 0;
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class HexagonPacketizerList : public VLIWPacketizerList {
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private:
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// Has the instruction been promoted to a dot-new instruction.
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bool PromotedToDotNew;
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// Has the instruction been glued to allocframe.
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bool GlueAllocframeStore;
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// Has the feeder instruction been glued to new value jump.
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bool GlueToNewValueJump;
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// Check if there is a dependence between some instruction already in this
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// packet and this instruction.
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bool Dependence;
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// Only check for dependence if there are resources available to
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// schedule this instruction.
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bool FoundSequentialDependence;
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2013-05-02 23:39:30 +08:00
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/// \brief A handle to the branch probability pass.
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const MachineBranchProbabilityInfo *MBPI;
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// Track MIs with ignored dependece.
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std::vector<MachineInstr*> IgnoreDepMIs;
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2012-05-04 05:52:53 +08:00
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public:
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// Ctor.
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HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
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2013-05-02 23:39:30 +08:00
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const MachineBranchProbabilityInfo *MBPI);
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2012-05-04 05:52:53 +08:00
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// initPacketizerState - initialize some internal flags.
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2014-04-29 15:58:16 +08:00
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void initPacketizerState() override;
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2012-05-04 05:52:53 +08:00
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// ignorePseudoInstruction - Ignore bundling of pseudo instructions.
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2014-04-29 15:58:16 +08:00
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bool ignorePseudoInstruction(MachineInstr *MI,
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MachineBasicBlock *MBB) override;
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2012-05-04 05:52:53 +08:00
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// isSoloInstruction - return true if instruction MI can not be packetized
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// with any other instruction, which means that MI itself is a packet.
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2014-04-29 15:58:16 +08:00
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bool isSoloInstruction(MachineInstr *MI) override;
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2012-05-04 05:52:53 +08:00
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// isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
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// together.
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2014-04-29 15:58:16 +08:00
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bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override;
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2012-05-04 05:52:53 +08:00
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// isLegalToPruneDependencies - Is it legal to prune dependece between SUI
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// and SUJ.
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2014-04-29 15:58:16 +08:00
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bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override;
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2012-05-04 05:52:53 +08:00
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2014-04-29 15:58:16 +08:00
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MachineBasicBlock::iterator addToPacket(MachineInstr *MI) override;
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2012-05-04 05:52:53 +08:00
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private:
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bool IsCallDependent(MachineInstr* MI, SDep::Kind DepType, unsigned DepReg);
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bool PromoteToDotNew(MachineInstr* MI, SDep::Kind DepType,
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2013-05-02 23:39:30 +08:00
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MachineBasicBlock::iterator &MII,
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const TargetRegisterClass* RC);
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2014-10-05 00:55:56 +08:00
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bool CanPromoteToDotNew(MachineInstr *MI, SUnit *PacketSU, unsigned DepReg,
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const std::map<MachineInstr *, SUnit *> &MIToSUnit,
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2013-05-02 23:39:30 +08:00
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MachineBasicBlock::iterator &MII,
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2014-10-05 00:55:56 +08:00
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const TargetRegisterClass *RC);
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bool
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CanPromoteToNewValue(MachineInstr *MI, SUnit *PacketSU, unsigned DepReg,
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const std::map<MachineInstr *, SUnit *> &MIToSUnit,
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MachineBasicBlock::iterator &MII);
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bool CanPromoteToNewValueStore(
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MachineInstr *MI, MachineInstr *PacketMI, unsigned DepReg,
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const std::map<MachineInstr *, SUnit *> &MIToSUnit);
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bool DemoteToDotOld(MachineInstr *MI);
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bool ArePredicatesComplements(
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MachineInstr *MI1, MachineInstr *MI2,
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const std::map<MachineInstr *, SUnit *> &MIToSUnit);
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bool RestrictingDepExistInPacket(MachineInstr *, unsigned,
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const std::map<MachineInstr *, SUnit *> &);
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2012-05-04 05:52:53 +08:00
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bool isNewifiable(MachineInstr* MI);
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bool isCondInst(MachineInstr* MI);
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bool tryAllocateResourcesForConstExt(MachineInstr* MI);
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bool canReserveResourcesForConstExt(MachineInstr *MI);
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void reserveResourcesForConstExt(MachineInstr* MI);
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bool isNewValueInst(MachineInstr* MI);
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};
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2015-06-23 17:49:53 +08:00
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}
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2012-05-04 05:52:53 +08:00
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2013-05-02 23:39:30 +08:00
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INITIALIZE_PASS_BEGIN(HexagonPacketizer, "packets", "Hexagon Packetizer",
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false, false)
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INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
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INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
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INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
|
[PM/AA] Rebuild LLVM's alias analysis infrastructure in a way compatible
with the new pass manager, and no longer relying on analysis groups.
This builds essentially a ground-up new AA infrastructure stack for
LLVM. The core ideas are the same that are used throughout the new pass
manager: type erased polymorphism and direct composition. The design is
as follows:
- FunctionAAResults is a type-erasing alias analysis results aggregation
interface to walk a single query across a range of results from
different alias analyses. Currently this is function-specific as we
always assume that aliasing queries are *within* a function.
- AAResultBase is a CRTP utility providing stub implementations of
various parts of the alias analysis result concept, notably in several
cases in terms of other more general parts of the interface. This can
be used to implement only a narrow part of the interface rather than
the entire interface. This isn't really ideal, this logic should be
hoisted into FunctionAAResults as currently it will cause
a significant amount of redundant work, but it faithfully models the
behavior of the prior infrastructure.
- All the alias analysis passes are ported to be wrapper passes for the
legacy PM and new-style analysis passes for the new PM with a shared
result object. In some cases (most notably CFL), this is an extremely
naive approach that we should revisit when we can specialize for the
new pass manager.
- BasicAA has been restructured to reflect that it is much more
fundamentally a function analysis because it uses dominator trees and
loop info that need to be constructed for each function.
All of the references to getting alias analysis results have been
updated to use the new aggregation interface. All the preservation and
other pass management code has been updated accordingly.
The way the FunctionAAResultsWrapperPass works is to detect the
available alias analyses when run, and add them to the results object.
This means that we should be able to continue to respect when various
passes are added to the pipeline, for example adding CFL or adding TBAA
passes should just cause their results to be available and to get folded
into this. The exception to this rule is BasicAA which really needs to
be a function pass due to using dominator trees and loop info. As
a consequence, the FunctionAAResultsWrapperPass directly depends on
BasicAA and always includes it in the aggregation.
This has significant implications for preserving analyses. Generally,
most passes shouldn't bother preserving FunctionAAResultsWrapperPass
because rebuilding the results just updates the set of known AA passes.
The exception to this rule are LoopPass instances which need to preserve
all the function analyses that the loop pass manager will end up
needing. This means preserving both BasicAAWrapperPass and the
aggregating FunctionAAResultsWrapperPass.
Now, when preserving an alias analysis, you do so by directly preserving
that analysis. This is only necessary for non-immutable-pass-provided
alias analyses though, and there are only three of interest: BasicAA,
GlobalsAA (formerly GlobalsModRef), and SCEVAA. Usually BasicAA is
preserved when needed because it (like DominatorTree and LoopInfo) is
marked as a CFG-only pass. I've expanded GlobalsAA into the preserved
set everywhere we previously were preserving all of AliasAnalysis, and
I've added SCEVAA in the intersection of that with where we preserve
SCEV itself.
One significant challenge to all of this is that the CGSCC passes were
actually using the alias analysis implementations by taking advantage of
a pretty amazing set of loop holes in the old pass manager's analysis
management code which allowed analysis groups to slide through in many
cases. Moving away from analysis groups makes this problem much more
obvious. To fix it, I've leveraged the flexibility the design of the new
PM components provides to just directly construct the relevant alias
analyses for the relevant functions in the IPO passes that need them.
This is a bit hacky, but should go away with the new pass manager, and
is already in many ways cleaner than the prior state.
Another significant challenge is that various facilities of the old
alias analysis infrastructure just don't fit any more. The most
significant of these is the alias analysis 'counter' pass. That pass
relied on the ability to snoop on AA queries at different points in the
analysis group chain. Instead, I'm planning to build printing
functionality directly into the aggregation layer. I've not included
that in this patch merely to keep it smaller.
Note that all of this needs a nearly complete rewrite of the AA
documentation. I'm planning to do that, but I'd like to make sure the
new design settles, and to flesh out a bit more of what it looks like in
the new pass manager first.
Differential Revision: http://reviews.llvm.org/D12080
llvm-svn: 247167
2015-09-10 01:55:00 +08:00
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INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
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2013-05-02 23:39:30 +08:00
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INITIALIZE_PASS_END(HexagonPacketizer, "packets", "Hexagon Packetizer",
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false, false)
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2012-05-04 05:52:53 +08:00
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// HexagonPacketizerList Ctor.
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HexagonPacketizerList::HexagonPacketizerList(
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2014-08-21 04:57:26 +08:00
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MachineFunction &MF, MachineLoopInfo &MLI,
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const MachineBranchProbabilityInfo *MBPI)
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: VLIWPacketizerList(MF, MLI, true) {
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2013-05-02 23:39:30 +08:00
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this->MBPI = MBPI;
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2012-05-04 05:52:53 +08:00
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}
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bool HexagonPacketizer::runOnMachineFunction(MachineFunction &Fn) {
|
2014-08-05 10:39:49 +08:00
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const TargetInstrInfo *TII = Fn.getSubtarget().getInstrInfo();
|
2012-05-04 05:52:53 +08:00
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MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
|
2013-05-02 23:39:30 +08:00
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const MachineBranchProbabilityInfo *MBPI =
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&getAnalysis<MachineBranchProbabilityInfo>();
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2012-05-04 05:52:53 +08:00
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// Instantiate the packetizer.
|
2014-08-21 04:57:26 +08:00
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HexagonPacketizerList Packetizer(Fn, MLI, MBPI);
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2012-05-04 05:52:53 +08:00
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// DFA state table should not be empty.
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assert(Packetizer.getResourceTracker() && "Empty DFA table!");
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//
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// Loop over all basic blocks and remove KILL pseudo-instructions
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// These instructions confuse the dependence analysis. Consider:
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// D0 = ... (Insn 0)
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// R0 = KILL R0, D0 (Insn 1)
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// R0 = ... (Insn 2)
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// Here, Insn 1 will result in the dependence graph not emitting an output
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// dependence between Insn 0 and Insn 2. This can lead to incorrect
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// packetization
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//
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for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
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MBB != MBBe; ++MBB) {
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MachineBasicBlock::iterator End = MBB->end();
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MachineBasicBlock::iterator MI = MBB->begin();
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while (MI != End) {
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if (MI->isKill()) {
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MachineBasicBlock::iterator DeleteMI = MI;
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++MI;
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MBB->erase(DeleteMI);
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End = MBB->end();
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continue;
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}
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++MI;
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}
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}
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// Loop over all of the basic blocks.
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for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
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MBB != MBBe; ++MBB) {
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// Find scheduling regions and schedule / packetize each region.
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unsigned RemainingCount = MBB->size();
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for(MachineBasicBlock::iterator RegionEnd = MBB->end();
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RegionEnd != MBB->begin();) {
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// The next region starts above the previous region. Look backward in the
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// instruction stream until we find the nearest boundary.
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MachineBasicBlock::iterator I = RegionEnd;
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for(;I != MBB->begin(); --I, --RemainingCount) {
|
2014-03-02 20:27:27 +08:00
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if (TII->isSchedulingBoundary(std::prev(I), MBB, Fn))
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2012-05-04 05:52:53 +08:00
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break;
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}
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I = MBB->begin();
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// Skip empty scheduling regions.
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if (I == RegionEnd) {
|
2014-03-02 20:27:27 +08:00
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RegionEnd = std::prev(RegionEnd);
|
2012-05-04 05:52:53 +08:00
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--RemainingCount;
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continue;
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}
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// Skip regions with one instruction.
|
2014-03-02 20:27:27 +08:00
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|
if (I == std::prev(RegionEnd)) {
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|
|
|
RegionEnd = std::prev(RegionEnd);
|
2012-05-04 05:52:53 +08:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
Packetizer.PacketizeMIs(MBB, I, RegionEnd);
|
|
|
|
RegionEnd = I;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static bool IsIndirectCall(MachineInstr* MI) {
|
2015-01-17 01:05:27 +08:00
|
|
|
return MI->getOpcode() == Hexagon::J2_callr;
|
2012-05-04 05:52:53 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Reserve resources for constant extender. Trigure an assertion if
|
|
|
|
// reservation fail.
|
|
|
|
void HexagonPacketizerList::reserveResourcesForConstExt(MachineInstr* MI) {
|
|
|
|
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
|
2015-06-23 21:50:23 +08:00
|
|
|
MachineInstr *PseudoMI = MF.CreateMachineInstr(QII->get(Hexagon::A4_ext),
|
|
|
|
MI->getDebugLoc());
|
2012-05-04 05:52:53 +08:00
|
|
|
|
|
|
|
if (ResourceTracker->canReserveResources(PseudoMI)) {
|
|
|
|
ResourceTracker->reserveResources(PseudoMI);
|
|
|
|
MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
|
|
|
|
} else {
|
|
|
|
MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
|
|
|
|
llvm_unreachable("can not reserve resources for constant extender.");
|
|
|
|
}
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool HexagonPacketizerList::canReserveResourcesForConstExt(MachineInstr *MI) {
|
|
|
|
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
|
2013-03-02 01:37:13 +08:00
|
|
|
assert((QII->isExtended(MI) || QII->isConstExtended(MI)) &&
|
2012-05-04 05:52:53 +08:00
|
|
|
"Should only be called for constant extended instructions");
|
2015-06-23 21:50:23 +08:00
|
|
|
MachineInstr *PseudoMI = MF.CreateMachineInstr(QII->get(Hexagon::A4_ext),
|
|
|
|
MI->getDebugLoc());
|
2012-05-04 05:52:53 +08:00
|
|
|
bool CanReserve = ResourceTracker->canReserveResources(PseudoMI);
|
2015-06-23 21:50:23 +08:00
|
|
|
MF.DeleteMachineInstr(PseudoMI);
|
2012-05-04 05:52:53 +08:00
|
|
|
return CanReserve;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Allocate resources (i.e. 4 bytes) for constant extender. If succeed, return
|
|
|
|
// true, otherwise, return false.
|
|
|
|
bool HexagonPacketizerList::tryAllocateResourcesForConstExt(MachineInstr* MI) {
|
|
|
|
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
|
2015-06-23 21:50:23 +08:00
|
|
|
MachineInstr *PseudoMI = MF.CreateMachineInstr(QII->get(Hexagon::A4_ext),
|
|
|
|
MI->getDebugLoc());
|
2012-05-04 05:52:53 +08:00
|
|
|
|
|
|
|
if (ResourceTracker->canReserveResources(PseudoMI)) {
|
|
|
|
ResourceTracker->reserveResources(PseudoMI);
|
|
|
|
MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
|
|
|
|
return true;
|
|
|
|
} else {
|
|
|
|
MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
bool HexagonPacketizerList::IsCallDependent(MachineInstr* MI,
|
|
|
|
SDep::Kind DepType,
|
|
|
|
unsigned DepReg) {
|
|
|
|
|
|
|
|
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
|
2014-08-05 05:25:23 +08:00
|
|
|
const HexagonRegisterInfo *QRI =
|
2014-10-14 09:03:16 +08:00
|
|
|
(const HexagonRegisterInfo *)MF.getSubtarget().getRegisterInfo();
|
2012-05-04 05:52:53 +08:00
|
|
|
|
|
|
|
// Check for lr dependence
|
|
|
|
if (DepReg == QRI->getRARegister()) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (QII->isDeallocRet(MI)) {
|
|
|
|
if (DepReg == QRI->getFrameRegister() ||
|
|
|
|
DepReg == QRI->getStackRegister())
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Check if this is a predicate dependence
|
|
|
|
const TargetRegisterClass* RC = QRI->getMinimalPhysRegClass(DepReg);
|
|
|
|
if (RC == &Hexagon::PredRegsRegClass) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
//
|
|
|
|
// Lastly check for an operand used in an indirect call
|
|
|
|
// If we had an attribute for checking if an instruction is an indirect call,
|
|
|
|
// then we could have avoided this relatively brittle implementation of
|
|
|
|
// IsIndirectCall()
|
|
|
|
//
|
|
|
|
// Assumes that the first operand of the CALLr is the function address
|
|
|
|
//
|
|
|
|
if (IsIndirectCall(MI) && (DepType == SDep::Data)) {
|
|
|
|
MachineOperand MO = MI->getOperand(0);
|
|
|
|
if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool IsRegDependence(const SDep::Kind DepType) {
|
|
|
|
return (DepType == SDep::Data || DepType == SDep::Anti ||
|
|
|
|
DepType == SDep::Output);
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool IsDirectJump(MachineInstr* MI) {
|
2014-12-11 05:24:10 +08:00
|
|
|
return (MI->getOpcode() == Hexagon::J2_jump);
|
2012-05-04 05:52:53 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static bool IsSchedBarrier(MachineInstr* MI) {
|
|
|
|
switch (MI->getOpcode()) {
|
2015-02-06 02:56:28 +08:00
|
|
|
case Hexagon::Y2_barrier:
|
2012-05-04 05:52:53 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool IsControlFlow(MachineInstr* MI) {
|
|
|
|
return (MI->getDesc().isTerminator() || MI->getDesc().isCall());
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool IsLoopN(MachineInstr *MI) {
|
2014-12-19 08:06:53 +08:00
|
|
|
return (MI->getOpcode() == Hexagon::J2_loop0i ||
|
|
|
|
MI->getOpcode() == Hexagon::J2_loop0r);
|
2012-05-04 05:52:53 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/// DoesModifyCalleeSavedReg - Returns true if the instruction modifies a
|
|
|
|
/// callee-saved register.
|
|
|
|
static bool DoesModifyCalleeSavedReg(MachineInstr *MI,
|
|
|
|
const TargetRegisterInfo *TRI) {
|
2015-03-12 05:41:28 +08:00
|
|
|
for (const MCPhysReg *CSR =
|
|
|
|
TRI->getCalleeSavedRegs(MI->getParent()->getParent());
|
|
|
|
*CSR; ++CSR) {
|
2012-05-04 05:52:53 +08:00
|
|
|
unsigned CalleeSavedReg = *CSR;
|
|
|
|
if (MI->modifiesRegister(CalleeSavedReg, TRI))
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Returns true if an instruction can be promoted to .new predicate
|
|
|
|
// or new-value store.
|
|
|
|
bool HexagonPacketizerList::isNewifiable(MachineInstr* MI) {
|
2013-05-11 04:58:11 +08:00
|
|
|
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
|
2015-03-24 00:01:03 +08:00
|
|
|
return isCondInst(MI) || QII->mayBeNewStore(MI);
|
2012-05-04 05:52:53 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
bool HexagonPacketizerList::isCondInst (MachineInstr* MI) {
|
|
|
|
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
|
|
|
|
const MCInstrDesc& TID = MI->getDesc();
|
|
|
|
// bug 5670: until that is fixed,
|
|
|
|
// this portion is disabled.
|
|
|
|
if ( TID.isConditionalBranch() // && !IsRegisterJump(MI)) ||
|
|
|
|
|| QII->isConditionalTransfer(MI)
|
|
|
|
|| QII->isConditionalALU32(MI)
|
|
|
|
|| QII->isConditionalLoad(MI)
|
|
|
|
|| QII->isConditionalStore(MI)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2012-05-15 03:35:42 +08:00
|
|
|
|
2012-05-04 05:52:53 +08:00
|
|
|
// Promote an instructiont to its .new form.
|
|
|
|
// At this time, we have already made a call to CanPromoteToDotNew
|
|
|
|
// and made sure that it can *indeed* be promoted.
|
|
|
|
bool HexagonPacketizerList::PromoteToDotNew(MachineInstr* MI,
|
|
|
|
SDep::Kind DepType, MachineBasicBlock::iterator &MII,
|
|
|
|
const TargetRegisterClass* RC) {
|
|
|
|
|
|
|
|
assert (DepType == SDep::Data);
|
|
|
|
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
|
|
|
|
|
|
|
|
int NewOpcode;
|
|
|
|
if (RC == &Hexagon::PredRegsRegClass)
|
2013-05-10 03:16:07 +08:00
|
|
|
NewOpcode = QII->GetDotNewPredOp(MI, MBPI);
|
2012-05-04 05:52:53 +08:00
|
|
|
else
|
2013-05-11 04:27:34 +08:00
|
|
|
NewOpcode = QII->GetDotNewOp(MI);
|
2012-05-04 05:52:53 +08:00
|
|
|
MI->setDesc(QII->get(NewOpcode));
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool HexagonPacketizerList::DemoteToDotOld(MachineInstr* MI) {
|
|
|
|
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
|
2013-05-11 04:58:11 +08:00
|
|
|
int NewOpcode = QII->GetDotOldOp(MI->getOpcode());
|
2012-05-04 05:52:53 +08:00
|
|
|
MI->setDesc(QII->get(NewOpcode));
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2013-05-11 04:27:34 +08:00
|
|
|
enum PredicateKind {
|
|
|
|
PK_False,
|
|
|
|
PK_True,
|
|
|
|
PK_Unknown
|
|
|
|
};
|
2012-05-04 05:52:53 +08:00
|
|
|
|
2013-05-11 04:27:34 +08:00
|
|
|
/// Returns true if an instruction is predicated on p0 and false if it's
|
|
|
|
/// predicated on !p0.
|
|
|
|
static PredicateKind getPredicateSense(MachineInstr* MI,
|
|
|
|
const HexagonInstrInfo *QII) {
|
|
|
|
if (!QII->isPredicated(MI))
|
|
|
|
return PK_Unknown;
|
2012-05-04 05:52:53 +08:00
|
|
|
|
2013-05-11 04:27:34 +08:00
|
|
|
if (QII->isPredicatedTrue(MI))
|
|
|
|
return PK_True;
|
2012-05-04 05:52:53 +08:00
|
|
|
|
2013-05-11 04:27:34 +08:00
|
|
|
return PK_False;
|
2012-05-04 05:52:53 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static MachineOperand& GetPostIncrementOperand(MachineInstr *MI,
|
|
|
|
const HexagonInstrInfo *QII) {
|
|
|
|
assert(QII->isPostIncrement(MI) && "Not a post increment operation.");
|
|
|
|
#ifndef NDEBUG
|
|
|
|
// Post Increment means duplicates. Use dense map to find duplicates in the
|
|
|
|
// list. Caution: Densemap initializes with the minimum of 64 buckets,
|
|
|
|
// whereas there are at most 5 operands in the post increment.
|
|
|
|
DenseMap<unsigned, unsigned> DefRegsSet;
|
|
|
|
for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)
|
|
|
|
if (MI->getOperand(opNum).isReg() &&
|
|
|
|
MI->getOperand(opNum).isDef()) {
|
|
|
|
DefRegsSet[MI->getOperand(opNum).getReg()] = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)
|
|
|
|
if (MI->getOperand(opNum).isReg() &&
|
|
|
|
MI->getOperand(opNum).isUse()) {
|
|
|
|
if (DefRegsSet[MI->getOperand(opNum).getReg()]) {
|
|
|
|
return MI->getOperand(opNum);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
if (MI->getDesc().mayLoad()) {
|
|
|
|
// The 2nd operand is always the post increment operand in load.
|
|
|
|
assert(MI->getOperand(1).isReg() &&
|
|
|
|
"Post increment operand has be to a register.");
|
|
|
|
return (MI->getOperand(1));
|
|
|
|
}
|
|
|
|
if (MI->getDesc().mayStore()) {
|
|
|
|
// The 1st operand is always the post increment operand in store.
|
|
|
|
assert(MI->getOperand(0).isReg() &&
|
|
|
|
"Post increment operand has be to a register.");
|
|
|
|
return (MI->getOperand(0));
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
// we should never come here.
|
|
|
|
llvm_unreachable("mayLoad or mayStore not set for Post Increment operation");
|
|
|
|
}
|
|
|
|
|
|
|
|
// get the value being stored
|
|
|
|
static MachineOperand& GetStoreValueOperand(MachineInstr *MI) {
|
|
|
|
// value being stored is always the last operand.
|
|
|
|
return (MI->getOperand(MI->getNumOperands()-1));
|
|
|
|
}
|
|
|
|
|
|
|
|
// can be new value store?
|
|
|
|
// Following restrictions are to be respected in convert a store into
|
|
|
|
// a new value store.
|
|
|
|
// 1. If an instruction uses auto-increment, its address register cannot
|
|
|
|
// be a new-value register. Arch Spec 5.4.2.1
|
|
|
|
// 2. If an instruction uses absolute-set addressing mode,
|
|
|
|
// its address register cannot be a new-value register.
|
|
|
|
// Arch Spec 5.4.2.1.TODO: This is not enabled as
|
|
|
|
// as absolute-set address mode patters are not implemented.
|
|
|
|
// 3. If an instruction produces a 64-bit result, its registers cannot be used
|
|
|
|
// as new-value registers. Arch Spec 5.4.2.2.
|
|
|
|
// 4. If the instruction that sets a new-value register is conditional, then
|
|
|
|
// the instruction that uses the new-value register must also be conditional,
|
|
|
|
// and both must always have their predicates evaluate identically.
|
|
|
|
// Arch Spec 5.4.2.3.
|
|
|
|
// 5. There is an implied restriction of a packet can not have another store,
|
|
|
|
// if there is a new value store in the packet. Corollary, if there is
|
|
|
|
// already a store in a packet, there can not be a new value store.
|
|
|
|
// Arch Spec: 3.4.4.2
|
2014-10-05 00:55:56 +08:00
|
|
|
bool HexagonPacketizerList::CanPromoteToNewValueStore(
|
|
|
|
MachineInstr *MI, MachineInstr *PacketMI, unsigned DepReg,
|
|
|
|
const std::map<MachineInstr *, SUnit *> &MIToSUnit) {
|
2013-05-11 04:58:11 +08:00
|
|
|
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
|
|
|
|
// Make sure we are looking at the store, that can be promoted.
|
|
|
|
if (!QII->mayBeNewStore(MI))
|
2012-05-04 05:52:53 +08:00
|
|
|
return false;
|
|
|
|
|
|
|
|
// Make sure there is dependency and can be new value'ed
|
|
|
|
if (GetStoreValueOperand(MI).isReg() &&
|
|
|
|
GetStoreValueOperand(MI).getReg() != DepReg)
|
|
|
|
return false;
|
|
|
|
|
2014-08-05 05:25:23 +08:00
|
|
|
const HexagonRegisterInfo *QRI =
|
2014-10-14 09:03:16 +08:00
|
|
|
(const HexagonRegisterInfo *)MF.getSubtarget().getRegisterInfo();
|
2012-05-04 05:52:53 +08:00
|
|
|
const MCInstrDesc& MCID = PacketMI->getDesc();
|
|
|
|
// first operand is always the result
|
|
|
|
|
2012-05-08 06:10:26 +08:00
|
|
|
const TargetRegisterClass* PacketRC = QII->getRegClass(MCID, 0, QRI, MF);
|
2012-05-04 05:52:53 +08:00
|
|
|
|
|
|
|
// if there is already an store in the packet, no can do new value store
|
|
|
|
// Arch Spec 3.4.4.2.
|
|
|
|
for (std::vector<MachineInstr*>::iterator VI = CurrentPacketMIs.begin(),
|
|
|
|
VE = CurrentPacketMIs.end();
|
|
|
|
(VI != VE); ++VI) {
|
2014-10-05 00:55:56 +08:00
|
|
|
SUnit *PacketSU = MIToSUnit.find(*VI)->second;
|
2012-05-04 05:52:53 +08:00
|
|
|
if (PacketSU->getInstr()->getDesc().mayStore() ||
|
|
|
|
// if we have mayStore = 1 set on ALLOCFRAME and DEALLOCFRAME,
|
|
|
|
// then we don't need this
|
2014-12-30 05:33:45 +08:00
|
|
|
PacketSU->getInstr()->getOpcode() == Hexagon::S2_allocframe ||
|
2014-12-27 04:30:58 +08:00
|
|
|
PacketSU->getInstr()->getOpcode() == Hexagon::L2_deallocframe)
|
2012-05-04 05:52:53 +08:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (PacketRC == &Hexagon::DoubleRegsRegClass) {
|
|
|
|
// new value store constraint: double regs can not feed into new value store
|
|
|
|
// arch spec section: 5.4.2.2
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Make sure it's NOT the post increment register that we are going to
|
|
|
|
// new value.
|
|
|
|
if (QII->isPostIncrement(MI) &&
|
|
|
|
MI->getDesc().mayStore() &&
|
|
|
|
GetPostIncrementOperand(MI, QII).getReg() == DepReg) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (QII->isPostIncrement(PacketMI) &&
|
|
|
|
PacketMI->getDesc().mayLoad() &&
|
|
|
|
GetPostIncrementOperand(PacketMI, QII).getReg() == DepReg) {
|
|
|
|
// if source is post_inc, or absolute-set addressing,
|
|
|
|
// it can not feed into new value store
|
|
|
|
// r3 = memw(r2++#4)
|
|
|
|
// memw(r30 + #-1404) = r2.new -> can not be new value store
|
|
|
|
// arch spec section: 5.4.2.1
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// If the source that feeds the store is predicated, new value store must
|
2013-05-11 04:58:11 +08:00
|
|
|
// also be predicated.
|
2012-05-04 05:52:53 +08:00
|
|
|
if (QII->isPredicated(PacketMI)) {
|
|
|
|
if (!QII->isPredicated(MI))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Check to make sure that they both will have their predicates
|
|
|
|
// evaluate identically
|
2012-05-12 04:00:34 +08:00
|
|
|
unsigned predRegNumSrc = 0;
|
|
|
|
unsigned predRegNumDst = 0;
|
2014-04-25 13:30:21 +08:00
|
|
|
const TargetRegisterClass* predRegClass = nullptr;
|
2012-05-04 05:52:53 +08:00
|
|
|
|
|
|
|
// Get predicate register used in the source instruction
|
|
|
|
for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
|
|
|
|
if ( PacketMI->getOperand(opNum).isReg())
|
|
|
|
predRegNumSrc = PacketMI->getOperand(opNum).getReg();
|
|
|
|
predRegClass = QRI->getMinimalPhysRegClass(predRegNumSrc);
|
|
|
|
if (predRegClass == &Hexagon::PredRegsRegClass) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
|
|
|
|
("predicate register not found in a predicated PacketMI instruction"));
|
|
|
|
|
|
|
|
// Get predicate register used in new-value store instruction
|
|
|
|
for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
|
|
|
|
if ( MI->getOperand(opNum).isReg())
|
|
|
|
predRegNumDst = MI->getOperand(opNum).getReg();
|
|
|
|
predRegClass = QRI->getMinimalPhysRegClass(predRegNumDst);
|
|
|
|
if (predRegClass == &Hexagon::PredRegsRegClass) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
|
|
|
|
("predicate register not found in a predicated MI instruction"));
|
|
|
|
|
|
|
|
// New-value register producer and user (store) need to satisfy these
|
|
|
|
// constraints:
|
|
|
|
// 1) Both instructions should be predicated on the same register.
|
|
|
|
// 2) If producer of the new-value register is .new predicated then store
|
|
|
|
// should also be .new predicated and if producer is not .new predicated
|
|
|
|
// then store should not be .new predicated.
|
|
|
|
// 3) Both new-value register producer and user should have same predicate
|
|
|
|
// sense, i.e, either both should be negated or both should be none negated.
|
|
|
|
|
|
|
|
if (( predRegNumDst != predRegNumSrc) ||
|
2013-03-29 03:44:04 +08:00
|
|
|
QII->isDotNewInst(PacketMI) != QII->isDotNewInst(MI) ||
|
2013-05-11 04:27:34 +08:00
|
|
|
getPredicateSense(MI, QII) != getPredicateSense(PacketMI, QII)) {
|
2012-05-04 05:52:53 +08:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Make sure that other than the new-value register no other store instruction
|
|
|
|
// register has been modified in the same packet. Predicate registers can be
|
|
|
|
// modified by they should not be modified between the producer and the store
|
|
|
|
// instruction as it will make them both conditional on different values.
|
|
|
|
// We already know this to be true for all the instructions before and
|
|
|
|
// including PacketMI. Howerver, we need to perform the check for the
|
|
|
|
// remaining instructions in the packet.
|
|
|
|
|
|
|
|
std::vector<MachineInstr*>::iterator VI;
|
|
|
|
std::vector<MachineInstr*>::iterator VE;
|
|
|
|
unsigned StartCheck = 0;
|
|
|
|
|
|
|
|
for (VI=CurrentPacketMIs.begin(), VE = CurrentPacketMIs.end();
|
|
|
|
(VI != VE); ++VI) {
|
2014-10-05 00:55:56 +08:00
|
|
|
SUnit *TempSU = MIToSUnit.find(*VI)->second;
|
2012-05-04 05:52:53 +08:00
|
|
|
MachineInstr* TempMI = TempSU->getInstr();
|
|
|
|
|
|
|
|
// Following condition is true for all the instructions until PacketMI is
|
|
|
|
// reached (StartCheck is set to 0 before the for loop).
|
|
|
|
// StartCheck flag is 1 for all the instructions after PacketMI.
|
|
|
|
if (TempMI != PacketMI && !StartCheck) // start processing only after
|
|
|
|
continue; // encountering PacketMI
|
|
|
|
|
|
|
|
StartCheck = 1;
|
|
|
|
if (TempMI == PacketMI) // We don't want to check PacketMI for dependence
|
|
|
|
continue;
|
|
|
|
|
|
|
|
for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
|
|
|
|
if (MI->getOperand(opNum).isReg() &&
|
|
|
|
TempSU->getInstr()->modifiesRegister(MI->getOperand(opNum).getReg(),
|
|
|
|
QRI))
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-12-05 13:44:44 +08:00
|
|
|
// Make sure that for non-POST_INC stores:
|
2012-05-04 05:52:53 +08:00
|
|
|
// 1. The only use of reg is DepReg and no other registers.
|
|
|
|
// This handles V4 base+index registers.
|
|
|
|
// The following store can not be dot new.
|
|
|
|
// Eg. r0 = add(r0, #3)a
|
|
|
|
// memw(r1+r0<<#2) = r0
|
|
|
|
if (!QII->isPostIncrement(MI) &&
|
|
|
|
GetStoreValueOperand(MI).isReg() &&
|
|
|
|
GetStoreValueOperand(MI).getReg() == DepReg) {
|
|
|
|
for(unsigned opNum = 0; opNum < MI->getNumOperands()-1; opNum++) {
|
|
|
|
if (MI->getOperand(opNum).isReg() &&
|
|
|
|
MI->getOperand(opNum).getReg() == DepReg) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
// 2. If data definition is because of implicit definition of the register,
|
|
|
|
// do not newify the store. Eg.
|
|
|
|
// %R9<def> = ZXTH %R12, %D6<imp-use>, %R12<imp-def>
|
|
|
|
// STrih_indexed %R8, 2, %R12<kill>; mem:ST2[%scevgep343]
|
|
|
|
for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
|
|
|
|
if (PacketMI->getOperand(opNum).isReg() &&
|
|
|
|
PacketMI->getOperand(opNum).getReg() == DepReg &&
|
|
|
|
PacketMI->getOperand(opNum).isDef() &&
|
|
|
|
PacketMI->getOperand(opNum).isImplicit()) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Can be dot new store.
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
// can this MI to promoted to either
|
|
|
|
// new value store or new value jump
|
2014-10-05 00:55:56 +08:00
|
|
|
bool HexagonPacketizerList::CanPromoteToNewValue(
|
|
|
|
MachineInstr *MI, SUnit *PacketSU, unsigned DepReg,
|
|
|
|
const std::map<MachineInstr *, SUnit *> &MIToSUnit,
|
|
|
|
MachineBasicBlock::iterator &MII) {
|
2012-05-04 05:52:53 +08:00
|
|
|
|
2013-05-11 04:58:11 +08:00
|
|
|
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
|
2015-02-10 05:56:37 +08:00
|
|
|
if (!QII->mayBeNewStore(MI))
|
2012-05-04 05:52:53 +08:00
|
|
|
return false;
|
|
|
|
|
|
|
|
MachineInstr *PacketMI = PacketSU->getInstr();
|
|
|
|
|
|
|
|
// Check to see the store can be new value'ed.
|
|
|
|
if (CanPromoteToNewValueStore(MI, PacketMI, DepReg, MIToSUnit))
|
|
|
|
return true;
|
|
|
|
|
|
|
|
// Check to see the compare/jump can be new value'ed.
|
|
|
|
// This is done as a pass on its own. Don't need to check it here.
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Check to see if an instruction can be dot new
|
|
|
|
// There are three kinds.
|
|
|
|
// 1. dot new on predicate - V2/V3/V4
|
|
|
|
// 2. dot new on stores NV/ST - V4
|
|
|
|
// 3. dot new on jump NV/J - V4 -- This is generated in a pass.
|
2014-10-05 00:55:56 +08:00
|
|
|
bool HexagonPacketizerList::CanPromoteToDotNew(
|
|
|
|
MachineInstr *MI, SUnit *PacketSU, unsigned DepReg,
|
|
|
|
const std::map<MachineInstr *, SUnit *> &MIToSUnit,
|
|
|
|
MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC) {
|
2013-03-29 03:44:04 +08:00
|
|
|
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
|
|
|
|
// Already a dot new instruction.
|
2013-05-11 04:58:11 +08:00
|
|
|
if (QII->isDotNewInst(MI) && !QII->mayBeNewStore(MI))
|
2012-05-04 05:52:53 +08:00
|
|
|
return false;
|
|
|
|
|
|
|
|
if (!isNewifiable(MI))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// predicate .new
|
|
|
|
if (RC == &Hexagon::PredRegsRegClass && isCondInst(MI))
|
|
|
|
return true;
|
|
|
|
else if (RC != &Hexagon::PredRegsRegClass &&
|
2013-05-11 04:58:11 +08:00
|
|
|
!QII->mayBeNewStore(MI)) // MI is not a new-value store
|
2012-05-04 05:52:53 +08:00
|
|
|
return false;
|
|
|
|
else {
|
|
|
|
// Create a dot new machine instruction to see if resources can be
|
|
|
|
// allocated. If not, bail out now.
|
2013-05-11 04:27:34 +08:00
|
|
|
int NewOpcode = QII->GetDotNewOp(MI);
|
2012-05-04 05:52:53 +08:00
|
|
|
const MCInstrDesc &desc = QII->get(NewOpcode);
|
|
|
|
DebugLoc dl;
|
|
|
|
MachineInstr *NewMI =
|
|
|
|
MI->getParent()->getParent()->CreateMachineInstr(desc, dl);
|
|
|
|
bool ResourcesAvailable = ResourceTracker->canReserveResources(NewMI);
|
|
|
|
MI->getParent()->getParent()->DeleteMachineInstr(NewMI);
|
|
|
|
|
|
|
|
if (!ResourcesAvailable)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// new value store only
|
|
|
|
// new new value jump generated as a passes
|
|
|
|
if (!CanPromoteToNewValue(MI, PacketSU, DepReg, MIToSUnit, MII)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Go through the packet instructions and search for anti dependency
|
|
|
|
// between them and DepReg from MI
|
|
|
|
// Consider this case:
|
|
|
|
// Trying to add
|
|
|
|
// a) %R1<def> = TFRI_cdNotPt %P3, 2
|
|
|
|
// to this packet:
|
|
|
|
// {
|
|
|
|
// b) %P0<def> = OR_pp %P3<kill>, %P0<kill>
|
|
|
|
// c) %P3<def> = TFR_PdRs %R23
|
|
|
|
// d) %R1<def> = TFRI_cdnPt %P3, 4
|
|
|
|
// }
|
|
|
|
// The P3 from a) and d) will be complements after
|
|
|
|
// a)'s P3 is converted to .new form
|
|
|
|
// Anti Dep between c) and b) is irrelevant for this case
|
2014-10-05 00:55:56 +08:00
|
|
|
bool HexagonPacketizerList::RestrictingDepExistInPacket(
|
|
|
|
MachineInstr *MI, unsigned DepReg,
|
|
|
|
const std::map<MachineInstr *, SUnit *> &MIToSUnit) {
|
2012-05-04 05:52:53 +08:00
|
|
|
|
|
|
|
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
|
2014-10-05 00:55:56 +08:00
|
|
|
SUnit *PacketSUDep = MIToSUnit.find(MI)->second;
|
2012-05-04 05:52:53 +08:00
|
|
|
|
|
|
|
for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),
|
|
|
|
VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
|
|
|
|
|
|
|
|
// We only care for dependencies to predicated instructions
|
|
|
|
if(!QII->isPredicated(*VIN)) continue;
|
|
|
|
|
|
|
|
// Scheduling Unit for current insn in the packet
|
2014-10-05 00:55:56 +08:00
|
|
|
SUnit *PacketSU = MIToSUnit.find(*VIN)->second;
|
2012-05-04 05:52:53 +08:00
|
|
|
|
|
|
|
// Look at dependencies between current members of the packet
|
|
|
|
// and predicate defining instruction MI.
|
|
|
|
// Make sure that dependency is on the exact register
|
|
|
|
// we care about.
|
|
|
|
if (PacketSU->isSucc(PacketSUDep)) {
|
|
|
|
for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
|
|
|
|
if ((PacketSU->Succs[i].getSUnit() == PacketSUDep) &&
|
|
|
|
(PacketSU->Succs[i].getKind() == SDep::Anti) &&
|
|
|
|
(PacketSU->Succs[i].getReg() == DepReg)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2013-05-15 00:36:34 +08:00
|
|
|
/// Gets the predicate register of a predicated instruction.
|
2013-05-23 23:43:11 +08:00
|
|
|
static unsigned getPredicatedRegister(MachineInstr *MI,
|
|
|
|
const HexagonInstrInfo *QII) {
|
2013-05-15 00:36:34 +08:00
|
|
|
/// We use the following rule: The first predicate register that is a use is
|
|
|
|
/// the predicate register of a predicated instruction.
|
|
|
|
|
|
|
|
assert(QII->isPredicated(MI) && "Must be predicated instruction");
|
|
|
|
|
|
|
|
for (MachineInstr::mop_iterator OI = MI->operands_begin(),
|
|
|
|
OE = MI->operands_end(); OI != OE; ++OI) {
|
|
|
|
MachineOperand &Op = *OI;
|
|
|
|
if (Op.isReg() && Op.getReg() && Op.isUse() &&
|
|
|
|
Hexagon::PredRegsRegClass.contains(Op.getReg()))
|
|
|
|
return Op.getReg();
|
|
|
|
}
|
|
|
|
|
|
|
|
llvm_unreachable("Unknown instruction operand layout");
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-05-04 05:52:53 +08:00
|
|
|
// Given two predicated instructions, this function detects whether
|
|
|
|
// the predicates are complements
|
2014-10-05 00:55:56 +08:00
|
|
|
bool HexagonPacketizerList::ArePredicatesComplements(
|
|
|
|
MachineInstr *MI1, MachineInstr *MI2,
|
|
|
|
const std::map<MachineInstr *, SUnit *> &MIToSUnit) {
|
2012-05-04 05:52:53 +08:00
|
|
|
|
|
|
|
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
|
2013-05-15 00:36:34 +08:00
|
|
|
|
|
|
|
// If we don't know the predicate sense of the instructions bail out early, we
|
|
|
|
// need it later.
|
|
|
|
if (getPredicateSense(MI1, QII) == PK_Unknown ||
|
|
|
|
getPredicateSense(MI2, QII) == PK_Unknown)
|
2012-05-04 05:52:53 +08:00
|
|
|
return false;
|
|
|
|
|
|
|
|
// Scheduling unit for candidate
|
2014-10-05 00:55:56 +08:00
|
|
|
SUnit *SU = MIToSUnit.find(MI1)->second;
|
2012-05-04 05:52:53 +08:00
|
|
|
|
|
|
|
// One corner case deals with the following scenario:
|
|
|
|
// Trying to add
|
|
|
|
// a) %R24<def> = TFR_cPt %P0, %R25
|
|
|
|
// to this packet:
|
|
|
|
//
|
|
|
|
// {
|
|
|
|
// b) %R25<def> = TFR_cNotPt %P0, %R24
|
|
|
|
// c) %P0<def> = CMPEQri %R26, 1
|
|
|
|
// }
|
|
|
|
//
|
|
|
|
// On general check a) and b) are complements, but
|
|
|
|
// presence of c) will convert a) to .new form, and
|
|
|
|
// then it is not a complement
|
|
|
|
// We attempt to detect it by analyzing existing
|
|
|
|
// dependencies in the packet
|
|
|
|
|
|
|
|
// Analyze relationships between all existing members of the packet.
|
|
|
|
// Look for Anti dependecy on the same predicate reg
|
|
|
|
// as used in the candidate
|
|
|
|
for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),
|
|
|
|
VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
|
|
|
|
|
|
|
|
// Scheduling Unit for current insn in the packet
|
2014-10-05 00:55:56 +08:00
|
|
|
SUnit *PacketSU = MIToSUnit.find(*VIN)->second;
|
2012-05-04 05:52:53 +08:00
|
|
|
|
|
|
|
// If this instruction in the packet is succeeded by the candidate...
|
|
|
|
if (PacketSU->isSucc(SU)) {
|
|
|
|
for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
|
|
|
|
// The corner case exist when there is true data
|
|
|
|
// dependency between candidate and one of current
|
|
|
|
// packet members, this dep is on predicate reg, and
|
|
|
|
// there already exist anti dep on the same pred in
|
|
|
|
// the packet.
|
|
|
|
if (PacketSU->Succs[i].getSUnit() == SU &&
|
2013-05-15 00:36:34 +08:00
|
|
|
PacketSU->Succs[i].getKind() == SDep::Data &&
|
2012-05-04 05:52:53 +08:00
|
|
|
Hexagon::PredRegsRegClass.contains(
|
|
|
|
PacketSU->Succs[i].getReg()) &&
|
|
|
|
// Here I know that *VIN is predicate setting instruction
|
|
|
|
// with true data dep to candidate on the register
|
|
|
|
// we care about - c) in the above example.
|
|
|
|
// Now I need to see if there is an anti dependency
|
|
|
|
// from c) to any other instruction in the
|
|
|
|
// same packet on the pred reg of interest
|
|
|
|
RestrictingDepExistInPacket(*VIN,PacketSU->Succs[i].getReg(),
|
|
|
|
MIToSUnit)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// If the above case does not apply, check regular
|
|
|
|
// complement condition.
|
|
|
|
// Check that the predicate register is the same and
|
|
|
|
// that the predicate sense is different
|
|
|
|
// We also need to differentiate .old vs. .new:
|
|
|
|
// !p0 is not complimentary to p0.new
|
2013-05-15 00:36:34 +08:00
|
|
|
unsigned PReg1 = getPredicatedRegister(MI1, QII);
|
|
|
|
unsigned PReg2 = getPredicatedRegister(MI2, QII);
|
|
|
|
return ((PReg1 == PReg2) &&
|
|
|
|
Hexagon::PredRegsRegClass.contains(PReg1) &&
|
|
|
|
Hexagon::PredRegsRegClass.contains(PReg2) &&
|
2013-05-11 04:27:34 +08:00
|
|
|
(getPredicateSense(MI1, QII) != getPredicateSense(MI2, QII)) &&
|
2013-03-29 03:44:04 +08:00
|
|
|
(QII->isDotNewInst(MI1) == QII->isDotNewInst(MI2)));
|
2012-05-04 05:52:53 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// initPacketizerState - Initialize packetizer flags
|
|
|
|
void HexagonPacketizerList::initPacketizerState() {
|
|
|
|
|
|
|
|
Dependence = false;
|
|
|
|
PromotedToDotNew = false;
|
|
|
|
GlueToNewValueJump = false;
|
|
|
|
GlueAllocframeStore = false;
|
|
|
|
FoundSequentialDependence = false;
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
// ignorePseudoInstruction - Ignore bundling of pseudo instructions.
|
|
|
|
bool HexagonPacketizerList::ignorePseudoInstruction(MachineInstr *MI,
|
|
|
|
MachineBasicBlock *MBB) {
|
|
|
|
if (MI->isDebugValue())
|
|
|
|
return true;
|
|
|
|
|
2015-04-22 23:47:35 +08:00
|
|
|
if (MI->isCFIInstruction())
|
|
|
|
return false;
|
|
|
|
|
2012-05-04 05:52:53 +08:00
|
|
|
// We must print out inline assembly
|
|
|
|
if (MI->isInlineAsm())
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// We check if MI has any functional units mapped to it.
|
|
|
|
// If it doesn't, we ignore the instruction.
|
|
|
|
const MCInstrDesc& TID = MI->getDesc();
|
|
|
|
unsigned SchedClass = TID.getSchedClass();
|
|
|
|
const InstrStage* IS =
|
|
|
|
ResourceTracker->getInstrItins()->beginStage(SchedClass);
|
2012-06-23 04:27:13 +08:00
|
|
|
unsigned FuncUnits = IS->getUnits();
|
2012-05-04 05:52:53 +08:00
|
|
|
return !FuncUnits;
|
|
|
|
}
|
|
|
|
|
|
|
|
// isSoloInstruction: - Returns true for instructions that must be
|
|
|
|
// scheduled in their own packet.
|
|
|
|
bool HexagonPacketizerList::isSoloInstruction(MachineInstr *MI) {
|
2015-04-22 23:47:35 +08:00
|
|
|
if (MI->isEHLabel() || MI->isCFIInstruction())
|
2012-05-04 05:52:53 +08:00
|
|
|
return true;
|
|
|
|
|
2015-04-22 23:47:35 +08:00
|
|
|
if (MI->isInlineAsm())
|
2012-05-04 05:52:53 +08:00
|
|
|
return true;
|
|
|
|
|
|
|
|
// From Hexagon V4 Programmer's Reference Manual 3.4.4 Grouping constraints:
|
|
|
|
// trap, pause, barrier, icinva, isync, and syncht are solo instructions.
|
|
|
|
// They must not be grouped with other instructions in a packet.
|
|
|
|
if (IsSchedBarrier(MI))
|
|
|
|
return true;
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// isLegalToPacketizeTogether:
|
|
|
|
// SUI is the current instruction that is out side of the current packet.
|
|
|
|
// SUJ is the current instruction inside the current packet against which that
|
|
|
|
// SUI will be packetized.
|
|
|
|
bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
|
|
|
|
MachineInstr *I = SUI->getInstr();
|
|
|
|
MachineInstr *J = SUJ->getInstr();
|
|
|
|
assert(I && J && "Unable to packetize null instruction!");
|
|
|
|
|
|
|
|
const MCInstrDesc &MCIDI = I->getDesc();
|
|
|
|
const MCInstrDesc &MCIDJ = J->getDesc();
|
|
|
|
|
|
|
|
MachineBasicBlock::iterator II = I;
|
|
|
|
|
|
|
|
const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
|
2014-08-05 05:25:23 +08:00
|
|
|
const HexagonRegisterInfo *QRI =
|
2014-10-14 09:03:16 +08:00
|
|
|
(const HexagonRegisterInfo *)MF.getSubtarget().getRegisterInfo();
|
2012-05-04 05:52:53 +08:00
|
|
|
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
|
|
|
|
|
|
|
|
// Inline asm cannot go in the packet.
|
|
|
|
if (I->getOpcode() == Hexagon::INLINEASM)
|
|
|
|
llvm_unreachable("Should not meet inline asm here!");
|
|
|
|
|
|
|
|
if (isSoloInstruction(I))
|
|
|
|
llvm_unreachable("Should not meet solo instr here!");
|
|
|
|
|
|
|
|
// A save callee-save register function call can only be in a packet
|
|
|
|
// with instructions that don't write to the callee-save registers.
|
|
|
|
if ((QII->isSaveCalleeSavedRegsCall(I) &&
|
|
|
|
DoesModifyCalleeSavedReg(J, QRI)) ||
|
|
|
|
(QII->isSaveCalleeSavedRegsCall(J) &&
|
|
|
|
DoesModifyCalleeSavedReg(I, QRI))) {
|
|
|
|
Dependence = true;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Two control flow instructions cannot go in the same packet.
|
|
|
|
if (IsControlFlow(I) && IsControlFlow(J)) {
|
|
|
|
Dependence = true;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// A LoopN instruction cannot appear in the same packet as a jump or call.
|
2013-05-11 04:58:11 +08:00
|
|
|
if (IsLoopN(I) &&
|
|
|
|
(IsDirectJump(J) || MCIDJ.isCall() || QII->isDeallocRet(J))) {
|
2012-05-04 05:52:53 +08:00
|
|
|
Dependence = true;
|
|
|
|
return false;
|
|
|
|
}
|
2013-05-11 04:58:11 +08:00
|
|
|
if (IsLoopN(J) &&
|
|
|
|
(IsDirectJump(I) || MCIDI.isCall() || QII->isDeallocRet(I))) {
|
2012-05-04 05:52:53 +08:00
|
|
|
Dependence = true;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// dealloc_return cannot appear in the same packet as a conditional or
|
|
|
|
// unconditional jump.
|
2013-05-11 04:58:11 +08:00
|
|
|
if (QII->isDeallocRet(I) &&
|
|
|
|
(MCIDJ.isBranch() || MCIDJ.isCall() || MCIDJ.isBarrier())) {
|
2012-05-04 05:52:53 +08:00
|
|
|
Dependence = true;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
// V4 allows dual store. But does not allow second store, if the
|
|
|
|
// first store is not in SLOT0. New value store, new value jump,
|
|
|
|
// dealloc_return and memop always take SLOT0.
|
|
|
|
// Arch spec 3.4.4.2
|
2015-02-10 05:56:37 +08:00
|
|
|
if (MCIDI.mayStore() && MCIDJ.mayStore() &&
|
|
|
|
(QII->isNewValueInst(J) || QII->isMemOp(J) || QII->isMemOp(I))) {
|
|
|
|
Dependence = true;
|
|
|
|
return false;
|
|
|
|
}
|
2012-05-04 05:52:53 +08:00
|
|
|
|
2015-02-10 05:56:37 +08:00
|
|
|
if ((QII->isMemOp(J) && MCIDI.mayStore())
|
|
|
|
|| (MCIDJ.mayStore() && QII->isMemOp(I))
|
|
|
|
|| (QII->isMemOp(J) && QII->isMemOp(I))) {
|
|
|
|
Dependence = true;
|
|
|
|
return false;
|
|
|
|
}
|
2012-05-04 05:52:53 +08:00
|
|
|
|
2015-02-10 05:56:37 +08:00
|
|
|
//if dealloc_return
|
|
|
|
if (MCIDJ.mayStore() && QII->isDeallocRet(I)) {
|
|
|
|
Dependence = true;
|
|
|
|
return false;
|
|
|
|
}
|
2012-05-04 05:52:53 +08:00
|
|
|
|
2015-02-10 05:56:37 +08:00
|
|
|
// If an instruction feeds new value jump, glue it.
|
|
|
|
MachineBasicBlock::iterator NextMII = I;
|
|
|
|
++NextMII;
|
|
|
|
if (NextMII != I->getParent()->end() && QII->isNewValueJump(NextMII)) {
|
|
|
|
MachineInstr *NextMI = NextMII;
|
2012-05-04 05:52:53 +08:00
|
|
|
|
2015-02-10 05:56:37 +08:00
|
|
|
bool secondRegMatch = false;
|
|
|
|
bool maintainNewValueJump = false;
|
2012-05-04 05:52:53 +08:00
|
|
|
|
2015-02-10 05:56:37 +08:00
|
|
|
if (NextMI->getOperand(1).isReg() &&
|
|
|
|
I->getOperand(0).getReg() == NextMI->getOperand(1).getReg()) {
|
|
|
|
secondRegMatch = true;
|
|
|
|
maintainNewValueJump = true;
|
|
|
|
}
|
2012-05-04 05:52:53 +08:00
|
|
|
|
2015-02-10 05:56:37 +08:00
|
|
|
if (!secondRegMatch &&
|
|
|
|
I->getOperand(0).getReg() == NextMI->getOperand(0).getReg()) {
|
|
|
|
maintainNewValueJump = true;
|
|
|
|
}
|
2012-05-04 05:52:53 +08:00
|
|
|
|
2015-02-10 05:56:37 +08:00
|
|
|
for (std::vector<MachineInstr*>::iterator
|
|
|
|
VI = CurrentPacketMIs.begin(),
|
|
|
|
VE = CurrentPacketMIs.end();
|
|
|
|
(VI != VE && maintainNewValueJump); ++VI) {
|
|
|
|
SUnit *PacketSU = MIToSUnit.find(*VI)->second;
|
2012-05-04 05:52:53 +08:00
|
|
|
|
2015-02-10 05:56:37 +08:00
|
|
|
// NVJ can not be part of the dual jump - Arch Spec: section 7.8
|
|
|
|
if (PacketSU->getInstr()->getDesc().isCall()) {
|
|
|
|
Dependence = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
// Validate
|
|
|
|
// 1. Packet does not have a store in it.
|
|
|
|
// 2. If the first operand of the nvj is newified, and the second
|
|
|
|
// operand is also a reg, it (second reg) is not defined in
|
|
|
|
// the same packet.
|
|
|
|
// 3. If the second operand of the nvj is newified, (which means
|
|
|
|
// first operand is also a reg), first reg is not defined in
|
|
|
|
// the same packet.
|
|
|
|
if (PacketSU->getInstr()->getDesc().mayStore() ||
|
|
|
|
PacketSU->getInstr()->getOpcode() == Hexagon::S2_allocframe ||
|
|
|
|
// Check #2.
|
|
|
|
(!secondRegMatch && NextMI->getOperand(1).isReg() &&
|
|
|
|
PacketSU->getInstr()->modifiesRegister(
|
|
|
|
NextMI->getOperand(1).getReg(), QRI)) ||
|
|
|
|
// Check #3.
|
|
|
|
(secondRegMatch &&
|
|
|
|
PacketSU->getInstr()->modifiesRegister(
|
|
|
|
NextMI->getOperand(0).getReg(), QRI))) {
|
|
|
|
Dependence = true;
|
|
|
|
break;
|
2012-05-04 05:52:53 +08:00
|
|
|
}
|
|
|
|
}
|
2015-02-10 05:56:37 +08:00
|
|
|
if (!Dependence)
|
|
|
|
GlueToNewValueJump = true;
|
|
|
|
else
|
|
|
|
return false;
|
2012-05-04 05:52:53 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
if (SUJ->isSucc(SUI)) {
|
|
|
|
for (unsigned i = 0;
|
|
|
|
(i < SUJ->Succs.size()) && !FoundSequentialDependence;
|
|
|
|
++i) {
|
|
|
|
|
|
|
|
if (SUJ->Succs[i].getSUnit() != SUI) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
SDep::Kind DepType = SUJ->Succs[i].getKind();
|
|
|
|
|
|
|
|
// For direct calls:
|
|
|
|
// Ignore register dependences for call instructions for
|
|
|
|
// packetization purposes except for those due to r31 and
|
|
|
|
// predicate registers.
|
|
|
|
//
|
|
|
|
// For indirect calls:
|
|
|
|
// Same as direct calls + check for true dependences to the register
|
|
|
|
// used in the indirect call.
|
|
|
|
//
|
|
|
|
// We completely ignore Order dependences for call instructions
|
|
|
|
//
|
|
|
|
// For returns:
|
|
|
|
// Ignore register dependences for return instructions like jumpr,
|
|
|
|
// dealloc return unless we have dependencies on the explicit uses
|
|
|
|
// of the registers used by jumpr (like r31) or dealloc return
|
|
|
|
// (like r29 or r30).
|
|
|
|
//
|
|
|
|
// TODO: Currently, jumpr is handling only return of r31. So, the
|
|
|
|
// following logic (specificaly IsCallDependent) is working fine.
|
|
|
|
// We need to enable jumpr for register other than r31 and then,
|
|
|
|
// we need to rework the last part, where it handles indirect call
|
|
|
|
// of that (IsCallDependent) function. Bug 6216 is opened for this.
|
|
|
|
//
|
|
|
|
unsigned DepReg = 0;
|
2014-04-25 13:30:21 +08:00
|
|
|
const TargetRegisterClass* RC = nullptr;
|
2012-05-04 05:52:53 +08:00
|
|
|
if (DepType == SDep::Data) {
|
|
|
|
DepReg = SUJ->Succs[i].getReg();
|
|
|
|
RC = QRI->getMinimalPhysRegClass(DepReg);
|
|
|
|
}
|
|
|
|
if ((MCIDI.isCall() || MCIDI.isReturn()) &&
|
|
|
|
(!IsRegDependence(DepType) ||
|
|
|
|
!IsCallDependent(I, DepType, SUJ->Succs[i].getReg()))) {
|
|
|
|
/* do nothing */
|
|
|
|
}
|
|
|
|
|
|
|
|
// For instructions that can be promoted to dot-new, try to promote.
|
|
|
|
else if ((DepType == SDep::Data) &&
|
|
|
|
CanPromoteToDotNew(I, SUJ, DepReg, MIToSUnit, II, RC) &&
|
|
|
|
PromoteToDotNew(I, DepType, II, RC)) {
|
|
|
|
PromotedToDotNew = true;
|
|
|
|
/* do nothing */
|
|
|
|
}
|
|
|
|
|
|
|
|
else if ((DepType == SDep::Data) &&
|
|
|
|
(QII->isNewValueJump(I))) {
|
|
|
|
/* do nothing */
|
|
|
|
}
|
|
|
|
|
|
|
|
// For predicated instructions, if the predicates are complements
|
|
|
|
// then there can be no dependence.
|
|
|
|
else if (QII->isPredicated(I) &&
|
|
|
|
QII->isPredicated(J) &&
|
|
|
|
ArePredicatesComplements(I, J, MIToSUnit)) {
|
|
|
|
/* do nothing */
|
|
|
|
|
|
|
|
}
|
|
|
|
else if (IsDirectJump(I) &&
|
|
|
|
!MCIDJ.isBranch() &&
|
|
|
|
!MCIDJ.isCall() &&
|
|
|
|
(DepType == SDep::Order)) {
|
|
|
|
// Ignore Order dependences between unconditional direct branches
|
|
|
|
// and non-control-flow instructions
|
|
|
|
/* do nothing */
|
|
|
|
}
|
|
|
|
else if (MCIDI.isConditionalBranch() && (DepType != SDep::Data) &&
|
|
|
|
(DepType != SDep::Output)) {
|
|
|
|
// Ignore all dependences for jumps except for true and output
|
|
|
|
// dependences
|
|
|
|
/* do nothing */
|
|
|
|
}
|
|
|
|
|
|
|
|
// Ignore output dependences due to superregs. We can
|
|
|
|
// write to two different subregisters of R1:0 for instance
|
|
|
|
// in the same cycle
|
|
|
|
//
|
|
|
|
|
|
|
|
//
|
|
|
|
// Let the
|
|
|
|
// If neither I nor J defines DepReg, then this is a
|
|
|
|
// superfluous output dependence. The dependence must be of the
|
|
|
|
// form:
|
|
|
|
// R0 = ...
|
|
|
|
// R1 = ...
|
|
|
|
// and there is an output dependence between the two instructions
|
|
|
|
// with
|
|
|
|
// DepReg = D0
|
|
|
|
// We want to ignore these dependences.
|
|
|
|
// Ideally, the dependence constructor should annotate such
|
|
|
|
// dependences. We can then avoid this relatively expensive check.
|
|
|
|
//
|
|
|
|
else if (DepType == SDep::Output) {
|
|
|
|
// DepReg is the register that's responsible for the dependence.
|
|
|
|
unsigned DepReg = SUJ->Succs[i].getReg();
|
|
|
|
|
|
|
|
// Check if I and J really defines DepReg.
|
|
|
|
if (I->definesRegister(DepReg) ||
|
|
|
|
J->definesRegister(DepReg)) {
|
|
|
|
FoundSequentialDependence = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// We ignore Order dependences for
|
|
|
|
// 1. Two loads unless they are volatile.
|
|
|
|
// 2. Two stores in V4 unless they are volatile.
|
|
|
|
else if ((DepType == SDep::Order) &&
|
2012-08-30 05:19:21 +08:00
|
|
|
!I->hasOrderedMemoryRef() &&
|
|
|
|
!J->hasOrderedMemoryRef()) {
|
2015-02-10 05:56:37 +08:00
|
|
|
if (MCIDI.mayStore() && MCIDJ.mayStore()) {
|
2012-05-04 05:52:53 +08:00
|
|
|
/* do nothing */
|
|
|
|
}
|
|
|
|
// store followed by store-- not OK on V2
|
|
|
|
// store followed by load -- not OK on all (OK if addresses
|
|
|
|
// are not aliased)
|
|
|
|
// load followed by store -- OK on all
|
|
|
|
// load followed by load -- OK on all
|
|
|
|
else if ( !MCIDJ.mayStore()) {
|
|
|
|
/* do nothing */
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
FoundSequentialDependence = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// For V4, special case ALLOCFRAME. Even though there is dependency
|
2014-09-08 21:05:23 +08:00
|
|
|
// between ALLOCFRAME and subsequent store, allow it to be
|
2012-05-04 05:52:53 +08:00
|
|
|
// packetized in a same packet. This implies that the store is using
|
2014-09-08 21:05:23 +08:00
|
|
|
// caller's SP. Hence, offset needs to be updated accordingly.
|
2012-05-04 05:52:53 +08:00
|
|
|
else if (DepType == SDep::Data
|
2014-12-30 05:33:45 +08:00
|
|
|
&& J->getOpcode() == Hexagon::S2_allocframe
|
2014-12-30 04:44:51 +08:00
|
|
|
&& (I->getOpcode() == Hexagon::S2_storerd_io
|
|
|
|
|| I->getOpcode() == Hexagon::S2_storeri_io
|
|
|
|
|| I->getOpcode() == Hexagon::S2_storerb_io)
|
2012-05-04 05:52:53 +08:00
|
|
|
&& I->getOperand(0).getReg() == QRI->getStackRegister()
|
|
|
|
&& QII->isValidOffset(I->getOpcode(),
|
|
|
|
I->getOperand(1).getImm() -
|
|
|
|
(FrameSize + HEXAGON_LRFP_SIZE)))
|
|
|
|
{
|
|
|
|
GlueAllocframeStore = true;
|
|
|
|
// Since this store is to be glued with allocframe in the same
|
|
|
|
// packet, it will use SP of the previous stack frame, i.e
|
|
|
|
// caller's SP. Therefore, we need to recalculate offset according
|
|
|
|
// to this change.
|
|
|
|
I->getOperand(1).setImm(I->getOperand(1).getImm() -
|
|
|
|
(FrameSize + HEXAGON_LRFP_SIZE));
|
|
|
|
}
|
|
|
|
|
|
|
|
//
|
|
|
|
// Skip over anti-dependences. Two instructions that are
|
|
|
|
// anti-dependent can share a packet
|
|
|
|
//
|
|
|
|
else if (DepType != SDep::Anti) {
|
|
|
|
FoundSequentialDependence = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (FoundSequentialDependence) {
|
|
|
|
Dependence = true;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
// isLegalToPruneDependencies
|
|
|
|
bool HexagonPacketizerList::isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {
|
|
|
|
MachineInstr *I = SUI->getInstr();
|
|
|
|
assert(I && SUJ->getInstr() && "Unable to packetize null instruction!");
|
|
|
|
|
|
|
|
const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
|
|
|
|
|
|
|
|
if (Dependence) {
|
|
|
|
|
|
|
|
// Check if the instruction was promoted to a dot-new. If so, demote it
|
|
|
|
// back into a dot-old.
|
|
|
|
if (PromotedToDotNew) {
|
|
|
|
DemoteToDotOld(I);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Check if the instruction (must be a store) was glued with an Allocframe
|
|
|
|
// instruction. If so, restore its offset to its original value, i.e. use
|
|
|
|
// curent SP instead of caller's SP.
|
|
|
|
if (GlueAllocframeStore) {
|
|
|
|
I->getOperand(1).setImm(I->getOperand(1).getImm() +
|
|
|
|
FrameSize + HEXAGON_LRFP_SIZE);
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
MachineBasicBlock::iterator
|
|
|
|
HexagonPacketizerList::addToPacket(MachineInstr *MI) {
|
|
|
|
|
|
|
|
MachineBasicBlock::iterator MII = MI;
|
|
|
|
MachineBasicBlock *MBB = MI->getParent();
|
|
|
|
|
|
|
|
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
|
|
|
|
|
|
|
|
if (GlueToNewValueJump) {
|
|
|
|
|
|
|
|
++MII;
|
|
|
|
MachineInstr *nvjMI = MII;
|
|
|
|
assert(ResourceTracker->canReserveResources(MI));
|
|
|
|
ResourceTracker->reserveResources(MI);
|
2013-03-02 01:37:13 +08:00
|
|
|
if ((QII->isExtended(MI) || QII->isConstExtended(MI)) &&
|
2012-05-04 05:52:53 +08:00
|
|
|
!tryAllocateResourcesForConstExt(MI)) {
|
|
|
|
endPacket(MBB, MI);
|
|
|
|
ResourceTracker->reserveResources(MI);
|
|
|
|
assert(canReserveResourcesForConstExt(MI) &&
|
|
|
|
"Ensure that there is a slot");
|
|
|
|
reserveResourcesForConstExt(MI);
|
|
|
|
// Reserve resources for new value jump constant extender.
|
|
|
|
assert(canReserveResourcesForConstExt(MI) &&
|
|
|
|
"Ensure that there is a slot");
|
|
|
|
reserveResourcesForConstExt(nvjMI);
|
|
|
|
assert(ResourceTracker->canReserveResources(nvjMI) &&
|
|
|
|
"Ensure that there is a slot");
|
|
|
|
|
|
|
|
} else if ( // Extended instruction takes two slots in the packet.
|
|
|
|
// Try reserve and allocate 4-byte in the current packet first.
|
|
|
|
(QII->isExtended(nvjMI)
|
|
|
|
&& (!tryAllocateResourcesForConstExt(nvjMI)
|
|
|
|
|| !ResourceTracker->canReserveResources(nvjMI)))
|
|
|
|
|| // For non-extended instruction, no need to allocate extra 4 bytes.
|
2013-03-02 01:37:13 +08:00
|
|
|
(!QII->isExtended(nvjMI) &&
|
2012-05-04 05:52:53 +08:00
|
|
|
!ResourceTracker->canReserveResources(nvjMI)))
|
|
|
|
{
|
|
|
|
endPacket(MBB, MI);
|
|
|
|
// A new and empty packet starts.
|
|
|
|
// We are sure that the resources requirements can be satisfied.
|
|
|
|
// Therefore, do not need to call "canReserveResources" anymore.
|
|
|
|
ResourceTracker->reserveResources(MI);
|
|
|
|
if (QII->isExtended(nvjMI))
|
|
|
|
reserveResourcesForConstExt(nvjMI);
|
|
|
|
}
|
|
|
|
// Here, we are sure that "reserveResources" would succeed.
|
|
|
|
ResourceTracker->reserveResources(nvjMI);
|
|
|
|
CurrentPacketMIs.push_back(MI);
|
|
|
|
CurrentPacketMIs.push_back(nvjMI);
|
|
|
|
} else {
|
2013-03-02 01:37:13 +08:00
|
|
|
if ( (QII->isExtended(MI) || QII->isConstExtended(MI))
|
2012-05-04 05:52:53 +08:00
|
|
|
&& ( !tryAllocateResourcesForConstExt(MI)
|
|
|
|
|| !ResourceTracker->canReserveResources(MI)))
|
|
|
|
{
|
|
|
|
endPacket(MBB, MI);
|
|
|
|
// Check if the instruction was promoted to a dot-new. If so, demote it
|
|
|
|
// back into a dot-old
|
|
|
|
if (PromotedToDotNew) {
|
|
|
|
DemoteToDotOld(MI);
|
|
|
|
}
|
|
|
|
reserveResourcesForConstExt(MI);
|
|
|
|
}
|
|
|
|
// In case that "MI" is not an extended insn,
|
|
|
|
// the resource availability has already been checked.
|
|
|
|
ResourceTracker->reserveResources(MI);
|
|
|
|
CurrentPacketMIs.push_back(MI);
|
|
|
|
}
|
|
|
|
return MII;
|
|
|
|
}
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Public Constructor Functions
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
FunctionPass *llvm::createHexagonPacketizer() {
|
|
|
|
return new HexagonPacketizer();
|
|
|
|
}
|
|
|
|
|