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llvm-project/llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll

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[RISCV] Add tests missed in r329871 llvm-svn: 329872
2018-04-12 13:36:44 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IFD %s
[RISCV] Implement RV64D codegen This patch: * Adds necessary RV64D codegen patterns * Modifies CC_RISCV so it will properly handle f64 types (with soft float ABI) Note that in general there is no reason to try to select fcvt.w[u].d rather than fcvt.l[u].d for i32 conversions because fptosi/fptoui produce poison if the input won't fit into the target type. Differential Revision: https://reviews.llvm.org/D53237 llvm-svn: 352833
2019-02-01 11:53:30 +08:00
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IFD %s
[RISCV] Add tests missed in r329871 llvm-svn: 329872
2018-04-12 13:36:44 +08:00
define double @func(double %d, i32 %n) nounwind {
; RV32IFD-LABEL: func:
; RV32IFD: # %bb.0: # %entry
; RV32IFD-NEXT: addi sp, sp, -32
; RV32IFD-NEXT: sw ra, 28(sp)
; RV32IFD-NEXT: sw a0, 16(sp)
; RV32IFD-NEXT: sw a1, 20(sp)
; RV32IFD-NEXT: fld ft0, 16(sp)
; RV32IFD-NEXT: beqz a2, .LBB0_2
; RV32IFD-NEXT: # %bb.1: # %if.else
; RV32IFD-NEXT: addi a2, a2, -1
; RV32IFD-NEXT: fsd ft0, 16(sp)
; RV32IFD-NEXT: lw a0, 16(sp)
; RV32IFD-NEXT: lw a1, 20(sp)
; RV32IFD-NEXT: fsd ft0, 8(sp)
[RISCV] Expand function call to "call" pseudoinstruction To do this: 1. Change GlobalAddress SDNode to TargetGlobalAddress to avoid legalizer split the symbol. 2. Change ExternalSymbol SDNode to TargetExternalSymbol to avoid legalizer split the symbol. 3. Let PseudoCALL match direct call with target operand TargetGlobalAddress and TargetExternalSymbol. Differential Revision: https://reviews.llvm.org/D44885 llvm-svn: 330827
2018-04-25 22:19:12 +08:00
; RV32IFD-NEXT: call func
[RISCV] Add tests missed in r329871 llvm-svn: 329872
2018-04-12 13:36:44 +08:00
; RV32IFD-NEXT: sw a0, 16(sp)
; RV32IFD-NEXT: sw a1, 20(sp)
; RV32IFD-NEXT: fld ft0, 16(sp)
; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: fadd.d ft0, ft0, ft1
; RV32IFD-NEXT: .LBB0_2: # %return
; RV32IFD-NEXT: fsd ft0, 16(sp)
; RV32IFD-NEXT: lw a0, 16(sp)
; RV32IFD-NEXT: lw a1, 20(sp)
; RV32IFD-NEXT: lw ra, 28(sp)
; RV32IFD-NEXT: addi sp, sp, 32
; RV32IFD-NEXT: ret
[RISCV] Implement RV64D codegen This patch: * Adds necessary RV64D codegen patterns * Modifies CC_RISCV so it will properly handle f64 types (with soft float ABI) Note that in general there is no reason to try to select fcvt.w[u].d rather than fcvt.l[u].d for i32 conversions because fptosi/fptoui produce poison if the input won't fit into the target type. Differential Revision: https://reviews.llvm.org/D53237 llvm-svn: 352833
2019-02-01 11:53:30 +08:00
;
; RV64IFD-LABEL: func:
; RV64IFD: # %bb.0: # %entry
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp)
; RV64IFD-NEXT: fmv.d.x ft0, a0
Revert Patch from Phabricator This reverts r372092 (git commit e38695a0255c9e7b53639f349f8101bae1ce5c04) llvm-svn: 372104
2019-09-17 18:52:09 +08:00
; RV64IFD-NEXT: slli a0, a1, 32
; RV64IFD-NEXT: srli a0, a0, 32
; RV64IFD-NEXT: beqz a0, .LBB0_2
[RISCV] Implement RV64D codegen This patch: * Adds necessary RV64D codegen patterns * Modifies CC_RISCV so it will properly handle f64 types (with soft float ABI) Note that in general there is no reason to try to select fcvt.w[u].d rather than fcvt.l[u].d for i32 conversions because fptosi/fptoui produce poison if the input won't fit into the target type. Differential Revision: https://reviews.llvm.org/D53237 llvm-svn: 352833
2019-02-01 11:53:30 +08:00
; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: addi a1, a1, -1
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: fsd ft0, 0(sp)
; RV64IFD-NEXT: call func
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fld ft1, 0(sp)
; RV64IFD-NEXT: fadd.d ft0, ft0, ft1
; RV64IFD-NEXT: .LBB0_2: # %return
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ld ra, 8(sp)
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
[RISCV] Add tests missed in r329871 llvm-svn: 329872
2018-04-12 13:36:44 +08:00
entry:
%cmp = icmp eq i32 %n, 0
br i1 %cmp, label %return, label %if.else
if.else:
%sub = add i32 %n, -1
%call = tail call double @func(double %d, i32 %sub)
%add = fadd double %call, %d
ret double %add
return:
ret double %d
}