2005-01-07 15:47:53 +08:00
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//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
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2005-04-22 06:36:52 +08:00
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//
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2005-01-07 15:47:53 +08:00
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// The LLVM Compiler Infrastructure
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//
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2007-12-30 04:36:04 +08:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-04-22 06:36:52 +08:00
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//
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2005-01-07 15:47:53 +08:00
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//===----------------------------------------------------------------------===//
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//
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// This implements the SelectionDAGISel class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "isel"
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2007-04-05 05:14:49 +08:00
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#include "llvm/ADT/BitVector.h"
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2006-10-17 04:52:31 +08:00
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#include "llvm/Analysis/AliasAnalysis.h"
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2005-01-07 15:47:53 +08:00
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#include "llvm/CodeGen/SelectionDAGISel.h"
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2006-01-21 10:32:06 +08:00
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#include "llvm/CodeGen/ScheduleDAG.h"
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2007-04-05 05:14:49 +08:00
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#include "llvm/Constants.h"
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2005-05-14 02:50:42 +08:00
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#include "llvm/CallingConv.h"
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2005-01-07 15:47:53 +08:00
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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2005-11-29 14:21:05 +08:00
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#include "llvm/GlobalVariable.h"
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2006-01-27 06:24:51 +08:00
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#include "llvm/InlineAsm.h"
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2005-01-07 15:47:53 +08:00
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#include "llvm/Instructions.h"
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#include "llvm/Intrinsics.h"
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2006-03-24 02:06:46 +08:00
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#include "llvm/IntrinsicInst.h"
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2007-04-09 14:17:21 +08:00
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#include "llvm/ParameterAttributes.h"
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2008-01-07 09:30:38 +08:00
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#include "llvm/CodeGen/Collector.h"
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2005-01-07 15:47:53 +08:00
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2007-12-31 12:13:23 +08:00
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#include "llvm/CodeGen/MachineJumpTableInfo.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2006-08-02 20:30:23 +08:00
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#include "llvm/CodeGen/SchedulerRegistry.h"
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2005-01-07 15:47:53 +08:00
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#include "llvm/CodeGen/SelectionDAG.h"
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2008-02-11 02:45:23 +08:00
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#include "llvm/Target/TargetRegisterInfo.h"
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2005-01-07 15:47:53 +08:00
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetMachine.h"
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2006-05-23 21:43:15 +08:00
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#include "llvm/Target/TargetOptions.h"
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2005-11-09 12:45:33 +08:00
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#include "llvm/Support/MathExtras.h"
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2005-01-07 15:47:53 +08:00
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#include "llvm/Support/Debug.h"
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2006-08-27 20:54:02 +08:00
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#include "llvm/Support/Compiler.h"
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2006-02-24 10:52:40 +08:00
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#include <algorithm>
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2005-01-07 15:47:53 +08:00
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using namespace llvm;
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2005-09-02 02:44:10 +08:00
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#ifndef NDEBUG
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2005-01-12 11:41:21 +08:00
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static cl::opt<bool>
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2006-01-21 10:32:06 +08:00
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ViewISelDAGs("view-isel-dags", cl::Hidden,
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cl::desc("Pop up a window to show isel dags as they are selected"));
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static cl::opt<bool>
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ViewSchedDAGs("view-sched-dags", cl::Hidden,
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cl::desc("Pop up a window to show sched dags as they are processed"));
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2007-08-29 04:32:58 +08:00
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static cl::opt<bool>
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ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
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2008-01-26 01:24:52 +08:00
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cl::desc("Pop up a window to show SUnit dags after they are processed"));
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2005-01-12 11:41:21 +08:00
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#else
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2007-08-29 04:32:58 +08:00
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static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0, ViewSUnitDAGs = 0;
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2005-01-12 11:41:21 +08:00
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#endif
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2006-08-02 20:30:23 +08:00
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//===---------------------------------------------------------------------===//
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///
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/// RegisterScheduler class - Track the registration of instruction schedulers.
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///
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//===---------------------------------------------------------------------===//
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MachinePassRegistry RegisterScheduler::Registry;
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//===---------------------------------------------------------------------===//
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///
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/// ISHeuristic command line option for instruction schedulers.
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///
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//===---------------------------------------------------------------------===//
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2008-05-13 08:00:25 +08:00
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static cl::opt<RegisterScheduler::FunctionPassCtor, false,
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RegisterPassParser<RegisterScheduler> >
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ISHeuristic("pre-RA-sched",
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cl::init(&createDefaultScheduler),
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cl::desc("Instruction schedulers available (before register"
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" allocation):"));
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2006-08-01 22:21:23 +08:00
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2008-05-13 08:00:25 +08:00
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static RegisterScheduler
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defaultListDAGScheduler("default", " Best scheduler for the target",
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createDefaultScheduler);
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2006-01-23 15:01:07 +08:00
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2008-02-26 10:33:44 +08:00
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namespace { struct SDISelAsmOperandInfo; }
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2007-05-01 01:29:31 +08:00
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2008-06-07 10:02:36 +08:00
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/// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
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/// insertvalue or extractvalue indices that identify a member, return
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/// the linearized index of the start of the member.
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///
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static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
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const unsigned *Indices,
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const unsigned *IndicesEnd,
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unsigned CurIndex = 0) {
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// Base case: We're done.
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if (Indices == IndicesEnd)
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return CurIndex;
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// Otherwise we need to recurse. A non-negative value is used to
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// indicate the final result value; a negative value carries the
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// complemented position to continue the search.
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CurIndex = ~CurIndex;
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// Given a struct type, recursively traverse the elements.
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if (const StructType *STy = dyn_cast<StructType>(Ty)) {
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for (StructType::element_iterator EI = STy->element_begin(),
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EE = STy->element_end();
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EI != EE; ++EI) {
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CurIndex = ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd,
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~CurIndex);
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if ((int)CurIndex >= 0)
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return CurIndex;
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}
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}
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// Given an array type, recursively traverse the elements.
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else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
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const Type *EltTy = ATy->getElementType();
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for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
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CurIndex = ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd,
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~CurIndex);
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if ((int)CurIndex >= 0)
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return CurIndex;
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}
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}
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// We haven't found the type we're looking for, so keep searching.
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return CurIndex;
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}
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2008-04-28 07:48:12 +08:00
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/// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
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2008-06-06 20:08:01 +08:00
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/// MVTs that represent all the individual underlying
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2008-04-28 07:48:12 +08:00
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/// non-aggregate types that comprise it.
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2008-06-07 10:02:36 +08:00
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///
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/// If Offsets is non-null, it points to a vector to be filled in
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/// with the in-memory offsets of each of the individual values.
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///
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2008-04-28 07:48:12 +08:00
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static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
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2008-06-07 10:02:36 +08:00
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SmallVectorImpl<MVT> &ValueVTs,
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SmallVectorImpl<uint64_t> *Offsets = 0,
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uint64_t StartingOffset = 0) {
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2008-04-28 07:48:12 +08:00
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// Given a struct type, recursively traverse the elements.
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if (const StructType *STy = dyn_cast<StructType>(Ty)) {
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2008-06-07 10:02:36 +08:00
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const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
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for (StructType::element_iterator EB = STy->element_begin(),
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EI = EB,
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EE = STy->element_end();
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EI != EE; ++EI)
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ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
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StartingOffset + SL->getElementOffset(EI - EB));
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2008-04-28 07:48:12 +08:00
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return;
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}
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// Given an array type, recursively traverse the elements.
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if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
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const Type *EltTy = ATy->getElementType();
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2008-06-07 10:02:36 +08:00
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uint64_t EltSize = TLI.getTargetData()->getABITypeSize(EltTy);
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2008-04-28 07:48:12 +08:00
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for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
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2008-06-07 10:02:36 +08:00
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ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
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StartingOffset + i * EltSize);
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2008-04-28 07:48:12 +08:00
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return;
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2008-04-26 02:27:55 +08:00
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}
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2008-06-06 20:08:01 +08:00
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// Base case: we can get an MVT for this LLVM IR type.
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2008-04-28 07:48:12 +08:00
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ValueVTs.push_back(TLI.getValueType(Ty));
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2008-06-07 10:02:36 +08:00
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if (Offsets)
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Offsets->push_back(StartingOffset);
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2008-04-28 07:48:12 +08:00
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}
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2008-04-26 02:27:55 +08:00
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2008-04-28 07:48:12 +08:00
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namespace {
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2008-04-29 02:10:39 +08:00
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/// RegsForValue - This struct represents the registers (physical or virtual)
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/// that a particular set of values is assigned, and the type information about
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/// the value. The most common situation is to represent one value at a time,
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/// but struct or array values are handled element-wise as multiple values.
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/// The splitting of aggregates is performed recursively, so that we never
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/// have aggregate-typed registers. The values at this point do not necessarily
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/// have legal types, so each value may require one or more registers of some
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/// legal type.
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///
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2006-06-29 07:17:24 +08:00
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struct VISIBILITY_HIDDEN RegsForValue {
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2008-04-26 02:27:55 +08:00
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/// TLI - The TargetLowering object.
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2008-04-29 02:10:39 +08:00
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///
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2008-04-26 02:27:55 +08:00
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const TargetLowering *TLI;
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2008-04-29 02:10:39 +08:00
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/// ValueVTs - The value types of the values, which may not be legal, and
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/// may need be promoted or synthesized from one or more registers.
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///
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2008-06-06 20:08:01 +08:00
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SmallVector<MVT, 4> ValueVTs;
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2006-02-23 06:37:12 +08:00
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2008-04-29 02:10:39 +08:00
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/// RegVTs - The value types of the registers. This is the same size as
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/// ValueVTs and it records, for each value, what the type of the assigned
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/// register or registers are. (Individual values are never synthesized
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/// from more than one type of register.)
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///
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/// With virtual registers, the contents of RegVTs is redundant with TLI's
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/// getRegisterType member function, however when with physical registers
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/// it is necessary to have a separate record of the types.
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2006-02-23 06:37:12 +08:00
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///
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2008-06-06 20:08:01 +08:00
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SmallVector<MVT, 4> RegVTs;
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2006-02-23 06:37:12 +08:00
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2008-04-29 02:10:39 +08:00
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/// Regs - This list holds the registers assigned to the values.
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/// Each legal or promoted value requires one register, and each
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/// expanded value requires multiple registers.
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///
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SmallVector<unsigned, 4> Regs;
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2006-02-23 06:37:12 +08:00
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2008-04-26 02:27:55 +08:00
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RegsForValue() : TLI(0) {}
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2006-02-23 06:37:12 +08:00
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2008-04-26 02:27:55 +08:00
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RegsForValue(const TargetLowering &tli,
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2008-04-28 14:44:42 +08:00
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const SmallVector<unsigned, 4> ®s,
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2008-06-06 20:08:01 +08:00
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MVT regvt, MVT valuevt)
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2008-04-29 02:10:39 +08:00
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: TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
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2008-04-26 02:27:55 +08:00
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RegsForValue(const TargetLowering &tli,
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2008-04-28 14:44:42 +08:00
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const SmallVector<unsigned, 4> ®s,
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2008-06-06 20:08:01 +08:00
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const SmallVector<MVT, 4> ®vts,
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const SmallVector<MVT, 4> &valuevts)
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2008-04-29 02:10:39 +08:00
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: TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
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2008-04-26 02:27:55 +08:00
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RegsForValue(const TargetLowering &tli,
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unsigned Reg, const Type *Ty) : TLI(&tli) {
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ComputeValueVTs(tli, Ty, ValueVTs);
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2008-04-29 01:42:03 +08:00
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for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
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2008-06-06 20:08:01 +08:00
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MVT ValueVT = ValueVTs[Value];
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2008-04-26 02:27:55 +08:00
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unsigned NumRegs = TLI->getNumRegisters(ValueVT);
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2008-06-06 20:08:01 +08:00
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MVT RegisterVT = TLI->getRegisterType(ValueVT);
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2008-04-26 02:27:55 +08:00
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for (unsigned i = 0; i != NumRegs; ++i)
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Regs.push_back(Reg + i);
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RegVTs.push_back(RegisterVT);
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Reg += NumRegs;
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}
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2006-02-23 06:37:12 +08:00
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}
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2008-04-29 12:29:54 +08:00
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/// append - Add the specified values to this one.
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void append(const RegsForValue &RHS) {
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TLI = RHS.TLI;
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ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
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RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
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Regs.append(RHS.Regs.begin(), RHS.Regs.end());
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}
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2006-02-23 06:37:12 +08:00
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/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
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2008-04-26 02:27:55 +08:00
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/// this value and returns the result as a ValueVTs value. This uses
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2006-02-23 06:37:12 +08:00
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/// Chain/Flag as the input and updates them for the output Chain/Flag.
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2007-06-29 07:29:44 +08:00
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/// If the Flag pointer is NULL, no flag is used.
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2006-02-23 06:37:12 +08:00
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SDOperand getCopyFromRegs(SelectionDAG &DAG,
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2007-06-29 07:29:44 +08:00
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SDOperand &Chain, SDOperand *Flag) const;
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2006-02-24 03:21:04 +08:00
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/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
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/// specified value into the registers specified by this object. This uses
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/// Chain/Flag as the input and updates them for the output Chain/Flag.
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2007-06-29 07:29:44 +08:00
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/// If the Flag pointer is NULL, no flag is used.
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2006-02-24 03:21:04 +08:00
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void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
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2007-06-29 07:29:44 +08:00
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SDOperand &Chain, SDOperand *Flag) const;
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2006-02-24 03:21:04 +08:00
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/// AddInlineAsmOperands - Add this value to the specified inlineasm node
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/// operand list. This adds the code marker and includes the number of
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/// values added into it.
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void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
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2006-02-24 04:06:57 +08:00
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std::vector<SDOperand> &Ops) const;
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2006-02-23 06:37:12 +08:00
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};
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}
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2006-01-23 15:01:07 +08:00
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2005-01-07 15:47:53 +08:00
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namespace llvm {
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2006-08-02 03:14:14 +08:00
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//===--------------------------------------------------------------------===//
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|
|
|
/// createDefaultScheduler - This creates an instruction scheduler appropriate
|
|
|
|
/// for the target.
|
|
|
|
ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
|
|
|
|
SelectionDAG *DAG,
|
|
|
|
MachineBasicBlock *BB) {
|
|
|
|
TargetLowering &TLI = IS->getTargetLowering();
|
|
|
|
|
|
|
|
if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
|
|
|
|
return createTDListDAGScheduler(IS, DAG, BB);
|
|
|
|
} else {
|
|
|
|
assert(TLI.getSchedulingPreference() ==
|
|
|
|
TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
|
|
|
|
return createBURRListDAGScheduler(IS, DAG, BB);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2005-01-07 15:47:53 +08:00
|
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
/// FunctionLoweringInfo - This contains information that is global to a
|
|
|
|
/// function that is used when lowering a region of the function.
|
2005-01-09 03:52:31 +08:00
|
|
|
class FunctionLoweringInfo {
|
|
|
|
public:
|
2005-01-07 15:47:53 +08:00
|
|
|
TargetLowering &TLI;
|
|
|
|
Function &Fn;
|
|
|
|
MachineFunction &MF;
|
2007-12-31 12:13:23 +08:00
|
|
|
MachineRegisterInfo &RegInfo;
|
2005-01-07 15:47:53 +08:00
|
|
|
|
|
|
|
FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
|
|
|
|
|
|
|
|
/// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
|
|
|
|
std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
|
|
|
|
|
|
|
|
/// ValueMap - Since we emit code for the function a basic block at a time,
|
|
|
|
/// we must remember which virtual registers hold the values for
|
|
|
|
/// cross-basic-block values.
|
2007-02-04 09:35:11 +08:00
|
|
|
DenseMap<const Value*, unsigned> ValueMap;
|
2005-01-07 15:47:53 +08:00
|
|
|
|
|
|
|
/// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
|
|
|
|
/// the entry block. This allows the allocas to be efficiently referenced
|
|
|
|
/// anywhere in the function.
|
|
|
|
std::map<const AllocaInst*, int> StaticAllocaMap;
|
|
|
|
|
2007-06-16 03:04:19 +08:00
|
|
|
#ifndef NDEBUG
|
|
|
|
SmallSet<Instruction*, 8> CatchInfoLost;
|
|
|
|
SmallSet<Instruction*, 8> CatchInfoFound;
|
|
|
|
#endif
|
|
|
|
|
2008-06-06 20:08:01 +08:00
|
|
|
unsigned MakeReg(MVT VT) {
|
2007-12-31 12:13:23 +08:00
|
|
|
return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT));
|
2005-01-07 15:47:53 +08:00
|
|
|
}
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
llvm-svn: 31230
2006-10-28 05:36:01 +08:00
|
|
|
|
|
|
|
/// isExportedInst - Return true if the specified value is an instruction
|
|
|
|
/// exported from its block.
|
|
|
|
bool isExportedInst(const Value *V) {
|
|
|
|
return ValueMap.count(V);
|
|
|
|
}
|
2005-04-22 06:36:52 +08:00
|
|
|
|
2006-03-17 03:51:18 +08:00
|
|
|
unsigned CreateRegForValue(const Value *V);
|
|
|
|
|
2005-01-07 15:47:53 +08:00
|
|
|
unsigned InitializeRegForValue(const Value *V) {
|
|
|
|
unsigned &R = ValueMap[V];
|
|
|
|
assert(R == 0 && "Already initialized this value register!");
|
|
|
|
return R = CreateRegForValue(V);
|
|
|
|
}
|
|
|
|
};
|
|
|
|
}
|
|
|
|
|
2007-07-05 04:52:51 +08:00
|
|
|
/// isSelector - Return true if this instruction is a call to the
|
|
|
|
/// eh.selector intrinsic.
|
|
|
|
static bool isSelector(Instruction *I) {
|
2007-06-16 03:04:19 +08:00
|
|
|
if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
|
2007-09-07 19:39:35 +08:00
|
|
|
return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 ||
|
|
|
|
II->getIntrinsicID() == Intrinsic::eh_selector_i64);
|
2007-06-16 03:04:19 +08:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2005-01-07 15:47:53 +08:00
|
|
|
/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
|
2006-03-27 09:32:24 +08:00
|
|
|
/// PHI nodes or outside of the basic block that defines it, or used by a
|
2008-02-21 14:45:13 +08:00
|
|
|
/// switch or atomic instruction, which may expand to multiple basic blocks.
|
2005-01-07 15:47:53 +08:00
|
|
|
static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
|
|
|
|
if (isa<PHINode>(I)) return true;
|
|
|
|
BasicBlock *BB = I->getParent();
|
|
|
|
for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
|
2006-03-27 09:32:24 +08:00
|
|
|
if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
llvm-svn: 31230
2006-10-28 05:36:01 +08:00
|
|
|
// FIXME: Remove switchinst special case.
|
2006-03-27 09:32:24 +08:00
|
|
|
isa<SwitchInst>(*UI))
|
2005-01-07 15:47:53 +08:00
|
|
|
return true;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
Significantly simplify this code and make it more aggressive. Instead of having
a special case hack for X86, make the hack more general: if an incoming argument
register is not used in any block other than the entry block, don't copy it to
a vreg. This helps us compile code like this:
%struct.foo = type { int, int, [0 x ubyte] }
int %test(%struct.foo* %X) {
%tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
%tmp = load ubyte* %tmp1 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
lbz r3, 108(r3)
blr
instead of:
_test:
lbz r2, 108(r3)
or r3, r2, r2
blr
The (dead) copy emitted to copy r3 into a vreg for extra-block uses was
increasing the live range of r3 past the load, preventing the coallescing.
This implements CodeGen/PowerPC/reg-coallesce-simple.ll
llvm-svn: 24115
2005-10-31 03:42:35 +08:00
|
|
|
/// isOnlyUsedInEntryBlock - If the specified argument is only used in the
|
2006-03-27 09:32:24 +08:00
|
|
|
/// entry block, return true. This includes arguments used by switches, since
|
|
|
|
/// the switch may expand into multiple basic blocks.
|
Significantly simplify this code and make it more aggressive. Instead of having
a special case hack for X86, make the hack more general: if an incoming argument
register is not used in any block other than the entry block, don't copy it to
a vreg. This helps us compile code like this:
%struct.foo = type { int, int, [0 x ubyte] }
int %test(%struct.foo* %X) {
%tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
%tmp = load ubyte* %tmp1 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
lbz r3, 108(r3)
blr
instead of:
_test:
lbz r2, 108(r3)
or r3, r2, r2
blr
The (dead) copy emitted to copy r3 into a vreg for extra-block uses was
increasing the live range of r3 past the load, preventing the coallescing.
This implements CodeGen/PowerPC/reg-coallesce-simple.ll
llvm-svn: 24115
2005-10-31 03:42:35 +08:00
|
|
|
static bool isOnlyUsedInEntryBlock(Argument *A) {
|
|
|
|
BasicBlock *Entry = A->getParent()->begin();
|
|
|
|
for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
|
2006-03-27 09:32:24 +08:00
|
|
|
if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
|
Significantly simplify this code and make it more aggressive. Instead of having
a special case hack for X86, make the hack more general: if an incoming argument
register is not used in any block other than the entry block, don't copy it to
a vreg. This helps us compile code like this:
%struct.foo = type { int, int, [0 x ubyte] }
int %test(%struct.foo* %X) {
%tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
%tmp = load ubyte* %tmp1 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
lbz r3, 108(r3)
blr
instead of:
_test:
lbz r2, 108(r3)
or r3, r2, r2
blr
The (dead) copy emitted to copy r3 into a vreg for extra-block uses was
increasing the live range of r3 past the load, preventing the coallescing.
This implements CodeGen/PowerPC/reg-coallesce-simple.ll
llvm-svn: 24115
2005-10-31 03:42:35 +08:00
|
|
|
return false; // Use not in entry block.
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2005-01-07 15:47:53 +08:00
|
|
|
FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
|
2005-04-22 06:36:52 +08:00
|
|
|
Function &fn, MachineFunction &mf)
|
2007-12-31 12:13:23 +08:00
|
|
|
: TLI(tli), Fn(fn), MF(mf), RegInfo(MF.getRegInfo()) {
|
2005-01-07 15:47:53 +08:00
|
|
|
|
Significantly simplify this code and make it more aggressive. Instead of having
a special case hack for X86, make the hack more general: if an incoming argument
register is not used in any block other than the entry block, don't copy it to
a vreg. This helps us compile code like this:
%struct.foo = type { int, int, [0 x ubyte] }
int %test(%struct.foo* %X) {
%tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
%tmp = load ubyte* %tmp1 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
lbz r3, 108(r3)
blr
instead of:
_test:
lbz r2, 108(r3)
or r3, r2, r2
blr
The (dead) copy emitted to copy r3 into a vreg for extra-block uses was
increasing the live range of r3 past the load, preventing the coallescing.
This implements CodeGen/PowerPC/reg-coallesce-simple.ll
llvm-svn: 24115
2005-10-31 03:42:35 +08:00
|
|
|
// Create a vreg for each argument register that is not dead and is used
|
|
|
|
// outside of the entry block for the function.
|
2005-05-12 02:57:06 +08:00
|
|
|
for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
|
|
|
|
AI != E; ++AI)
|
Significantly simplify this code and make it more aggressive. Instead of having
a special case hack for X86, make the hack more general: if an incoming argument
register is not used in any block other than the entry block, don't copy it to
a vreg. This helps us compile code like this:
%struct.foo = type { int, int, [0 x ubyte] }
int %test(%struct.foo* %X) {
%tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
%tmp = load ubyte* %tmp1 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
lbz r3, 108(r3)
blr
instead of:
_test:
lbz r2, 108(r3)
or r3, r2, r2
blr
The (dead) copy emitted to copy r3 into a vreg for extra-block uses was
increasing the live range of r3 past the load, preventing the coallescing.
This implements CodeGen/PowerPC/reg-coallesce-simple.ll
llvm-svn: 24115
2005-10-31 03:42:35 +08:00
|
|
|
if (!isOnlyUsedInEntryBlock(AI))
|
|
|
|
InitializeRegForValue(AI);
|
2005-01-07 15:47:53 +08:00
|
|
|
|
Significantly simplify this code and make it more aggressive. Instead of having
a special case hack for X86, make the hack more general: if an incoming argument
register is not used in any block other than the entry block, don't copy it to
a vreg. This helps us compile code like this:
%struct.foo = type { int, int, [0 x ubyte] }
int %test(%struct.foo* %X) {
%tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
%tmp = load ubyte* %tmp1 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
lbz r3, 108(r3)
blr
instead of:
_test:
lbz r2, 108(r3)
or r3, r2, r2
blr
The (dead) copy emitted to copy r3 into a vreg for extra-block uses was
increasing the live range of r3 past the load, preventing the coallescing.
This implements CodeGen/PowerPC/reg-coallesce-simple.ll
llvm-svn: 24115
2005-10-31 03:42:35 +08:00
|
|
|
// Initialize the mapping of values to registers. This is only set up for
|
|
|
|
// instruction values that are used outside of the block that defines
|
|
|
|
// them.
|
2005-10-01 11:57:14 +08:00
|
|
|
Function::iterator BB = Fn.begin(), EB = Fn.end();
|
2005-01-07 15:47:53 +08:00
|
|
|
for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
|
|
|
|
if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
|
2006-10-20 15:07:24 +08:00
|
|
|
if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
|
2005-01-07 15:47:53 +08:00
|
|
|
const Type *Ty = AI->getAllocatedType();
|
Executive summary: getTypeSize -> getTypeStoreSize / getABITypeSize.
The meaning of getTypeSize was not clear - clarifying it is important
now that we have x86 long double and arbitrary precision integers.
The issue with long double is that it requires 80 bits, and this is
not a multiple of its alignment. This gives a primitive type for
which getTypeSize differed from getABITypeSize. For arbitrary precision
integers it is even worse: there is the minimum number of bits needed to
hold the type (eg: 36 for an i36), the maximum number of bits that will
be overwriten when storing the type (40 bits for i36) and the ABI size
(i.e. the storage size rounded up to a multiple of the alignment; 64 bits
for i36).
This patch removes getTypeSize (not really - it is still there but
deprecated to allow for a gradual transition). Instead there is:
(1) getTypeSizeInBits - a number of bits that suffices to hold all
values of the type. For a primitive type, this is the minimum number
of bits. For an i36 this is 36 bits. For x86 long double it is 80.
This corresponds to gcc's TYPE_PRECISION.
(2) getTypeStoreSizeInBits - the maximum number of bits that is
written when storing the type (or read when reading it). For an
i36 this is 40 bits, for an x86 long double it is 80 bits. This
is the size alias analysis is interested in (getTypeStoreSize
returns the number of bytes). There doesn't seem to be anything
corresponding to this in gcc.
(3) getABITypeSizeInBits - this is getTypeStoreSizeInBits rounded
up to a multiple of the alignment. For an i36 this is 64, for an
x86 long double this is 96 or 128 depending on the OS. This is the
spacing between consecutive elements when you form an array out of
this type (getABITypeSize returns the number of bytes). This is
TYPE_SIZE in gcc.
Since successive elements in a SequentialType (arrays, pointers
and vectors) need to be aligned, the spacing between them will be
given by getABITypeSize. This means that the size of an array
is the length times the getABITypeSize. It also means that GEP
computations need to use getABITypeSize when computing offsets.
Furthermore, if an alloca allocates several elements at once then
these too need to be aligned, so the size of the alloca has to be
the number of elements multiplied by getABITypeSize. Logically
speaking this doesn't have to be the case when allocating just
one element, but it is simpler to also use getABITypeSize in this
case. So alloca's and mallocs should use getABITypeSize. Finally,
since gcc's only notion of size is that given by getABITypeSize, if
you want to output assembler etc the same as gcc then getABITypeSize
is the size you want.
Since a store will overwrite no more than getTypeStoreSize bytes,
and a read will read no more than that many bytes, this is the
notion of size appropriate for alias analysis calculations.
In this patch I have corrected all type size uses except some of
those in ScalarReplAggregates, lib/Codegen, lib/Target (the hard
cases). I will get around to auditing these too at some point,
but I could do with some help.
Finally, I made one change which I think wise but others might
consider pointless and suboptimal: in an unpacked struct the
amount of space allocated for a field is now given by the ABI
size rather than getTypeStoreSize. I did this because every
other place that reserves memory for a type (eg: alloca) now
uses getABITypeSize, and I didn't want to make an exception
for unpacked structs, i.e. I did it to make things more uniform.
This only effects structs containing long doubles and arbitrary
precision integers. If someone wants to pack these types more
tightly they can always use a packed struct.
llvm-svn: 43620
2007-11-02 04:53:16 +08:00
|
|
|
uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
|
2005-11-06 17:00:38 +08:00
|
|
|
unsigned Align =
|
2007-02-14 13:52:17 +08:00
|
|
|
std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
|
2005-11-06 17:00:38 +08:00
|
|
|
AI->getAlignment());
|
2005-05-14 07:14:17 +08:00
|
|
|
|
2006-10-20 15:07:24 +08:00
|
|
|
TySize *= CUI->getZExtValue(); // Get total allocated size.
|
2005-10-19 06:14:06 +08:00
|
|
|
if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
|
2005-01-07 15:47:53 +08:00
|
|
|
StaticAllocaMap[AI] =
|
2007-04-25 12:08:28 +08:00
|
|
|
MF.getFrameInfo()->CreateStackObject(TySize, Align);
|
2005-01-07 15:47:53 +08:00
|
|
|
}
|
|
|
|
|
2005-10-01 11:57:14 +08:00
|
|
|
for (; BB != EB; ++BB)
|
|
|
|
for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
|
2005-01-07 15:47:53 +08:00
|
|
|
if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
|
|
|
|
if (!isa<AllocaInst>(I) ||
|
|
|
|
!StaticAllocaMap.count(cast<AllocaInst>(I)))
|
|
|
|
InitializeRegForValue(I);
|
|
|
|
|
|
|
|
// Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
|
|
|
|
// also creates the initial PHI MachineInstrs, though none of the input
|
|
|
|
// operands are populated.
|
2005-10-01 11:57:14 +08:00
|
|
|
for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
|
2005-01-07 15:47:53 +08:00
|
|
|
MachineBasicBlock *MBB = new MachineBasicBlock(BB);
|
|
|
|
MBBMap[BB] = MBB;
|
|
|
|
MF.getBasicBlockList().push_back(MBB);
|
|
|
|
|
|
|
|
// Create Machine PHI nodes for LLVM PHI nodes, lowering them as
|
|
|
|
// appropriate.
|
|
|
|
PHINode *PN;
|
2006-10-28 07:50:33 +08:00
|
|
|
for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
|
|
|
|
if (PN->use_empty()) continue;
|
|
|
|
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT VT = TLI.getValueType(PN->getType());
|
2007-06-26 00:23:39 +08:00
|
|
|
unsigned NumRegisters = TLI.getNumRegisters(VT);
|
2006-10-28 07:50:33 +08:00
|
|
|
unsigned PHIReg = ValueMap[PN];
|
|
|
|
assert(PHIReg && "PHI node does not have an assigned virtual register!");
|
2006-11-28 07:37:22 +08:00
|
|
|
const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
|
2007-06-21 22:42:22 +08:00
|
|
|
for (unsigned i = 0; i != NumRegisters; ++i)
|
2006-11-28 07:37:22 +08:00
|
|
|
BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
|
2006-10-28 07:50:33 +08:00
|
|
|
}
|
2005-01-07 15:47:53 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-03-17 03:51:18 +08:00
|
|
|
/// CreateRegForValue - Allocate the appropriate number of virtual registers of
|
|
|
|
/// the correctly promoted or expanded types. Assign these registers
|
|
|
|
/// consecutive vreg numbers and return the first assigned number.
|
2008-04-29 02:19:43 +08:00
|
|
|
///
|
|
|
|
/// In the case that the given value has struct or array type, this function
|
|
|
|
/// will assign registers for each member or element.
|
|
|
|
///
|
2006-03-17 03:51:18 +08:00
|
|
|
unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
|
2008-06-06 20:08:01 +08:00
|
|
|
SmallVector<MVT, 4> ValueVTs;
|
2008-04-28 14:44:42 +08:00
|
|
|
ComputeValueVTs(TLI, V->getType(), ValueVTs);
|
2007-04-25 05:13:23 +08:00
|
|
|
|
2008-04-26 02:27:55 +08:00
|
|
|
unsigned FirstReg = 0;
|
2008-04-29 01:42:03 +08:00
|
|
|
for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT ValueVT = ValueVTs[Value];
|
|
|
|
MVT RegisterVT = TLI.getRegisterType(ValueVT);
|
2007-06-27 22:34:07 +08:00
|
|
|
|
2008-04-28 14:44:42 +08:00
|
|
|
unsigned NumRegs = TLI.getNumRegisters(ValueVT);
|
2008-04-26 02:27:55 +08:00
|
|
|
for (unsigned i = 0; i != NumRegs; ++i) {
|
|
|
|
unsigned R = MakeReg(RegisterVT);
|
|
|
|
if (!FirstReg) FirstReg = R;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return FirstReg;
|
2006-03-17 03:51:18 +08:00
|
|
|
}
|
2005-01-07 15:47:53 +08:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// SelectionDAGLowering - This is the common target-independent lowering
|
|
|
|
/// implementation that is parameterized by a TargetLowering object.
|
|
|
|
/// Also, targets can overload any lowering method.
|
|
|
|
///
|
|
|
|
namespace llvm {
|
|
|
|
class SelectionDAGLowering {
|
|
|
|
MachineBasicBlock *CurMBB;
|
|
|
|
|
2007-02-04 09:31:47 +08:00
|
|
|
DenseMap<const Value*, SDOperand> NodeMap;
|
2005-01-07 15:47:53 +08:00
|
|
|
|
2005-01-18 06:19:26 +08:00
|
|
|
/// PendingLoads - Loads are not emitted to the program immediately. We bunch
|
|
|
|
/// them up and then emit token factor nodes when possible. This allows us to
|
|
|
|
/// get simple disambiguation between loads without worrying about alias
|
|
|
|
/// analysis.
|
|
|
|
std::vector<SDOperand> PendingLoads;
|
|
|
|
|
2008-03-28 03:56:19 +08:00
|
|
|
/// PendingExports - CopyToReg nodes that copy values to virtual registers
|
|
|
|
/// for export to other blocks need to be emitted before any terminator
|
|
|
|
/// instruction, but they have no other ordering requirements. We bunch them
|
|
|
|
/// up and the emit a single tokenfactor for them just before terminator
|
|
|
|
/// instructions.
|
|
|
|
std::vector<SDOperand> PendingExports;
|
|
|
|
|
2007-04-05 05:14:49 +08:00
|
|
|
/// Case - A struct to record the Value for a switch case, and the
|
|
|
|
/// case's target basic block.
|
|
|
|
struct Case {
|
|
|
|
Constant* Low;
|
|
|
|
Constant* High;
|
|
|
|
MachineBasicBlock* BB;
|
|
|
|
|
|
|
|
Case() : Low(0), High(0), BB(0) { }
|
|
|
|
Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
|
|
|
|
Low(low), High(high), BB(bb) { }
|
|
|
|
uint64_t size() const {
|
|
|
|
uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
|
|
|
|
uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue();
|
|
|
|
return (rHigh - rLow + 1ULL);
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2007-04-09 20:31:58 +08:00
|
|
|
struct CaseBits {
|
|
|
|
uint64_t Mask;
|
|
|
|
MachineBasicBlock* BB;
|
|
|
|
unsigned Bits;
|
|
|
|
|
|
|
|
CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
|
|
|
|
Mask(mask), BB(bb), Bits(bits) { }
|
|
|
|
};
|
|
|
|
|
2007-04-05 05:14:49 +08:00
|
|
|
typedef std::vector<Case> CaseVector;
|
2007-04-09 20:31:58 +08:00
|
|
|
typedef std::vector<CaseBits> CaseBitsVector;
|
2007-04-05 05:14:49 +08:00
|
|
|
typedef CaseVector::iterator CaseItr;
|
|
|
|
typedef std::pair<CaseItr, CaseItr> CaseRange;
|
2006-03-27 09:32:24 +08:00
|
|
|
|
|
|
|
/// CaseRec - A struct with ctor used in lowering switches to a binary tree
|
|
|
|
/// of conditional branches.
|
|
|
|
struct CaseRec {
|
|
|
|
CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
|
|
|
|
CaseBB(bb), LT(lt), GE(ge), Range(r) {}
|
|
|
|
|
|
|
|
/// CaseBB - The MBB in which to emit the compare and branch
|
|
|
|
MachineBasicBlock *CaseBB;
|
|
|
|
/// LT, GE - If nonzero, we know the current case value must be less-than or
|
|
|
|
/// greater-than-or-equal-to these Constants.
|
|
|
|
Constant *LT;
|
|
|
|
Constant *GE;
|
|
|
|
/// Range - A pair of iterators representing the range of case values to be
|
|
|
|
/// processed at this point in the binary search tree.
|
|
|
|
CaseRange Range;
|
|
|
|
};
|
2007-03-27 19:29:11 +08:00
|
|
|
|
|
|
|
typedef std::vector<CaseRec> CaseRecVector;
|
2007-04-05 05:14:49 +08:00
|
|
|
|
|
|
|
/// The comparison function for sorting the switch case values in the vector.
|
|
|
|
/// WARNING: Case ranges should be disjoint!
|
2006-03-27 09:32:24 +08:00
|
|
|
struct CaseCmp {
|
2007-04-09 20:31:58 +08:00
|
|
|
bool operator () (const Case& C1, const Case& C2) {
|
2007-04-05 05:14:49 +08:00
|
|
|
assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
|
|
|
|
const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
|
|
|
|
const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
|
|
|
|
return CI1->getValue().slt(CI2->getValue());
|
2006-03-27 09:32:24 +08:00
|
|
|
}
|
|
|
|
};
|
2007-04-05 05:14:49 +08:00
|
|
|
|
2007-04-09 20:31:58 +08:00
|
|
|
struct CaseBitsCmp {
|
|
|
|
bool operator () (const CaseBits& C1, const CaseBits& C2) {
|
|
|
|
return C1.Bits > C2.Bits;
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2007-04-05 05:14:49 +08:00
|
|
|
unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
|
2006-03-27 09:32:24 +08:00
|
|
|
|
2005-01-07 15:47:53 +08:00
|
|
|
public:
|
|
|
|
// TLI - This is information that describes the available target features we
|
|
|
|
// need for lowering. This indicates when operations are unavailable,
|
|
|
|
// implemented with a libcall, etc.
|
|
|
|
TargetLowering &TLI;
|
|
|
|
SelectionDAG &DAG;
|
2006-05-03 09:29:57 +08:00
|
|
|
const TargetData *TD;
|
2007-08-28 00:26:13 +08:00
|
|
|
AliasAnalysis &AA;
|
2005-01-07 15:47:53 +08:00
|
|
|
|
2006-03-27 09:32:24 +08:00
|
|
|
/// SwitchCases - Vector of CaseBlock structures used to communicate
|
|
|
|
/// SwitchInst code generation information.
|
|
|
|
std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
|
2007-03-25 23:07:15 +08:00
|
|
|
/// JTCases - Vector of JumpTable structures used to communicate
|
|
|
|
/// SwitchInst code generation information.
|
|
|
|
std::vector<SelectionDAGISel::JumpTableBlock> JTCases;
|
2007-04-09 20:31:58 +08:00
|
|
|
std::vector<SelectionDAGISel::BitTestBlock> BitTestCases;
|
2006-03-27 09:32:24 +08:00
|
|
|
|
2005-01-07 15:47:53 +08:00
|
|
|
/// FuncInfo - Information about the function as a whole.
|
|
|
|
///
|
|
|
|
FunctionLoweringInfo &FuncInfo;
|
2008-01-07 09:30:38 +08:00
|
|
|
|
|
|
|
/// GCI - Garbage collection metadata for the function.
|
|
|
|
CollectorMetadata *GCI;
|
2005-01-07 15:47:53 +08:00
|
|
|
|
|
|
|
SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
|
2007-08-28 00:26:13 +08:00
|
|
|
AliasAnalysis &aa,
|
2008-01-07 09:30:38 +08:00
|
|
|
FunctionLoweringInfo &funcinfo,
|
|
|
|
CollectorMetadata *gci)
|
2007-08-28 00:26:13 +08:00
|
|
|
: TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa),
|
2008-01-07 09:30:38 +08:00
|
|
|
FuncInfo(funcinfo), GCI(gci) {
|
2005-01-07 15:47:53 +08:00
|
|
|
}
|
|
|
|
|
2008-03-28 03:56:19 +08:00
|
|
|
/// getRoot - Return the current virtual root of the Selection DAG,
|
|
|
|
/// flushing any PendingLoad items. This must be done before emitting
|
|
|
|
/// a store or any other node that may need to be ordered after any
|
|
|
|
/// prior load instructions.
|
2005-01-18 03:43:36 +08:00
|
|
|
///
|
|
|
|
SDOperand getRoot() {
|
2005-01-18 06:19:26 +08:00
|
|
|
if (PendingLoads.empty())
|
|
|
|
return DAG.getRoot();
|
2005-04-22 06:36:52 +08:00
|
|
|
|
2005-01-18 06:19:26 +08:00
|
|
|
if (PendingLoads.size() == 1) {
|
|
|
|
SDOperand Root = PendingLoads[0];
|
|
|
|
DAG.setRoot(Root);
|
|
|
|
PendingLoads.clear();
|
|
|
|
return Root;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Otherwise, we have to make a token factor node.
|
2006-08-08 10:23:42 +08:00
|
|
|
SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
|
|
|
|
&PendingLoads[0], PendingLoads.size());
|
2005-01-18 06:19:26 +08:00
|
|
|
PendingLoads.clear();
|
|
|
|
DAG.setRoot(Root);
|
|
|
|
return Root;
|
2005-01-18 03:43:36 +08:00
|
|
|
}
|
|
|
|
|
2008-03-28 03:56:19 +08:00
|
|
|
/// getControlRoot - Similar to getRoot, but instead of flushing all the
|
|
|
|
/// PendingLoad items, flush all the PendingExports items. It is necessary
|
|
|
|
/// to do this before emitting a terminator instruction.
|
|
|
|
///
|
|
|
|
SDOperand getControlRoot() {
|
|
|
|
SDOperand Root = DAG.getRoot();
|
|
|
|
|
|
|
|
if (PendingExports.empty())
|
|
|
|
return Root;
|
|
|
|
|
|
|
|
// Turn all of the CopyToReg chains into one factored node.
|
|
|
|
if (Root.getOpcode() != ISD::EntryToken) {
|
|
|
|
unsigned i = 0, e = PendingExports.size();
|
|
|
|
for (; i != e; ++i) {
|
|
|
|
assert(PendingExports[i].Val->getNumOperands() > 1);
|
|
|
|
if (PendingExports[i].Val->getOperand(0) == Root)
|
|
|
|
break; // Don't add the root if we already indirectly depend on it.
|
|
|
|
}
|
|
|
|
|
|
|
|
if (i == e)
|
|
|
|
PendingExports.push_back(Root);
|
|
|
|
}
|
|
|
|
|
|
|
|
Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
|
|
|
|
&PendingExports[0],
|
|
|
|
PendingExports.size());
|
|
|
|
PendingExports.clear();
|
|
|
|
DAG.setRoot(Root);
|
|
|
|
return Root;
|
|
|
|
}
|
|
|
|
|
|
|
|
void CopyValueToVirtualRegister(Value *V, unsigned Reg);
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
llvm-svn: 31230
2006-10-28 05:36:01 +08:00
|
|
|
|
2005-01-07 15:47:53 +08:00
|
|
|
void visit(Instruction &I) { visit(I.getOpcode(), I); }
|
|
|
|
|
|
|
|
void visit(unsigned Opcode, User &I) {
|
2006-11-10 12:41:34 +08:00
|
|
|
// Note: this doesn't use InstVisitor, because it has to work with
|
|
|
|
// ConstantExpr's in addition to instructions.
|
2005-01-07 15:47:53 +08:00
|
|
|
switch (Opcode) {
|
|
|
|
default: assert(0 && "Unknown instruction type encountered!");
|
|
|
|
abort();
|
|
|
|
// Build the switch statement using the Instruction.def file.
|
|
|
|
#define HANDLE_INST(NUM, OPCODE, CLASS) \
|
|
|
|
case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
|
|
|
|
#include "llvm/Instruction.def"
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
|
|
|
|
|
2006-03-16 06:19:46 +08:00
|
|
|
SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
|
2006-10-10 04:57:25 +08:00
|
|
|
const Value *SV, SDOperand Root,
|
2007-04-23 07:15:30 +08:00
|
|
|
bool isVolatile, unsigned Alignment);
|
2005-01-07 15:47:53 +08:00
|
|
|
|
2006-03-17 03:57:50 +08:00
|
|
|
SDOperand getValue(const Value *V);
|
2005-01-07 15:47:53 +08:00
|
|
|
|
2007-02-04 09:31:47 +08:00
|
|
|
void setValue(const Value *V, SDOperand NewN) {
|
2005-01-07 15:47:53 +08:00
|
|
|
SDOperand &N = NodeMap[V];
|
|
|
|
assert(N.Val == 0 && "Already set a value for this node!");
|
2007-02-04 09:31:47 +08:00
|
|
|
N = NewN;
|
2005-01-07 15:47:53 +08:00
|
|
|
}
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
llvm-svn: 25878
2006-02-02 02:59:47 +08:00
|
|
|
|
2008-02-26 10:33:44 +08:00
|
|
|
void GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
|
2007-05-01 05:11:17 +08:00
|
|
|
std::set<unsigned> &OutputRegs,
|
|
|
|
std::set<unsigned> &InputRegs);
|
2006-03-27 09:32:24 +08:00
|
|
|
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
llvm-svn: 31230
2006-10-28 05:36:01 +08:00
|
|
|
void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
|
|
|
|
MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
|
|
|
|
unsigned Opc);
|
2006-10-28 07:50:33 +08:00
|
|
|
bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
llvm-svn: 31230
2006-10-28 05:36:01 +08:00
|
|
|
void ExportFromCurrentBlock(Value *V);
|
2007-12-19 17:48:52 +08:00
|
|
|
void LowerCallTo(CallSite CS, SDOperand Callee, bool IsTailCall,
|
2007-05-23 19:08:31 +08:00
|
|
|
MachineBasicBlock *LandingPad = NULL);
|
2007-11-27 21:23:08 +08:00
|
|
|
|
2005-01-07 15:47:53 +08:00
|
|
|
// Terminator instructions.
|
|
|
|
void visitRet(ReturnInst &I);
|
|
|
|
void visitBr(BranchInst &I);
|
2006-03-27 09:32:24 +08:00
|
|
|
void visitSwitch(SwitchInst &I);
|
2005-01-07 15:47:53 +08:00
|
|
|
void visitUnreachable(UnreachableInst &I) { /* noop */ }
|
|
|
|
|
2007-03-27 19:29:11 +08:00
|
|
|
// Helpers for visitSwitch
|
2007-03-27 20:05:48 +08:00
|
|
|
bool handleSmallSwitchRange(CaseRec& CR,
|
2007-03-27 19:29:11 +08:00
|
|
|
CaseRecVector& WorkList,
|
|
|
|
Value* SV,
|
|
|
|
MachineBasicBlock* Default);
|
2007-03-27 20:05:48 +08:00
|
|
|
bool handleJTSwitchCase(CaseRec& CR,
|
2007-03-27 19:29:11 +08:00
|
|
|
CaseRecVector& WorkList,
|
|
|
|
Value* SV,
|
|
|
|
MachineBasicBlock* Default);
|
2007-03-27 20:05:48 +08:00
|
|
|
bool handleBTSplitSwitchCase(CaseRec& CR,
|
2007-03-27 19:29:11 +08:00
|
|
|
CaseRecVector& WorkList,
|
|
|
|
Value* SV,
|
|
|
|
MachineBasicBlock* Default);
|
2007-04-09 20:31:58 +08:00
|
|
|
bool handleBitTestsSwitchCase(CaseRec& CR,
|
|
|
|
CaseRecVector& WorkList,
|
|
|
|
Value* SV,
|
|
|
|
MachineBasicBlock* Default);
|
2006-03-27 09:32:24 +08:00
|
|
|
void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
|
2007-04-09 20:31:58 +08:00
|
|
|
void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B);
|
|
|
|
void visitBitTestCase(MachineBasicBlock* NextMBB,
|
|
|
|
unsigned Reg,
|
|
|
|
SelectionDAGISel::BitTestCase &B);
|
2006-04-23 02:53:45 +08:00
|
|
|
void visitJumpTable(SelectionDAGISel::JumpTable &JT);
|
2007-03-25 23:07:15 +08:00
|
|
|
void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
|
|
|
|
SelectionDAGISel::JumpTableHeader &JTH);
|
2006-03-27 09:32:24 +08:00
|
|
|
|
2005-01-07 15:47:53 +08:00
|
|
|
// These all get lowered before this pass.
|
2007-02-22 06:53:45 +08:00
|
|
|
void visitInvoke(InvokeInst &I);
|
|
|
|
void visitUnwind(UnwindInst &I);
|
2005-01-07 15:47:53 +08:00
|
|
|
|
2007-06-26 00:23:39 +08:00
|
|
|
void visitBinary(User &I, unsigned OpCode);
|
2005-11-18 15:42:56 +08:00
|
|
|
void visitShift(User &I, unsigned Opcode);
|
2005-11-19 08:36:38 +08:00
|
|
|
void visitAdd(User &I) {
|
2007-06-26 00:23:39 +08:00
|
|
|
if (I.getType()->isFPOrFPVector())
|
|
|
|
visitBinary(I, ISD::FADD);
|
2006-10-26 14:15:43 +08:00
|
|
|
else
|
2007-06-26 00:23:39 +08:00
|
|
|
visitBinary(I, ISD::ADD);
|
2005-09-29 06:28:18 +08:00
|
|
|
}
|
2005-04-02 13:04:50 +08:00
|
|
|
void visitSub(User &I);
|
2006-10-26 14:15:43 +08:00
|
|
|
void visitMul(User &I) {
|
2007-06-26 00:23:39 +08:00
|
|
|
if (I.getType()->isFPOrFPVector())
|
|
|
|
visitBinary(I, ISD::FMUL);
|
2006-10-26 14:15:43 +08:00
|
|
|
else
|
2007-06-26 00:23:39 +08:00
|
|
|
visitBinary(I, ISD::MUL);
|
2005-01-07 15:47:53 +08:00
|
|
|
}
|
2007-06-26 00:23:39 +08:00
|
|
|
void visitURem(User &I) { visitBinary(I, ISD::UREM); }
|
|
|
|
void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
|
|
|
|
void visitFRem(User &I) { visitBinary(I, ISD::FREM); }
|
|
|
|
void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); }
|
|
|
|
void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); }
|
|
|
|
void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); }
|
|
|
|
void visitAnd (User &I) { visitBinary(I, ISD::AND); }
|
|
|
|
void visitOr (User &I) { visitBinary(I, ISD::OR); }
|
|
|
|
void visitXor (User &I) { visitBinary(I, ISD::XOR); }
|
2007-01-21 08:29:26 +08:00
|
|
|
void visitShl (User &I) { visitShift(I, ISD::SHL); }
|
2006-11-08 14:47:33 +08:00
|
|
|
void visitLShr(User &I) { visitShift(I, ISD::SRL); }
|
|
|
|
void visitAShr(User &I) { visitShift(I, ISD::SRA); }
|
2006-11-20 09:22:35 +08:00
|
|
|
void visitICmp(User &I);
|
|
|
|
void visitFCmp(User &I);
|
2008-05-13 03:40:03 +08:00
|
|
|
void visitVICmp(User &I);
|
|
|
|
void visitVFCmp(User &I);
|
2006-11-27 09:05:10 +08:00
|
|
|
// Visit the conversion instructions
|
|
|
|
void visitTrunc(User &I);
|
|
|
|
void visitZExt(User &I);
|
|
|
|
void visitSExt(User &I);
|
|
|
|
void visitFPTrunc(User &I);
|
|
|
|
void visitFPExt(User &I);
|
|
|
|
void visitFPToUI(User &I);
|
|
|
|
void visitFPToSI(User &I);
|
|
|
|
void visitUIToFP(User &I);
|
|
|
|
void visitSIToFP(User &I);
|
|
|
|
void visitPtrToInt(User &I);
|
|
|
|
void visitIntToPtr(User &I);
|
|
|
|
void visitBitCast(User &I);
|
2005-01-07 15:47:53 +08:00
|
|
|
|
2006-03-29 08:11:43 +08:00
|
|
|
void visitExtractElement(User &I);
|
|
|
|
void visitInsertElement(User &I);
|
2006-04-08 12:15:24 +08:00
|
|
|
void visitShuffleVector(User &I);
|
2006-03-18 09:44:44 +08:00
|
|
|
|
2008-06-07 10:02:36 +08:00
|
|
|
void visitExtractValue(ExtractValueInst &I);
|
|
|
|
void visitInsertValue(InsertValueInst &I);
|
2008-05-16 03:50:34 +08:00
|
|
|
|
2005-01-07 15:47:53 +08:00
|
|
|
void visitGetElementPtr(User &I);
|
|
|
|
void visitSelect(User &I);
|
|
|
|
|
|
|
|
void visitMalloc(MallocInst &I);
|
|
|
|
void visitFree(FreeInst &I);
|
|
|
|
void visitAlloca(AllocaInst &I);
|
|
|
|
void visitLoad(LoadInst &I);
|
|
|
|
void visitStore(StoreInst &I);
|
|
|
|
void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
|
|
|
|
void visitCall(CallInst &I);
|
2007-12-18 02:08:19 +08:00
|
|
|
void visitInlineAsm(CallSite CS);
|
2005-11-10 03:44:01 +08:00
|
|
|
const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
|
2006-03-24 10:22:33 +08:00
|
|
|
void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
|
2005-01-07 15:47:53 +08:00
|
|
|
|
|
|
|
void visitVAStart(CallInst &I);
|
|
|
|
void visitVAArg(VAArgInst &I);
|
|
|
|
void visitVAEnd(CallInst &I);
|
|
|
|
void visitVACopy(CallInst &I);
|
|
|
|
|
2008-03-12 05:11:25 +08:00
|
|
|
void visitGetResult(GetResultInst &I);
|
2008-02-20 06:15:16 +08:00
|
|
|
|
2005-01-07 15:47:53 +08:00
|
|
|
void visitUserOp1(Instruction &I) {
|
|
|
|
assert(0 && "UserOp1 should not exist at instruction selection time!");
|
|
|
|
abort();
|
|
|
|
}
|
|
|
|
void visitUserOp2(Instruction &I) {
|
|
|
|
assert(0 && "UserOp2 should not exist at instruction selection time!");
|
|
|
|
abort();
|
|
|
|
}
|
2008-05-06 03:05:59 +08:00
|
|
|
|
|
|
|
private:
|
|
|
|
inline const char *implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op);
|
|
|
|
|
2005-01-07 15:47:53 +08:00
|
|
|
};
|
|
|
|
} // end namespace llvm
|
|
|
|
|
2007-07-06 04:12:34 +08:00
|
|
|
|
2008-02-12 04:58:28 +08:00
|
|
|
/// getCopyFromParts - Create a value that contains the specified legal parts
|
|
|
|
/// combined into the value they represent. If the parts combine to a type
|
|
|
|
/// larger then ValueVT then AssertOp can be used to specify whether the extra
|
|
|
|
/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
|
2008-03-09 17:38:46 +08:00
|
|
|
/// (ISD::AssertSext).
|
2007-07-06 04:12:34 +08:00
|
|
|
static SDOperand getCopyFromParts(SelectionDAG &DAG,
|
|
|
|
const SDOperand *Parts,
|
|
|
|
unsigned NumParts,
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT PartVT,
|
|
|
|
MVT ValueVT,
|
2008-03-09 17:38:46 +08:00
|
|
|
ISD::NodeType AssertOp = ISD::DELETED_NODE) {
|
2008-02-13 04:46:31 +08:00
|
|
|
assert(NumParts > 0 && "No parts to assemble!");
|
|
|
|
TargetLowering &TLI = DAG.getTargetLoweringInfo();
|
|
|
|
SDOperand Val = Parts[0];
|
|
|
|
|
|
|
|
if (NumParts > 1) {
|
|
|
|
// Assemble the value from multiple parts.
|
2008-06-06 20:08:01 +08:00
|
|
|
if (!ValueVT.isVector()) {
|
|
|
|
unsigned PartBits = PartVT.getSizeInBits();
|
|
|
|
unsigned ValueBits = ValueVT.getSizeInBits();
|
2008-02-13 04:46:31 +08:00
|
|
|
|
|
|
|
// Assemble the power of 2 part.
|
|
|
|
unsigned RoundParts = NumParts & (NumParts - 1) ?
|
|
|
|
1 << Log2_32(NumParts) : NumParts;
|
|
|
|
unsigned RoundBits = PartBits * RoundParts;
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT RoundVT = RoundBits == ValueBits ?
|
|
|
|
ValueVT : MVT::getIntegerVT(RoundBits);
|
2008-02-13 04:46:31 +08:00
|
|
|
SDOperand Lo, Hi;
|
|
|
|
|
|
|
|
if (RoundParts > 2) {
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT HalfVT = MVT::getIntegerVT(RoundBits/2);
|
2008-02-13 04:46:31 +08:00
|
|
|
Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT);
|
|
|
|
Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2,
|
|
|
|
PartVT, HalfVT);
|
2007-07-06 04:12:34 +08:00
|
|
|
} else {
|
2008-02-13 04:46:31 +08:00
|
|
|
Lo = Parts[0];
|
|
|
|
Hi = Parts[1];
|
2007-07-06 04:12:34 +08:00
|
|
|
}
|
2008-02-13 04:46:31 +08:00
|
|
|
if (TLI.isBigEndian())
|
|
|
|
std::swap(Lo, Hi);
|
|
|
|
Val = DAG.getNode(ISD::BUILD_PAIR, RoundVT, Lo, Hi);
|
|
|
|
|
|
|
|
if (RoundParts < NumParts) {
|
|
|
|
// Assemble the trailing non-power-of-2 part.
|
|
|
|
unsigned OddParts = NumParts - RoundParts;
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
|
2008-02-13 04:46:31 +08:00
|
|
|
Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT);
|
|
|
|
|
|
|
|
// Combine the round and odd parts.
|
|
|
|
Lo = Val;
|
|
|
|
if (TLI.isBigEndian())
|
|
|
|
std::swap(Lo, Hi);
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
|
2008-02-13 04:46:31 +08:00
|
|
|
Hi = DAG.getNode(ISD::ANY_EXTEND, TotalVT, Hi);
|
|
|
|
Hi = DAG.getNode(ISD::SHL, TotalVT, Hi,
|
2008-06-06 20:08:01 +08:00
|
|
|
DAG.getConstant(Lo.getValueType().getSizeInBits(),
|
2008-02-13 04:46:31 +08:00
|
|
|
TLI.getShiftAmountTy()));
|
|
|
|
Lo = DAG.getNode(ISD::ZERO_EXTEND, TotalVT, Lo);
|
|
|
|
Val = DAG.getNode(ISD::OR, TotalVT, Lo, Hi);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
// Handle a multi-element vector.
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT IntermediateVT, RegisterVT;
|
2008-02-13 04:46:31 +08:00
|
|
|
unsigned NumIntermediates;
|
|
|
|
unsigned NumRegs =
|
|
|
|
TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
|
|
|
|
RegisterVT);
|
|
|
|
assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
|
2008-05-15 04:29:30 +08:00
|
|
|
NumParts = NumRegs; // Silence a compiler warning.
|
2008-02-13 04:46:31 +08:00
|
|
|
assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
|
|
|
|
assert(RegisterVT == Parts[0].getValueType() &&
|
|
|
|
"Part type doesn't match part!");
|
|
|
|
|
|
|
|
// Assemble the parts into intermediate operands.
|
|
|
|
SmallVector<SDOperand, 8> Ops(NumIntermediates);
|
|
|
|
if (NumIntermediates == NumParts) {
|
|
|
|
// If the register was not expanded, truncate or copy the value,
|
|
|
|
// as appropriate.
|
|
|
|
for (unsigned i = 0; i != NumParts; ++i)
|
|
|
|
Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
|
|
|
|
PartVT, IntermediateVT);
|
|
|
|
} else if (NumParts > 0) {
|
|
|
|
// If the intermediate type was expanded, build the intermediate operands
|
|
|
|
// from the parts.
|
|
|
|
assert(NumParts % NumIntermediates == 0 &&
|
|
|
|
"Must expand into a divisible number of parts!");
|
|
|
|
unsigned Factor = NumParts / NumIntermediates;
|
|
|
|
for (unsigned i = 0; i != NumIntermediates; ++i)
|
|
|
|
Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
|
|
|
|
PartVT, IntermediateVT);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
|
|
|
|
// operands.
|
2008-06-06 20:08:01 +08:00
|
|
|
Val = DAG.getNode(IntermediateVT.isVector() ?
|
2008-02-13 04:46:31 +08:00
|
|
|
ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR,
|
|
|
|
ValueVT, &Ops[0], NumIntermediates);
|
2007-07-06 04:12:34 +08:00
|
|
|
}
|
2008-02-13 04:46:31 +08:00
|
|
|
}
|
2007-07-06 04:12:34 +08:00
|
|
|
|
2008-02-13 04:46:31 +08:00
|
|
|
// There is now one part, held in Val. Correct it to match ValueVT.
|
|
|
|
PartVT = Val.getValueType();
|
2007-07-06 04:12:34 +08:00
|
|
|
|
2008-02-13 04:46:31 +08:00
|
|
|
if (PartVT == ValueVT)
|
|
|
|
return Val;
|
|
|
|
|
2008-06-06 20:08:01 +08:00
|
|
|
if (PartVT.isVector()) {
|
|
|
|
assert(ValueVT.isVector() && "Unknown vector conversion!");
|
2008-02-13 04:46:31 +08:00
|
|
|
return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
|
2007-07-06 04:12:34 +08:00
|
|
|
}
|
|
|
|
|
2008-06-06 20:08:01 +08:00
|
|
|
if (ValueVT.isVector()) {
|
|
|
|
assert(ValueVT.getVectorElementType() == PartVT &&
|
|
|
|
ValueVT.getVectorNumElements() == 1 &&
|
2008-02-13 04:46:31 +08:00
|
|
|
"Only trivial scalar-to-vector conversions should get here!");
|
|
|
|
return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val);
|
|
|
|
}
|
2007-07-06 04:12:34 +08:00
|
|
|
|
2008-06-06 20:08:01 +08:00
|
|
|
if (PartVT.isInteger() &&
|
|
|
|
ValueVT.isInteger()) {
|
2008-06-09 04:54:56 +08:00
|
|
|
if (ValueVT.bitsLT(PartVT)) {
|
2008-02-13 04:46:31 +08:00
|
|
|
// For a truncate, see if we have any information to
|
|
|
|
// indicate whether the truncated bits will always be
|
|
|
|
// zero or sign-extension.
|
|
|
|
if (AssertOp != ISD::DELETED_NODE)
|
|
|
|
Val = DAG.getNode(AssertOp, PartVT, Val,
|
|
|
|
DAG.getValueType(ValueVT));
|
|
|
|
return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
|
|
|
|
} else {
|
|
|
|
return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
|
|
|
|
}
|
2007-07-06 04:12:34 +08:00
|
|
|
}
|
2008-02-13 04:46:31 +08:00
|
|
|
|
2008-06-06 20:08:01 +08:00
|
|
|
if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
|
2008-06-09 04:54:56 +08:00
|
|
|
if (ValueVT.bitsLT(Val.getValueType()))
|
2008-03-09 17:38:46 +08:00
|
|
|
// FP_ROUND's are always exact here.
|
2008-03-09 15:47:22 +08:00
|
|
|
return DAG.getNode(ISD::FP_ROUND, ValueVT, Val,
|
2008-03-09 17:38:46 +08:00
|
|
|
DAG.getIntPtrConstant(1));
|
2008-03-09 15:47:22 +08:00
|
|
|
return DAG.getNode(ISD::FP_EXTEND, ValueVT, Val);
|
|
|
|
}
|
2008-02-13 04:46:31 +08:00
|
|
|
|
2008-06-06 20:08:01 +08:00
|
|
|
if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
|
2008-02-13 04:46:31 +08:00
|
|
|
return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
|
|
|
|
|
|
|
|
assert(0 && "Unknown mismatch!");
|
2008-03-31 02:22:13 +08:00
|
|
|
return SDOperand();
|
2007-07-06 04:12:34 +08:00
|
|
|
}
|
|
|
|
|
2008-02-12 04:58:28 +08:00
|
|
|
/// getCopyToParts - Create a series of nodes that contain the specified value
|
|
|
|
/// split into legal parts. If the parts contain more bits than Val, then, for
|
|
|
|
/// integers, ExtendKind can be used to specify how to generate the extra bits.
|
2007-07-06 04:12:34 +08:00
|
|
|
static void getCopyToParts(SelectionDAG &DAG,
|
|
|
|
SDOperand Val,
|
|
|
|
SDOperand *Parts,
|
|
|
|
unsigned NumParts,
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT PartVT,
|
2008-02-12 04:58:28 +08:00
|
|
|
ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
|
2007-08-10 22:59:38 +08:00
|
|
|
TargetLowering &TLI = DAG.getTargetLoweringInfo();
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT PtrVT = TLI.getPointerTy();
|
|
|
|
MVT ValueVT = Val.getValueType();
|
|
|
|
unsigned PartBits = PartVT.getSizeInBits();
|
2008-02-13 04:46:31 +08:00
|
|
|
assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
|
|
|
|
|
|
|
|
if (!NumParts)
|
|
|
|
return;
|
|
|
|
|
2008-06-06 20:08:01 +08:00
|
|
|
if (!ValueVT.isVector()) {
|
2008-02-13 04:46:31 +08:00
|
|
|
if (PartVT == ValueVT) {
|
|
|
|
assert(NumParts == 1 && "No-op copy with multiple parts!");
|
|
|
|
Parts[0] = Val;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2008-06-06 20:08:01 +08:00
|
|
|
if (NumParts * PartBits > ValueVT.getSizeInBits()) {
|
2008-02-13 04:46:31 +08:00
|
|
|
// If the parts cover more bits than the value has, promote the value.
|
2008-06-06 20:08:01 +08:00
|
|
|
if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
|
2008-02-13 04:46:31 +08:00
|
|
|
assert(NumParts == 1 && "Do not know what to promote to!");
|
|
|
|
Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
|
2008-06-06 20:08:01 +08:00
|
|
|
} else if (PartVT.isInteger() && ValueVT.isInteger()) {
|
|
|
|
ValueVT = MVT::getIntegerVT(NumParts * PartBits);
|
2008-02-13 04:46:31 +08:00
|
|
|
Val = DAG.getNode(ExtendKind, ValueVT, Val);
|
|
|
|
} else {
|
|
|
|
assert(0 && "Unknown mismatch!");
|
|
|
|
}
|
2008-06-06 20:08:01 +08:00
|
|
|
} else if (PartBits == ValueVT.getSizeInBits()) {
|
2008-02-13 04:46:31 +08:00
|
|
|
// Different types of the same size.
|
|
|
|
assert(NumParts == 1 && PartVT != ValueVT);
|
|
|
|
Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
|
2008-06-06 20:08:01 +08:00
|
|
|
} else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
|
2008-02-13 04:46:31 +08:00
|
|
|
// If the parts cover less bits than value has, truncate the value.
|
2008-06-06 20:08:01 +08:00
|
|
|
if (PartVT.isInteger() && ValueVT.isInteger()) {
|
|
|
|
ValueVT = MVT::getIntegerVT(NumParts * PartBits);
|
2008-02-13 04:46:31 +08:00
|
|
|
Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
|
|
|
|
} else {
|
|
|
|
assert(0 && "Unknown mismatch!");
|
|
|
|
}
|
|
|
|
}
|
2007-07-06 04:12:34 +08:00
|
|
|
|
2008-02-13 04:46:31 +08:00
|
|
|
// The value may have changed - recompute ValueVT.
|
|
|
|
ValueVT = Val.getValueType();
|
2008-06-06 20:08:01 +08:00
|
|
|
assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
|
2008-02-13 04:46:31 +08:00
|
|
|
"Failed to tile the value with PartVT!");
|
|
|
|
|
|
|
|
if (NumParts == 1) {
|
|
|
|
assert(PartVT == ValueVT && "Type conversion failed!");
|
|
|
|
Parts[0] = Val;
|
2007-07-06 04:12:34 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2008-02-13 04:46:31 +08:00
|
|
|
// Expand the value into multiple parts.
|
|
|
|
if (NumParts & (NumParts - 1)) {
|
|
|
|
// The number of parts is not a power of 2. Split off and copy the tail.
|
2008-06-06 20:08:01 +08:00
|
|
|
assert(PartVT.isInteger() && ValueVT.isInteger() &&
|
2008-02-13 04:46:31 +08:00
|
|
|
"Do not know what to expand to!");
|
|
|
|
unsigned RoundParts = 1 << Log2_32(NumParts);
|
|
|
|
unsigned RoundBits = RoundParts * PartBits;
|
|
|
|
unsigned OddParts = NumParts - RoundParts;
|
|
|
|
SDOperand OddVal = DAG.getNode(ISD::SRL, ValueVT, Val,
|
|
|
|
DAG.getConstant(RoundBits,
|
|
|
|
TLI.getShiftAmountTy()));
|
|
|
|
getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT);
|
|
|
|
if (TLI.isBigEndian())
|
|
|
|
// The odd parts were reversed by getCopyToParts - unreverse them.
|
|
|
|
std::reverse(Parts + RoundParts, Parts + NumParts);
|
|
|
|
NumParts = RoundParts;
|
2008-06-06 20:08:01 +08:00
|
|
|
ValueVT = MVT::getIntegerVT(NumParts * PartBits);
|
2008-02-13 04:46:31 +08:00
|
|
|
Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
|
|
|
|
}
|
|
|
|
|
|
|
|
// The number of parts is a power of 2. Repeatedly bisect the value using
|
|
|
|
// EXTRACT_ELEMENT.
|
2008-03-13 04:30:08 +08:00
|
|
|
Parts[0] = DAG.getNode(ISD::BIT_CONVERT,
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT::getIntegerVT(ValueVT.getSizeInBits()),
|
2008-03-13 04:30:08 +08:00
|
|
|
Val);
|
2008-02-13 04:46:31 +08:00
|
|
|
for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
|
|
|
|
for (unsigned i = 0; i < NumParts; i += StepSize) {
|
|
|
|
unsigned ThisBits = StepSize * PartBits / 2;
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT ThisVT = MVT::getIntegerVT (ThisBits);
|
2008-03-13 04:30:08 +08:00
|
|
|
SDOperand &Part0 = Parts[i];
|
|
|
|
SDOperand &Part1 = Parts[i+StepSize/2];
|
|
|
|
|
|
|
|
Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
|
|
|
|
DAG.getConstant(1, PtrVT));
|
|
|
|
Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
|
|
|
|
DAG.getConstant(0, PtrVT));
|
|
|
|
|
|
|
|
if (ThisBits == PartBits && ThisVT != PartVT) {
|
|
|
|
Part0 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part0);
|
|
|
|
Part1 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part1);
|
|
|
|
}
|
2008-02-13 04:46:31 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (TLI.isBigEndian())
|
|
|
|
std::reverse(Parts, Parts + NumParts);
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Vector ValueVT.
|
|
|
|
if (NumParts == 1) {
|
2007-07-06 04:12:34 +08:00
|
|
|
if (PartVT != ValueVT) {
|
2008-06-06 20:08:01 +08:00
|
|
|
if (PartVT.isVector()) {
|
2007-07-06 04:12:34 +08:00
|
|
|
Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
|
2008-02-13 04:46:31 +08:00
|
|
|
} else {
|
2008-06-06 20:08:01 +08:00
|
|
|
assert(ValueVT.getVectorElementType() == PartVT &&
|
|
|
|
ValueVT.getVectorNumElements() == 1 &&
|
2007-10-12 22:33:11 +08:00
|
|
|
"Only trivial vector-to-scalar conversions should get here!");
|
|
|
|
Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val,
|
|
|
|
DAG.getConstant(0, PtrVT));
|
2007-07-06 04:12:34 +08:00
|
|
|
}
|
|
|
|
}
|
2008-02-13 04:46:31 +08:00
|
|
|
|
2007-07-06 04:12:34 +08:00
|
|
|
Parts[0] = Val;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Handle a multi-element vector.
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT IntermediateVT, RegisterVT;
|
2007-07-06 04:12:34 +08:00
|
|
|
unsigned NumIntermediates;
|
|
|
|
unsigned NumRegs =
|
|
|
|
DAG.getTargetLoweringInfo()
|
|
|
|
.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
|
|
|
|
RegisterVT);
|
2008-06-06 20:08:01 +08:00
|
|
|
unsigned NumElements = ValueVT.getVectorNumElements();
|
2007-07-06 04:12:34 +08:00
|
|
|
|
|
|
|
assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
|
2008-05-15 04:29:30 +08:00
|
|
|
NumParts = NumRegs; // Silence a compiler warning.
|
2007-07-06 04:12:34 +08:00
|
|
|
assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
|
|
|
|
|
|
|
|
// Split the vector into intermediate operands.
|
|
|
|
SmallVector<SDOperand, 8> Ops(NumIntermediates);
|
|
|
|
for (unsigned i = 0; i != NumIntermediates; ++i)
|
2008-06-06 20:08:01 +08:00
|
|
|
if (IntermediateVT.isVector())
|
2007-07-06 04:12:34 +08:00
|
|
|
Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
|
|
|
|
IntermediateVT, Val,
|
|
|
|
DAG.getConstant(i * (NumElements / NumIntermediates),
|
2007-08-10 22:59:38 +08:00
|
|
|
PtrVT));
|
2007-07-06 04:12:34 +08:00
|
|
|
else
|
|
|
|
Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
|
|
|
|
IntermediateVT, Val,
|
2007-08-10 22:59:38 +08:00
|
|
|
DAG.getConstant(i, PtrVT));
|
2007-07-06 04:12:34 +08:00
|
|
|
|
|
|
|
// Split the intermediate operands into legal parts.
|
|
|
|
if (NumParts == NumIntermediates) {
|
|
|
|
// If the register was not expanded, promote or copy the value,
|
|
|
|
// as appropriate.
|
|
|
|
for (unsigned i = 0; i != NumParts; ++i)
|
2007-07-10 04:59:04 +08:00
|
|
|
getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
|
2007-07-06 04:12:34 +08:00
|
|
|
} else if (NumParts > 0) {
|
|
|
|
// If the intermediate type was expanded, split each the value into
|
|
|
|
// legal parts.
|
|
|
|
assert(NumParts % NumIntermediates == 0 &&
|
|
|
|
"Must expand into a divisible number of parts!");
|
|
|
|
unsigned Factor = NumParts / NumIntermediates;
|
|
|
|
for (unsigned i = 0; i != NumIntermediates; ++i)
|
2007-07-10 04:59:04 +08:00
|
|
|
getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
|
2007-07-06 04:12:34 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2006-03-17 03:57:50 +08:00
|
|
|
SDOperand SelectionDAGLowering::getValue(const Value *V) {
|
|
|
|
SDOperand &N = NodeMap[V];
|
|
|
|
if (N.Val) return N;
|
|
|
|
|
|
|
|
if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT VT = TLI.getValueType(V->getType(), true);
|
2008-04-28 14:44:42 +08:00
|
|
|
|
|
|
|
if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
|
|
|
|
return N = DAG.getConstant(CI->getValue(), VT);
|
|
|
|
|
|
|
|
if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
|
2006-03-17 03:57:50 +08:00
|
|
|
return N = DAG.getGlobalAddress(GV, VT);
|
2008-04-28 14:44:42 +08:00
|
|
|
|
|
|
|
if (isa<ConstantPointerNull>(C))
|
2006-03-17 03:57:50 +08:00
|
|
|
return N = DAG.getConstant(0, TLI.getPointerTy());
|
2008-04-28 14:44:42 +08:00
|
|
|
|
|
|
|
if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
|
|
|
|
return N = DAG.getConstantFP(CFP->getValueAPF(), VT);
|
|
|
|
|
2008-06-07 10:02:36 +08:00
|
|
|
if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()) &&
|
|
|
|
!V->getType()->isAggregateType())
|
2008-04-28 15:16:35 +08:00
|
|
|
return N = DAG.getNode(ISD::UNDEF, VT);
|
2008-04-28 14:44:42 +08:00
|
|
|
|
|
|
|
if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
|
|
|
|
visit(CE->getOpcode(), *CE);
|
|
|
|
SDOperand N1 = NodeMap[V];
|
|
|
|
assert(N1.Val && "visit didn't populate the ValueMap!");
|
|
|
|
return N1;
|
|
|
|
}
|
|
|
|
|
2008-06-07 10:02:36 +08:00
|
|
|
if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
|
|
|
|
SmallVector<SDOperand, 4> Constants;
|
|
|
|
SmallVector<MVT, 4> ValueVTs;
|
|
|
|
for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
|
|
|
|
OI != OE; ++OI) {
|
|
|
|
SDNode *Val = getValue(*OI).Val;
|
|
|
|
for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) {
|
|
|
|
Constants.push_back(SDOperand(Val, i));
|
|
|
|
ValueVTs.push_back(Val->getValueType(i));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return DAG.getNode(ISD::MERGE_VALUES,
|
|
|
|
DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
|
|
|
|
&Constants[0], Constants.size());
|
|
|
|
}
|
|
|
|
|
|
|
|
if (const ArrayType *ATy = dyn_cast<ArrayType>(C->getType())) {
|
|
|
|
assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
|
|
|
|
"Unknown array constant!");
|
|
|
|
unsigned NumElts = ATy->getNumElements();
|
|
|
|
MVT EltVT = TLI.getValueType(ATy->getElementType());
|
|
|
|
SmallVector<SDOperand, 4> Constants(NumElts);
|
|
|
|
SmallVector<MVT, 4> ValueVTs(NumElts, EltVT);
|
|
|
|
for (unsigned i = 0, e = NumElts; i != e; ++i) {
|
|
|
|
if (isa<UndefValue>(C))
|
|
|
|
Constants[i] = DAG.getNode(ISD::UNDEF, EltVT);
|
|
|
|
else if (EltVT.isFloatingPoint())
|
|
|
|
Constants[i] = DAG.getConstantFP(0, EltVT);
|
|
|
|
else
|
|
|
|
Constants[i] = DAG.getConstant(0, EltVT);
|
|
|
|
}
|
|
|
|
return DAG.getNode(ISD::MERGE_VALUES,
|
|
|
|
DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
|
|
|
|
&Constants[0], Constants.size());
|
|
|
|
}
|
|
|
|
|
|
|
|
if (const StructType *STy = dyn_cast<StructType>(C->getType())) {
|
|
|
|
assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
|
|
|
|
"Unknown struct constant!");
|
|
|
|
unsigned NumElts = STy->getNumElements();
|
|
|
|
SmallVector<SDOperand, 4> Constants(NumElts);
|
|
|
|
SmallVector<MVT, 4> ValueVTs(NumElts);
|
|
|
|
for (unsigned i = 0, e = NumElts; i != e; ++i) {
|
|
|
|
MVT EltVT = TLI.getValueType(STy->getElementType(i));
|
|
|
|
ValueVTs[i] = EltVT;
|
|
|
|
if (isa<UndefValue>(C))
|
|
|
|
Constants[i] = DAG.getNode(ISD::UNDEF, EltVT);
|
|
|
|
else if (EltVT.isFloatingPoint())
|
|
|
|
Constants[i] = DAG.getConstantFP(0, EltVT);
|
|
|
|
else
|
|
|
|
Constants[i] = DAG.getConstant(0, EltVT);
|
|
|
|
}
|
|
|
|
return DAG.getNode(ISD::MERGE_VALUES,
|
|
|
|
DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
|
|
|
|
&Constants[0], Constants.size());
|
|
|
|
}
|
|
|
|
|
2008-04-28 15:16:35 +08:00
|
|
|
const VectorType *VecTy = cast<VectorType>(V->getType());
|
2008-04-28 14:44:42 +08:00
|
|
|
unsigned NumElements = VecTy->getNumElements();
|
|
|
|
|
2008-04-28 15:16:35 +08:00
|
|
|
// Now that we know the number and type of the elements, get that number of
|
|
|
|
// elements into the Ops array based on what kind of constant it is.
|
|
|
|
SmallVector<SDOperand, 16> Ops;
|
2008-04-28 14:44:42 +08:00
|
|
|
if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
|
|
|
|
for (unsigned i = 0; i != NumElements; ++i)
|
|
|
|
Ops.push_back(getValue(CP->getOperand(i)));
|
2006-03-17 03:57:50 +08:00
|
|
|
} else {
|
2008-04-28 15:16:35 +08:00
|
|
|
assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
|
|
|
|
"Unknown vector constant!");
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT EltVT = TLI.getValueType(VecTy->getElementType());
|
2008-04-28 15:16:35 +08:00
|
|
|
|
2008-04-28 14:44:42 +08:00
|
|
|
SDOperand Op;
|
2008-04-28 15:16:35 +08:00
|
|
|
if (isa<UndefValue>(C))
|
|
|
|
Op = DAG.getNode(ISD::UNDEF, EltVT);
|
2008-06-06 20:08:01 +08:00
|
|
|
else if (EltVT.isFloatingPoint())
|
2008-04-28 15:16:35 +08:00
|
|
|
Op = DAG.getConstantFP(0, EltVT);
|
2008-04-28 14:44:42 +08:00
|
|
|
else
|
2008-04-28 15:16:35 +08:00
|
|
|
Op = DAG.getConstant(0, EltVT);
|
2008-04-28 14:44:42 +08:00
|
|
|
Ops.assign(NumElements, Op);
|
2006-03-17 03:57:50 +08:00
|
|
|
}
|
2008-04-28 14:44:42 +08:00
|
|
|
|
|
|
|
// Create a BUILD_VECTOR node.
|
|
|
|
return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
|
2006-03-17 03:57:50 +08:00
|
|
|
}
|
|
|
|
|
2008-04-28 14:44:42 +08:00
|
|
|
// If this is a static alloca, generate it as the frameindex instead of
|
|
|
|
// computation.
|
2006-03-17 03:57:50 +08:00
|
|
|
if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
|
|
|
|
std::map<const AllocaInst*, int>::iterator SI =
|
2008-04-28 14:44:42 +08:00
|
|
|
FuncInfo.StaticAllocaMap.find(AI);
|
2006-03-17 03:57:50 +08:00
|
|
|
if (SI != FuncInfo.StaticAllocaMap.end())
|
|
|
|
return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
|
|
|
|
}
|
|
|
|
|
2007-02-26 02:40:32 +08:00
|
|
|
unsigned InReg = FuncInfo.ValueMap[V];
|
|
|
|
assert(InReg && "Value not in map!");
|
2006-03-17 03:57:50 +08:00
|
|
|
|
2008-04-28 15:16:35 +08:00
|
|
|
RegsForValue RFV(TLI, InReg, V->getType());
|
2007-06-29 07:29:44 +08:00
|
|
|
SDOperand Chain = DAG.getEntryNode();
|
|
|
|
return RFV.getCopyFromRegs(DAG, Chain, NULL);
|
2006-03-17 03:57:50 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2005-01-07 15:47:53 +08:00
|
|
|
void SelectionDAGLowering::visitRet(ReturnInst &I) {
|
|
|
|
if (I.getNumOperands() == 0) {
|
2008-03-28 03:56:19 +08:00
|
|
|
DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getControlRoot()));
|
2005-01-07 15:47:53 +08:00
|
|
|
return;
|
|
|
|
}
|
2008-04-28 14:44:42 +08:00
|
|
|
|
2006-08-08 10:23:42 +08:00
|
|
|
SmallVector<SDOperand, 8> NewValues;
|
2008-03-28 03:56:19 +08:00
|
|
|
NewValues.push_back(getControlRoot());
|
|
|
|
for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
|
2006-01-28 05:09:22 +08:00
|
|
|
SDOperand RetOp = getValue(I.getOperand(i));
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT VT = RetOp.getValueType();
|
2008-02-12 04:58:28 +08:00
|
|
|
|
2006-05-27 07:09:09 +08:00
|
|
|
// FIXME: C calling convention requires the return type to be promoted to
|
|
|
|
// at least 32-bit. But this is not necessary for non-C calling conventions.
|
2008-06-06 20:08:01 +08:00
|
|
|
if (VT.isInteger()) {
|
|
|
|
MVT MinVT = TLI.getRegisterType(MVT::i32);
|
2008-06-09 04:54:56 +08:00
|
|
|
if (VT.bitsLT(MinVT))
|
2008-02-12 04:58:28 +08:00
|
|
|
VT = MinVT;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned NumParts = TLI.getNumRegisters(VT);
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT PartVT = TLI.getRegisterType(VT);
|
2008-02-12 04:58:28 +08:00
|
|
|
SmallVector<SDOperand, 4> Parts(NumParts);
|
|
|
|
ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
|
|
|
|
|
|
|
|
const Function *F = I.getParent()->getParent();
|
|
|
|
if (F->paramHasAttr(0, ParamAttr::SExt))
|
|
|
|
ExtendKind = ISD::SIGN_EXTEND;
|
|
|
|
else if (F->paramHasAttr(0, ParamAttr::ZExt))
|
|
|
|
ExtendKind = ISD::ZERO_EXTEND;
|
|
|
|
|
|
|
|
getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT, ExtendKind);
|
|
|
|
|
|
|
|
for (unsigned i = 0; i < NumParts; ++i) {
|
|
|
|
NewValues.push_back(Parts[i]);
|
2008-03-21 17:14:45 +08:00
|
|
|
NewValues.push_back(DAG.getArgFlags(ISD::ArgFlagsTy()));
|
2006-01-28 05:09:22 +08:00
|
|
|
}
|
2005-01-07 15:47:53 +08:00
|
|
|
}
|
2006-08-08 10:23:42 +08:00
|
|
|
DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
|
|
|
|
&NewValues[0], NewValues.size()));
|
2005-01-07 15:47:53 +08:00
|
|
|
}
|
|
|
|
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
llvm-svn: 31230
2006-10-28 05:36:01 +08:00
|
|
|
/// ExportFromCurrentBlock - If this condition isn't known to be exported from
|
|
|
|
/// the current basic block, add it to ValueMap now so that we'll get a
|
|
|
|
/// CopyTo/FromReg.
|
|
|
|
void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
|
|
|
|
// No need to export constants.
|
|
|
|
if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
|
|
|
|
|
|
|
|
// Already exported?
|
|
|
|
if (FuncInfo.isExportedInst(V)) return;
|
|
|
|
|
|
|
|
unsigned Reg = FuncInfo.InitializeRegForValue(V);
|
2008-03-28 03:56:19 +08:00
|
|
|
CopyValueToVirtualRegister(V, Reg);
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
llvm-svn: 31230
2006-10-28 05:36:01 +08:00
|
|
|
}
|
|
|
|
|
2006-10-28 07:50:33 +08:00
|
|
|
bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
|
|
|
|
const BasicBlock *FromBB) {
|
|
|
|
// The operands of the setcc have to be in this block. We don't know
|
|
|
|
// how to export them from some other block.
|
|
|
|
if (Instruction *VI = dyn_cast<Instruction>(V)) {
|
|
|
|
// Can export from current BB.
|
|
|
|
if (VI->getParent() == FromBB)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
// Is already exported, noop.
|
|
|
|
return FuncInfo.isExportedInst(V);
|
|
|
|
}
|
|
|
|
|
|
|
|
// If this is an argument, we can export it if the BB is the entry block or
|
|
|
|
// if it is already exported.
|
|
|
|
if (isa<Argument>(V)) {
|
|
|
|
if (FromBB == &FromBB->getParent()->getEntryBlock())
|
|
|
|
return true;
|
|
|
|
|
|
|
|
// Otherwise, can only export this if it is already exported.
|
|
|
|
return FuncInfo.isExportedInst(V);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Otherwise, constants can always be exported.
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2006-10-30 05:01:20 +08:00
|
|
|
static bool InBlock(const Value *V, const BasicBlock *BB) {
|
|
|
|
if (const Instruction *I = dyn_cast<Instruction>(V))
|
|
|
|
return I->getParent() == BB;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
llvm-svn: 31230
2006-10-28 05:36:01 +08:00
|
|
|
/// FindMergedConditions - If Cond is an expression like
|
|
|
|
void SelectionDAGLowering::FindMergedConditions(Value *Cond,
|
|
|
|
MachineBasicBlock *TBB,
|
|
|
|
MachineBasicBlock *FBB,
|
|
|
|
MachineBasicBlock *CurBB,
|
|
|
|
unsigned Opc) {
|
|
|
|
// If this node is not part of the or/and tree, emit it as a branch.
|
2006-12-23 14:05:41 +08:00
|
|
|
Instruction *BOp = dyn_cast<Instruction>(Cond);
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
llvm-svn: 31230
2006-10-28 05:36:01 +08:00
|
|
|
|
2006-12-23 14:05:41 +08:00
|
|
|
if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
|
|
|
|
(unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
|
2006-10-30 05:01:20 +08:00
|
|
|
BOp->getParent() != CurBB->getBasicBlock() ||
|
|
|
|
!InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
|
|
|
|
!InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
llvm-svn: 31230
2006-10-28 05:36:01 +08:00
|
|
|
const BasicBlock *BB = CurBB->getBasicBlock();
|
|
|
|
|
2006-12-23 14:05:41 +08:00
|
|
|
// If the leaf of the tree is a comparison, merge the condition into
|
|
|
|
// the caseblock.
|
|
|
|
if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
|
|
|
|
// The operands of the cmp have to be in this block. We don't know
|
2006-10-30 02:23:37 +08:00
|
|
|
// how to export them from some other block. If this is the first block
|
|
|
|
// of the sequence, no exporting is needed.
|
|
|
|
(CurBB == CurMBB ||
|
|
|
|
(isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
|
|
|
|
isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
|
2006-12-23 14:05:41 +08:00
|
|
|
BOp = cast<Instruction>(Cond);
|
|
|
|
ISD::CondCode Condition;
|
|
|
|
if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
|
|
|
|
switch (IC->getPredicate()) {
|
|
|
|
default: assert(0 && "Unknown icmp predicate opcode!");
|
|
|
|
case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
|
|
|
|
case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
|
|
|
|
case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
|
|
|
|
case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
|
|
|
|
case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
|
|
|
|
case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
|
|
|
|
case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
|
|
|
|
case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
|
|
|
|
case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
|
|
|
|
case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
|
|
|
|
}
|
|
|
|
} else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
|
|
|
|
ISD::CondCode FPC, FOC;
|
|
|
|
switch (FC->getPredicate()) {
|
|
|
|
default: assert(0 && "Unknown fcmp predicate opcode!");
|
|
|
|
case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
|
|
|
|
case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
|
|
|
|
case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
|
|
|
|
case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
|
|
|
|
case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
|
|
|
|
case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
|
|
|
|
case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
|
2008-05-01 15:26:11 +08:00
|
|
|
case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
|
|
|
|
case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
|
2006-12-23 14:05:41 +08:00
|
|
|
case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
|
|
|
|
case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
|
|
|
|
case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
|
|
|
|
case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
|
|
|
|
case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
|
|
|
|
case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
|
|
|
|
case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
|
|
|
|
}
|
|
|
|
if (FiniteOnlyFPMath())
|
|
|
|
Condition = FOC;
|
|
|
|
else
|
|
|
|
Condition = FPC;
|
|
|
|
} else {
|
2007-02-04 09:31:47 +08:00
|
|
|
Condition = ISD::SETEQ; // silence warning.
|
2006-12-23 14:05:41 +08:00
|
|
|
assert(0 && "Unknown compare instruction");
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
llvm-svn: 31230
2006-10-28 05:36:01 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
|
2007-04-05 05:14:49 +08:00
|
|
|
BOp->getOperand(1), NULL, TBB, FBB, CurBB);
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
llvm-svn: 31230
2006-10-28 05:36:01 +08:00
|
|
|
SwitchCases.push_back(CB);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Create a CaseBlock record representing this branch.
|
2007-01-11 20:24:14 +08:00
|
|
|
SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
|
2007-04-05 05:14:49 +08:00
|
|
|
NULL, TBB, FBB, CurBB);
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
llvm-svn: 31230
2006-10-28 05:36:01 +08:00
|
|
|
SwitchCases.push_back(CB);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
Codegen cond&cond with two branches. This compiles (f.e.) PowerPC/and-branch.ll to:
cmpwi cr0, r4, 4
bgt cr0, LBB1_2 ;UnifiedReturnBlock
LBB1_3: ;entry
cmplwi cr0, r3, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r3, r4, r3
rlwinm r2, r2, 30, 31, 31
or r2, r2, r3
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
LBB1_1: ;cond_true
llvm-svn: 31232
2006-10-28 05:54:23 +08:00
|
|
|
|
|
|
|
// Create TmpBB after CurBB.
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
llvm-svn: 31230
2006-10-28 05:36:01 +08:00
|
|
|
MachineFunction::iterator BBI = CurBB;
|
|
|
|
MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock());
|
|
|
|
CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB);
|
|
|
|
|
Codegen cond&cond with two branches. This compiles (f.e.) PowerPC/and-branch.ll to:
cmpwi cr0, r4, 4
bgt cr0, LBB1_2 ;UnifiedReturnBlock
LBB1_3: ;entry
cmplwi cr0, r3, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r3, r4, r3
rlwinm r2, r2, 30, 31, 31
or r2, r2, r3
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
LBB1_1: ;cond_true
llvm-svn: 31232
2006-10-28 05:54:23 +08:00
|
|
|
if (Opc == Instruction::Or) {
|
|
|
|
// Codegen X | Y as:
|
|
|
|
// jmp_if_X TBB
|
|
|
|
// jmp TmpBB
|
|
|
|
// TmpBB:
|
|
|
|
// jmp_if_Y TBB
|
|
|
|
// jmp FBB
|
|
|
|
//
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
llvm-svn: 31230
2006-10-28 05:36:01 +08:00
|
|
|
|
Codegen cond&cond with two branches. This compiles (f.e.) PowerPC/and-branch.ll to:
cmpwi cr0, r4, 4
bgt cr0, LBB1_2 ;UnifiedReturnBlock
LBB1_3: ;entry
cmplwi cr0, r3, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r3, r4, r3
rlwinm r2, r2, 30, 31, 31
or r2, r2, r3
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
LBB1_1: ;cond_true
llvm-svn: 31232
2006-10-28 05:54:23 +08:00
|
|
|
// Emit the LHS condition.
|
|
|
|
FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
|
|
|
|
|
|
|
|
// Emit the RHS condition into TmpBB.
|
|
|
|
FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
|
|
|
|
} else {
|
|
|
|
assert(Opc == Instruction::And && "Unknown merge op!");
|
|
|
|
// Codegen X & Y as:
|
|
|
|
// jmp_if_X TmpBB
|
|
|
|
// jmp FBB
|
|
|
|
// TmpBB:
|
|
|
|
// jmp_if_Y TBB
|
|
|
|
// jmp FBB
|
|
|
|
//
|
|
|
|
// This requires creation of TmpBB after CurBB.
|
|
|
|
|
|
|
|
// Emit the LHS condition.
|
|
|
|
FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
|
|
|
|
|
|
|
|
// Emit the RHS condition into TmpBB.
|
|
|
|
FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
|
|
|
|
}
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
llvm-svn: 31230
2006-10-28 05:36:01 +08:00
|
|
|
}
|
|
|
|
|
2006-11-01 06:37:42 +08:00
|
|
|
/// If the set of cases should be emitted as a series of branches, return true.
|
|
|
|
/// If we should emit this as a bunch of and/or'd together conditions, return
|
|
|
|
/// false.
|
|
|
|
static bool
|
|
|
|
ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
|
|
|
|
if (Cases.size() != 2) return true;
|
|
|
|
|
Compile CodeGen/PowerPC/fp-branch.ll to:
_intcoord_cond_next55:
LBB1_3: ;cond_next55
lis r2, ha16(LCPI1_0)
lfs f0, lo16(LCPI1_0)(r2)
fcmpu cr0, f1, f0
blt cr0, LBB1_2 ;cond_next62.exitStub
LBB1_1: ;bb72.exitStub
li r3, 1
blr
LBB1_2: ;cond_next62.exitStub
li r3, 0
blr
instead of:
_intcoord_cond_next55:
LBB1_3: ;cond_next55
lis r2, ha16(LCPI1_0)
lfs f0, lo16(LCPI1_0)(r2)
fcmpu cr0, f1, f0
bge cr0, LBB1_1 ;bb72.exitStub
LBB1_4: ;cond_next55
lis r2, ha16(LCPI1_0)
lfs f0, lo16(LCPI1_0)(r2)
fcmpu cr0, f1, f0
bnu cr0, LBB1_2 ;cond_next62.exitStub
LBB1_1: ;bb72.exitStub
li r3, 1
blr
LBB1_2: ;cond_next62.exitStub
li r3, 0
blr
llvm-svn: 31330
2006-11-01 07:06:00 +08:00
|
|
|
// If this is two comparisons of the same values or'd or and'd together, they
|
|
|
|
// will get folded into a single comparison, so don't emit two blocks.
|
|
|
|
if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
|
|
|
|
Cases[0].CmpRHS == Cases[1].CmpRHS) ||
|
|
|
|
(Cases[0].CmpRHS == Cases[1].CmpLHS &&
|
|
|
|
Cases[0].CmpLHS == Cases[1].CmpRHS)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2006-11-01 06:37:42 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2005-01-07 15:47:53 +08:00
|
|
|
void SelectionDAGLowering::visitBr(BranchInst &I) {
|
|
|
|
// Update machine-CFG edges.
|
|
|
|
MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
|
|
|
|
|
|
|
|
// Figure out which block is immediately after the current one.
|
|
|
|
MachineBasicBlock *NextBlock = 0;
|
|
|
|
MachineFunction::iterator BBI = CurMBB;
|
|
|
|
if (++BBI != CurMBB->getParent()->end())
|
|
|
|
NextBlock = BBI;
|
|
|
|
|
|
|
|
if (I.isUnconditional()) {
|
2008-06-07 08:00:23 +08:00
|
|
|
// Update machine-CFG edges.
|
|
|
|
CurMBB->addSuccessor(Succ0MBB);
|
|
|
|
|
2005-01-07 15:47:53 +08:00
|
|
|
// If this is not a fall-through branch, emit the branch.
|
|
|
|
if (Succ0MBB != NextBlock)
|
2008-03-28 03:56:19 +08:00
|
|
|
DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
|
2005-04-22 12:01:18 +08:00
|
|
|
DAG.getBasicBlock(Succ0MBB)));
|
2006-10-25 01:57:59 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
// If this condition is one of the special cases we handle, do special stuff
|
|
|
|
// now.
|
|
|
|
Value *CondVal = I.getCondition();
|
|
|
|
MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
llvm-svn: 31230
2006-10-28 05:36:01 +08:00
|
|
|
|
|
|
|
// If this is a series of conditions that are or'd or and'd together, emit
|
|
|
|
// this as a sequence of branches instead of setcc's with and/or operations.
|
|
|
|
// For example, instead of something like:
|
|
|
|
// cmp A, B
|
|
|
|
// C = seteq
|
|
|
|
// cmp D, E
|
|
|
|
// F = setle
|
|
|
|
// or C, F
|
|
|
|
// jnz foo
|
|
|
|
// Emit:
|
|
|
|
// cmp A, B
|
|
|
|
// je foo
|
|
|
|
// cmp D, E
|
|
|
|
// jle foo
|
|
|
|
//
|
|
|
|
if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
|
|
|
|
if (BOp->hasOneUse() &&
|
Codegen cond&cond with two branches. This compiles (f.e.) PowerPC/and-branch.ll to:
cmpwi cr0, r4, 4
bgt cr0, LBB1_2 ;UnifiedReturnBlock
LBB1_3: ;entry
cmplwi cr0, r3, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r3, r4, r3
rlwinm r2, r2, 30, 31, 31
or r2, r2, r3
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
LBB1_1: ;cond_true
llvm-svn: 31232
2006-10-28 05:54:23 +08:00
|
|
|
(BOp->getOpcode() == Instruction::And ||
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
llvm-svn: 31230
2006-10-28 05:36:01 +08:00
|
|
|
BOp->getOpcode() == Instruction::Or)) {
|
|
|
|
FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
|
Compile CodeGen/PowerPC/fp-branch.ll to:
_intcoord_cond_next55:
LBB1_3: ;cond_next55
lis r2, ha16(LCPI1_0)
lfs f0, lo16(LCPI1_0)(r2)
fcmpu cr0, f1, f0
blt cr0, LBB1_2 ;cond_next62.exitStub
LBB1_1: ;bb72.exitStub
li r3, 1
blr
LBB1_2: ;cond_next62.exitStub
li r3, 0
blr
instead of:
_intcoord_cond_next55:
LBB1_3: ;cond_next55
lis r2, ha16(LCPI1_0)
lfs f0, lo16(LCPI1_0)(r2)
fcmpu cr0, f1, f0
bge cr0, LBB1_1 ;bb72.exitStub
LBB1_4: ;cond_next55
lis r2, ha16(LCPI1_0)
lfs f0, lo16(LCPI1_0)(r2)
fcmpu cr0, f1, f0
bnu cr0, LBB1_2 ;cond_next62.exitStub
LBB1_1: ;bb72.exitStub
li r3, 1
blr
LBB1_2: ;cond_next62.exitStub
li r3, 0
blr
llvm-svn: 31330
2006-11-01 07:06:00 +08:00
|
|
|
// If the compares in later blocks need to use values not currently
|
|
|
|
// exported from this block, export them now. This block should always
|
|
|
|
// be the first entry.
|
|
|
|
assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
|
|
|
|
|
2006-11-01 06:37:42 +08:00
|
|
|
// Allow some cases to be rejected.
|
|
|
|
if (ShouldEmitAsBranches(SwitchCases)) {
|
|
|
|
for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
|
|
|
|
ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
|
|
|
|
ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Emit the branch for this block.
|
|
|
|
visitSwitchCase(SwitchCases[0]);
|
|
|
|
SwitchCases.erase(SwitchCases.begin());
|
|
|
|
return;
|
2006-10-30 02:23:37 +08:00
|
|
|
}
|
|
|
|
|
Compile CodeGen/PowerPC/fp-branch.ll to:
_intcoord_cond_next55:
LBB1_3: ;cond_next55
lis r2, ha16(LCPI1_0)
lfs f0, lo16(LCPI1_0)(r2)
fcmpu cr0, f1, f0
blt cr0, LBB1_2 ;cond_next62.exitStub
LBB1_1: ;bb72.exitStub
li r3, 1
blr
LBB1_2: ;cond_next62.exitStub
li r3, 0
blr
instead of:
_intcoord_cond_next55:
LBB1_3: ;cond_next55
lis r2, ha16(LCPI1_0)
lfs f0, lo16(LCPI1_0)(r2)
fcmpu cr0, f1, f0
bge cr0, LBB1_1 ;bb72.exitStub
LBB1_4: ;cond_next55
lis r2, ha16(LCPI1_0)
lfs f0, lo16(LCPI1_0)(r2)
fcmpu cr0, f1, f0
bnu cr0, LBB1_2 ;cond_next62.exitStub
LBB1_1: ;bb72.exitStub
li r3, 1
blr
LBB1_2: ;cond_next62.exitStub
li r3, 0
blr
llvm-svn: 31330
2006-11-01 07:06:00 +08:00
|
|
|
// Okay, we decided not to do this, remove any inserted MBB's and clear
|
|
|
|
// SwitchCases.
|
|
|
|
for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
|
|
|
|
CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB);
|
|
|
|
|
2006-11-01 06:37:42 +08:00
|
|
|
SwitchCases.clear();
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
llvm-svn: 31230
2006-10-28 05:36:01 +08:00
|
|
|
}
|
|
|
|
}
|
2006-10-25 02:07:37 +08:00
|
|
|
|
|
|
|
// Create a CaseBlock record representing this branch.
|
2007-01-11 20:24:14 +08:00
|
|
|
SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
|
2007-04-05 05:14:49 +08:00
|
|
|
NULL, Succ0MBB, Succ1MBB, CurMBB);
|
2006-10-25 02:07:37 +08:00
|
|
|
// Use visitSwitchCase to actually insert the fast branch sequence for this
|
|
|
|
// cond branch.
|
|
|
|
visitSwitchCase(CB);
|
2005-01-07 15:47:53 +08:00
|
|
|
}
|
|
|
|
|
2006-03-27 09:32:24 +08:00
|
|
|
/// visitSwitchCase - Emits the necessary code to represent a single node in
|
|
|
|
/// the binary search tree resulting from lowering a switch instruction.
|
|
|
|
void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
|
2006-10-25 01:57:59 +08:00
|
|
|
SDOperand Cond;
|
|
|
|
SDOperand CondLHS = getValue(CB.CmpLHS);
|
|
|
|
|
2007-04-05 05:14:49 +08:00
|
|
|
// Build the setcc now.
|
|
|
|
if (CB.CmpMHS == NULL) {
|
|
|
|
// Fold "(X == true)" to X and "(X == false)" to !X to
|
|
|
|
// handle common cases produced by branch lowering.
|
|
|
|
if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
|
|
|
|
Cond = CondLHS;
|
|
|
|
else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
|
|
|
|
SDOperand True = DAG.getConstant(1, CondLHS.getValueType());
|
|
|
|
Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
|
|
|
|
} else
|
|
|
|
Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
|
|
|
|
} else {
|
|
|
|
assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
|
|
|
|
|
|
|
|
uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
|
|
|
|
uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
|
|
|
|
|
|
|
|
SDOperand CmpOp = getValue(CB.CmpMHS);
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT VT = CmpOp.getValueType();
|
2007-03-25 23:07:15 +08:00
|
|
|
|
2007-04-05 05:14:49 +08:00
|
|
|
if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
|
|
|
|
Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
|
|
|
|
} else {
|
|
|
|
SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
|
|
|
|
Cond = DAG.getSetCC(MVT::i1, SUB,
|
|
|
|
DAG.getConstant(High-Low, VT), ISD::SETULE);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-06-07 08:00:23 +08:00
|
|
|
// Update successor info
|
|
|
|
CurMBB->addSuccessor(CB.TrueBB);
|
|
|
|
CurMBB->addSuccessor(CB.FalseBB);
|
|
|
|
|
2006-03-27 09:32:24 +08:00
|
|
|
// Set NextBlock to be the MBB immediately after the current one, if any.
|
|
|
|
// This is used to avoid emitting unnecessary branches to the next block.
|
|
|
|
MachineBasicBlock *NextBlock = 0;
|
|
|
|
MachineFunction::iterator BBI = CurMBB;
|
|
|
|
if (++BBI != CurMBB->getParent()->end())
|
|
|
|
NextBlock = BBI;
|
|
|
|
|
|
|
|
// If the lhs block is the next block, invert the condition so that we can
|
|
|
|
// fall through to the lhs instead of the rhs block.
|
2006-10-25 01:57:59 +08:00
|
|
|
if (CB.TrueBB == NextBlock) {
|
|
|
|
std::swap(CB.TrueBB, CB.FalseBB);
|
2006-03-27 09:32:24 +08:00
|
|
|
SDOperand True = DAG.getConstant(1, Cond.getValueType());
|
|
|
|
Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
|
|
|
|
}
|
2008-03-28 03:56:19 +08:00
|
|
|
SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(), Cond,
|
2006-10-25 01:57:59 +08:00
|
|
|
DAG.getBasicBlock(CB.TrueBB));
|
|
|
|
if (CB.FalseBB == NextBlock)
|
2006-03-27 09:32:24 +08:00
|
|
|
DAG.setRoot(BrCond);
|
|
|
|
else
|
|
|
|
DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
|
2006-10-25 01:57:59 +08:00
|
|
|
DAG.getBasicBlock(CB.FalseBB)));
|
2006-03-27 09:32:24 +08:00
|
|
|
}
|
|
|
|
|
2007-03-25 23:07:15 +08:00
|
|
|
/// visitJumpTable - Emit JumpTable node in the current MBB
|
2006-04-23 02:53:45 +08:00
|
|
|
void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
|
|
|
|
// Emit the code for the jump table
|
2007-04-24 09:24:20 +08:00
|
|
|
assert(JT.Reg != -1U && "Should lower JT Header first!");
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT PTy = TLI.getPointerTy();
|
2008-03-28 03:56:19 +08:00
|
|
|
SDOperand Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy);
|
2006-10-30 16:00:44 +08:00
|
|
|
SDOperand Table = DAG.getJumpTable(JT.JTI, PTy);
|
|
|
|
DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
|
|
|
|
Table, Index));
|
|
|
|
return;
|
2006-04-23 02:53:45 +08:00
|
|
|
}
|
|
|
|
|
2007-03-25 23:07:15 +08:00
|
|
|
/// visitJumpTableHeader - This function emits necessary code to produce index
|
|
|
|
/// in the JumpTable from switch case.
|
|
|
|
void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
|
|
|
|
SelectionDAGISel::JumpTableHeader &JTH) {
|
|
|
|
// Subtract the lowest switch case value from the value being switched on
|
|
|
|
// and conditional branch to default mbb if the result is greater than the
|
|
|
|
// difference between smallest and largest cases.
|
|
|
|
SDOperand SwitchOp = getValue(JTH.SValue);
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT VT = SwitchOp.getValueType();
|
2007-03-25 23:07:15 +08:00
|
|
|
SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
|
|
|
|
DAG.getConstant(JTH.First, VT));
|
|
|
|
|
|
|
|
// The SDNode we just created, which holds the value being switched on
|
|
|
|
// minus the the smallest case value, needs to be copied to a virtual
|
|
|
|
// register so it can be used as an index into the jump table in a
|
|
|
|
// subsequent basic block. This value may be smaller or larger than the
|
|
|
|
// target's pointer type, and therefore require extension or truncating.
|
2008-06-09 04:54:56 +08:00
|
|
|
if (VT.bitsGT(TLI.getPointerTy()))
|
2007-03-25 23:07:15 +08:00
|
|
|
SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
|
|
|
|
else
|
|
|
|
SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
|
|
|
|
|
|
|
|
unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
|
2008-03-28 03:56:19 +08:00
|
|
|
SDOperand CopyTo = DAG.getCopyToReg(getControlRoot(), JumpTableReg, SwitchOp);
|
2007-03-25 23:07:15 +08:00
|
|
|
JT.Reg = JumpTableReg;
|
|
|
|
|
|
|
|
// Emit the range check for the jump table, and branch to the default
|
|
|
|
// block for the switch statement if the value being switched on exceeds
|
|
|
|
// the largest case in the switch.
|
2008-03-10 23:42:14 +08:00
|
|
|
SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
|
2007-03-25 23:07:15 +08:00
|
|
|
DAG.getConstant(JTH.Last-JTH.First,VT),
|
|
|
|
ISD::SETUGT);
|
|
|
|
|
|
|
|
// Set NextBlock to be the MBB immediately after the current one, if any.
|
|
|
|
// This is used to avoid emitting unnecessary branches to the next block.
|
|
|
|
MachineBasicBlock *NextBlock = 0;
|
|
|
|
MachineFunction::iterator BBI = CurMBB;
|
|
|
|
if (++BBI != CurMBB->getParent()->end())
|
|
|
|
NextBlock = BBI;
|
|
|
|
|
|
|
|
SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
|
|
|
|
DAG.getBasicBlock(JT.Default));
|
|
|
|
|
|
|
|
if (JT.MBB == NextBlock)
|
|
|
|
DAG.setRoot(BrCond);
|
|
|
|
else
|
|
|
|
DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
|
2007-04-09 20:31:58 +08:00
|
|
|
DAG.getBasicBlock(JT.MBB)));
|
|
|
|
|
|
|
|
return;
|
2007-03-25 23:07:15 +08:00
|
|
|
}
|
|
|
|
|
2007-04-09 20:31:58 +08:00
|
|
|
/// visitBitTestHeader - This function emits necessary code to produce value
|
|
|
|
/// suitable for "bit tests"
|
|
|
|
void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) {
|
|
|
|
// Subtract the minimum value
|
|
|
|
SDOperand SwitchOp = getValue(B.SValue);
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT VT = SwitchOp.getValueType();
|
2007-04-09 20:31:58 +08:00
|
|
|
SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
|
|
|
|
DAG.getConstant(B.First, VT));
|
|
|
|
|
|
|
|
// Check range
|
2008-03-10 23:42:14 +08:00
|
|
|
SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
|
2007-04-09 20:31:58 +08:00
|
|
|
DAG.getConstant(B.Range, VT),
|
|
|
|
ISD::SETUGT);
|
|
|
|
|
|
|
|
SDOperand ShiftOp;
|
2008-06-09 04:54:56 +08:00
|
|
|
if (VT.bitsGT(TLI.getShiftAmountTy()))
|
2007-04-09 20:31:58 +08:00
|
|
|
ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
|
|
|
|
else
|
|
|
|
ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
|
|
|
|
|
|
|
|
// Make desired shift
|
|
|
|
SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
|
|
|
|
DAG.getConstant(1, TLI.getPointerTy()),
|
|
|
|
ShiftOp);
|
|
|
|
|
|
|
|
unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
|
2008-03-28 03:56:19 +08:00
|
|
|
SDOperand CopyTo = DAG.getCopyToReg(getControlRoot(), SwitchReg, SwitchVal);
|
2007-04-09 20:31:58 +08:00
|
|
|
B.Reg = SwitchReg;
|
|
|
|
|
|
|
|
// Set NextBlock to be the MBB immediately after the current one, if any.
|
|
|
|
// This is used to avoid emitting unnecessary branches to the next block.
|
|
|
|
MachineBasicBlock *NextBlock = 0;
|
|
|
|
MachineFunction::iterator BBI = CurMBB;
|
|
|
|
if (++BBI != CurMBB->getParent()->end())
|
|
|
|
NextBlock = BBI;
|
|
|
|
|
|
|
|
MachineBasicBlock* MBB = B.Cases[0].ThisBB;
|
2008-06-07 08:00:23 +08:00
|
|
|
|
|
|
|
CurMBB->addSuccessor(B.Default);
|
|
|
|
CurMBB->addSuccessor(MBB);
|
|
|
|
|
|
|
|
SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
|
|
|
|
DAG.getBasicBlock(B.Default));
|
|
|
|
|
2007-04-09 20:31:58 +08:00
|
|
|
if (MBB == NextBlock)
|
|
|
|
DAG.setRoot(BrRange);
|
|
|
|
else
|
|
|
|
DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
|
|
|
|
DAG.getBasicBlock(MBB)));
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// visitBitTestCase - this function produces one "bit test"
|
|
|
|
void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
|
|
|
|
unsigned Reg,
|
|
|
|
SelectionDAGISel::BitTestCase &B) {
|
|
|
|
// Emit bit tests and jumps
|
2008-03-28 03:56:19 +08:00
|
|
|
SDOperand SwitchVal = DAG.getCopyFromReg(getControlRoot(), Reg, TLI.getPointerTy());
|
2007-04-09 20:31:58 +08:00
|
|
|
|
|
|
|
SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(),
|
|
|
|
SwitchVal,
|
|
|
|
DAG.getConstant(B.Mask,
|
|
|
|
TLI.getPointerTy()));
|
2008-03-10 23:42:14 +08:00
|
|
|
SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp), AndOp,
|
2007-04-09 20:31:58 +08:00
|
|
|
DAG.getConstant(0, TLI.getPointerTy()),
|
|
|
|
ISD::SETNE);
|
2008-06-07 08:00:23 +08:00
|
|
|
|
|
|
|
CurMBB->addSuccessor(B.TargetBB);
|
|
|
|
CurMBB->addSuccessor(NextMBB);
|
|
|
|
|
2008-03-28 03:56:19 +08:00
|
|
|
SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(),
|
2007-04-09 20:31:58 +08:00
|
|
|
AndCmp, DAG.getBasicBlock(B.TargetBB));
|
|
|
|
|
|
|
|
// Set NextBlock to be the MBB immediately after the current one, if any.
|
|
|
|
// This is used to avoid emitting unnecessary branches to the next block.
|
|
|
|
MachineBasicBlock *NextBlock = 0;
|
|
|
|
MachineFunction::iterator BBI = CurMBB;
|
|
|
|
if (++BBI != CurMBB->getParent()->end())
|
|
|
|
NextBlock = BBI;
|
|
|
|
|
|
|
|
if (NextMBB == NextBlock)
|
|
|
|
DAG.setRoot(BrAnd);
|
|
|
|
else
|
|
|
|
DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
|
|
|
|
DAG.getBasicBlock(NextMBB)));
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
2007-03-25 23:07:15 +08:00
|
|
|
|
2007-02-22 06:53:45 +08:00
|
|
|
void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
|
|
|
|
// Retrieve successors.
|
|
|
|
MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
|
2007-06-13 13:51:31 +08:00
|
|
|
MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
|
2007-06-06 18:05:18 +08:00
|
|
|
|
2007-12-18 02:08:19 +08:00
|
|
|
if (isa<InlineAsm>(I.getCalledValue()))
|
|
|
|
visitInlineAsm(&I);
|
|
|
|
else
|
2007-12-19 17:48:52 +08:00
|
|
|
LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad);
|
2007-06-13 13:51:31 +08:00
|
|
|
|
|
|
|
// If the value of the invoke is used outside of its defining block, make it
|
|
|
|
// available as a virtual register.
|
|
|
|
if (!I.use_empty()) {
|
|
|
|
DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
|
|
|
|
if (VMI != FuncInfo.ValueMap.end())
|
2008-03-28 03:56:19 +08:00
|
|
|
CopyValueToVirtualRegister(&I, VMI->second);
|
2007-06-13 13:51:31 +08:00
|
|
|
}
|
2007-06-06 18:05:18 +08:00
|
|
|
|
2007-06-13 13:51:31 +08:00
|
|
|
// Update successor info
|
|
|
|
CurMBB->addSuccessor(Return);
|
|
|
|
CurMBB->addSuccessor(LandingPad);
|
2008-06-07 08:00:23 +08:00
|
|
|
|
|
|
|
// Drop into normal successor.
|
|
|
|
DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
|
|
|
|
DAG.getBasicBlock(Return)));
|
2007-02-22 06:53:45 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
|
|
|
|
}
|
|
|
|
|
2007-04-05 05:14:49 +08:00
|
|
|
/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
|
2007-03-27 19:29:11 +08:00
|
|
|
/// small case ranges).
|
2007-03-27 20:05:48 +08:00
|
|
|
bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
|
2007-03-27 19:29:11 +08:00
|
|
|
CaseRecVector& WorkList,
|
|
|
|
Value* SV,
|
|
|
|
MachineBasicBlock* Default) {
|
2007-03-27 20:05:48 +08:00
|
|
|
Case& BackCase = *(CR.Range.second-1);
|
|
|
|
|
|
|
|
// Size is the number of Cases represented by this range.
|
|
|
|
unsigned Size = CR.Range.second - CR.Range.first;
|
2007-04-09 20:31:58 +08:00
|
|
|
if (Size > 3)
|
2007-03-27 20:05:48 +08:00
|
|
|
return false;
|
2007-04-05 05:14:49 +08:00
|
|
|
|
2007-03-27 19:29:11 +08:00
|
|
|
// Get the MachineFunction which holds the current MBB. This is used when
|
|
|
|
// inserting any additional MBBs necessary to represent the switch.
|
|
|
|
MachineFunction *CurMF = CurMBB->getParent();
|
|
|
|
|
|
|
|
// Figure out which block is immediately after the current one.
|
|
|
|
MachineBasicBlock *NextBlock = 0;
|
|
|
|
MachineFunction::iterator BBI = CR.CaseBB;
|
|
|
|
|
|
|
|
if (++BBI != CurMBB->getParent()->end())
|
|
|
|
NextBlock = BBI;
|
|
|
|
|
|
|
|
// TODO: If any two of the cases has the same destination, and if one value
|
|
|
|
// is the same as the other, but has one bit unset that the other has set,
|
|
|
|
// use bit manipulation to do two compares at once. For example:
|
|
|
|
// "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
|
|
|
|
|
|
|
|
// Rearrange the case blocks so that the last one falls through if possible.
|
2007-04-05 05:14:49 +08:00
|
|
|
if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
|
2007-03-27 19:29:11 +08:00
|
|
|
// The last case block won't fall through into 'NextBlock' if we emit the
|
|
|
|
// branches in this order. See if rearranging a case value would help.
|
|
|
|
for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
|
2007-04-05 05:14:49 +08:00
|
|
|
if (I->BB == NextBlock) {
|
2007-03-27 19:29:11 +08:00
|
|
|
std::swap(*I, BackCase);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Create a CaseBlock record representing a conditional branch to
|
|
|
|
// the Case's target mbb if the value being switched on SV is equal
|
|
|
|
// to C.
|
|
|
|
MachineBasicBlock *CurBlock = CR.CaseBB;
|
|
|
|
for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
|
|
|
|
MachineBasicBlock *FallThrough;
|
|
|
|
if (I != E-1) {
|
|
|
|
FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock());
|
|
|
|
CurMF->getBasicBlockList().insert(BBI, FallThrough);
|
|
|
|
} else {
|
|
|
|
// If the last case doesn't match, go to the default block.
|
|
|
|
FallThrough = Default;
|
|
|
|
}
|
2007-04-05 05:14:49 +08:00
|
|
|
|
|
|
|
Value *RHS, *LHS, *MHS;
|
|
|
|
ISD::CondCode CC;
|
|
|
|
if (I->High == I->Low) {
|
|
|
|
// This is just small small case range :) containing exactly 1 case
|
|
|
|
CC = ISD::SETEQ;
|
|
|
|
LHS = SV; RHS = I->High; MHS = NULL;
|
|
|
|
} else {
|
|
|
|
CC = ISD::SETLE;
|
|
|
|
LHS = I->Low; MHS = SV; RHS = I->High;
|
|
|
|
}
|
|
|
|
SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS,
|
|
|
|
I->BB, FallThrough, CurBlock);
|
2007-03-27 19:29:11 +08:00
|
|
|
|
|
|
|
// If emitting the first comparison, just call visitSwitchCase to emit the
|
|
|
|
// code into the current block. Otherwise, push the CaseBlock onto the
|
|
|
|
// vector to be later processed by SDISel, and insert the node's MBB
|
|
|
|
// before the next MBB.
|
|
|
|
if (CurBlock == CurMBB)
|
|
|
|
visitSwitchCase(CB);
|
|
|
|
else
|
|
|
|
SwitchCases.push_back(CB);
|
|
|
|
|
|
|
|
CurBlock = FallThrough;
|
|
|
|
}
|
2007-03-27 20:05:48 +08:00
|
|
|
|
|
|
|
return true;
|
2007-03-27 19:29:11 +08:00
|
|
|
}
|
|
|
|
|
2007-05-10 04:07:08 +08:00
|
|
|
static inline bool areJTsAllowed(const TargetLowering &TLI) {
|
|
|
|
return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
|
|
|
|
TLI.isOperationLegal(ISD::BRIND, MVT::Other));
|
|
|
|
}
|
|
|
|
|
2007-03-27 19:29:11 +08:00
|
|
|
/// handleJTSwitchCase - Emit jumptable for current switch case range
|
2007-03-27 20:05:48 +08:00
|
|
|
bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
|
2007-03-27 19:29:11 +08:00
|
|
|
CaseRecVector& WorkList,
|
|
|
|
Value* SV,
|
|
|
|
MachineBasicBlock* Default) {
|
2007-03-27 20:05:48 +08:00
|
|
|
Case& FrontCase = *CR.Range.first;
|
|
|
|
Case& BackCase = *(CR.Range.second-1);
|
|
|
|
|
2007-04-05 05:14:49 +08:00
|
|
|
int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
|
|
|
|
int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
|
|
|
|
|
|
|
|
uint64_t TSize = 0;
|
|
|
|
for (CaseItr I = CR.Range.first, E = CR.Range.second;
|
|
|
|
I!=E; ++I)
|
|
|
|
TSize += I->size();
|
2007-03-27 20:05:48 +08:00
|
|
|
|
2007-05-10 04:07:08 +08:00
|
|
|
if (!areJTsAllowed(TLI) || TSize <= 3)
|
2007-03-27 20:05:48 +08:00
|
|
|
return false;
|
|
|
|
|
2007-04-05 05:14:49 +08:00
|
|
|
double Density = (double)TSize / (double)((Last - First) + 1ULL);
|
|
|
|
if (Density < 0.4)
|
2007-03-27 20:05:48 +08:00
|
|
|
return false;
|
|
|
|
|
2007-04-05 05:14:49 +08:00
|
|
|
DOUT << "Lowering jump table\n"
|
|
|
|
<< "First entry: " << First << ". Last entry: " << Last << "\n"
|
2007-04-09 20:31:58 +08:00
|
|
|
<< "Size: " << TSize << ". Density: " << Density << "\n\n";
|
2007-04-05 05:14:49 +08:00
|
|
|
|
2007-03-27 19:29:11 +08:00
|
|
|
// Get the MachineFunction which holds the current MBB. This is used when
|
|
|
|
// inserting any additional MBBs necessary to represent the switch.
|
2007-03-27 20:05:48 +08:00
|
|
|
MachineFunction *CurMF = CurMBB->getParent();
|
2007-03-27 19:29:11 +08:00
|
|
|
|
|
|
|
// Figure out which block is immediately after the current one.
|
|
|
|
MachineBasicBlock *NextBlock = 0;
|
|
|
|
MachineFunction::iterator BBI = CR.CaseBB;
|
|
|
|
|
|
|
|
if (++BBI != CurMBB->getParent()->end())
|
|
|
|
NextBlock = BBI;
|
|
|
|
|
|
|
|
const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
|
|
|
|
|
|
|
|
// Create a new basic block to hold the code for loading the address
|
|
|
|
// of the jump table, and jumping to it. Update successor information;
|
|
|
|
// we will either branch to the default case for the switch, or the jump
|
|
|
|
// table.
|
|
|
|
MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
|
|
|
|
CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
|
|
|
|
CR.CaseBB->addSuccessor(Default);
|
|
|
|
CR.CaseBB->addSuccessor(JumpTableBB);
|
|
|
|
|
|
|
|
// Build a vector of destination BBs, corresponding to each target
|
2007-04-09 20:31:58 +08:00
|
|
|
// of the jump table. If the value of the jump table slot corresponds to
|
2007-03-27 19:29:11 +08:00
|
|
|
// a case statement, push the case's BB onto the vector, otherwise, push
|
|
|
|
// the default BB.
|
|
|
|
std::vector<MachineBasicBlock*> DestBBs;
|
|
|
|
int64_t TEI = First;
|
2007-04-05 05:14:49 +08:00
|
|
|
for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
|
|
|
|
int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
|
|
|
|
int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
|
|
|
|
|
|
|
|
if ((Low <= TEI) && (TEI <= High)) {
|
|
|
|
DestBBs.push_back(I->BB);
|
|
|
|
if (TEI==High)
|
|
|
|
++I;
|
2007-03-27 19:29:11 +08:00
|
|
|
} else {
|
|
|
|
DestBBs.push_back(Default);
|
|
|
|
}
|
2007-04-05 05:14:49 +08:00
|
|
|
}
|
2007-03-27 19:29:11 +08:00
|
|
|
|
|
|
|
// Update successor info. Add one edge to each unique successor.
|
2007-04-05 05:14:49 +08:00
|
|
|
BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
|
2007-03-27 19:29:11 +08:00
|
|
|
for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
|
|
|
|
E = DestBBs.end(); I != E; ++I) {
|
|
|
|
if (!SuccsHandled[(*I)->getNumber()]) {
|
|
|
|
SuccsHandled[(*I)->getNumber()] = true;
|
|
|
|
JumpTableBB->addSuccessor(*I);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Create a jump table index for this jump table, or return an existing
|
|
|
|
// one.
|
|
|
|
unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
|
|
|
|
|
|
|
|
// Set the jump table information so that we can codegen it as a second
|
|
|
|
// MachineBasicBlock
|
2007-04-24 09:24:20 +08:00
|
|
|
SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default);
|
2007-03-27 19:29:11 +08:00
|
|
|
SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB,
|
|
|
|
(CR.CaseBB == CurMBB));
|
|
|
|
if (CR.CaseBB == CurMBB)
|
|
|
|
visitJumpTableHeader(JT, JTH);
|
|
|
|
|
|
|
|
JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT));
|
|
|
|
|
2007-03-27 20:05:48 +08:00
|
|
|
return true;
|
2007-03-27 19:29:11 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/// handleBTSplitSwitchCase - emit comparison and split binary search tree into
|
|
|
|
/// 2 subtrees.
|
2007-03-27 20:05:48 +08:00
|
|
|
bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
|
2007-03-27 19:29:11 +08:00
|
|
|
CaseRecVector& WorkList,
|
|
|
|
Value* SV,
|
|
|
|
MachineBasicBlock* Default) {
|
|
|
|
// Get the MachineFunction which holds the current MBB. This is used when
|
|
|
|
// inserting any additional MBBs necessary to represent the switch.
|
|
|
|
MachineFunction *CurMF = CurMBB->getParent();
|
|
|
|
|
|
|
|
// Figure out which block is immediately after the current one.
|
|
|
|
MachineBasicBlock *NextBlock = 0;
|
|
|
|
MachineFunction::iterator BBI = CR.CaseBB;
|
|
|
|
|
|
|
|
if (++BBI != CurMBB->getParent()->end())
|
|
|
|
NextBlock = BBI;
|
|
|
|
|
|
|
|
Case& FrontCase = *CR.Range.first;
|
|
|
|
Case& BackCase = *(CR.Range.second-1);
|
|
|
|
const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
|
|
|
|
|
|
|
|
// Size is the number of Cases represented by this range.
|
|
|
|
unsigned Size = CR.Range.second - CR.Range.first;
|
|
|
|
|
2007-04-05 05:14:49 +08:00
|
|
|
int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
|
|
|
|
int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
|
2007-04-09 20:31:58 +08:00
|
|
|
double FMetric = 0;
|
2007-04-05 05:14:49 +08:00
|
|
|
CaseItr Pivot = CR.Range.first + Size/2;
|
2007-03-27 19:29:11 +08:00
|
|
|
|
|
|
|
// Select optimal pivot, maximizing sum density of LHS and RHS. This will
|
|
|
|
// (heuristically) allow us to emit JumpTable's later.
|
2007-04-05 05:14:49 +08:00
|
|
|
uint64_t TSize = 0;
|
|
|
|
for (CaseItr I = CR.Range.first, E = CR.Range.second;
|
|
|
|
I!=E; ++I)
|
|
|
|
TSize += I->size();
|
|
|
|
|
|
|
|
uint64_t LSize = FrontCase.size();
|
|
|
|
uint64_t RSize = TSize-LSize;
|
2007-04-09 20:31:58 +08:00
|
|
|
DOUT << "Selecting best pivot: \n"
|
|
|
|
<< "First: " << First << ", Last: " << Last <<"\n"
|
|
|
|
<< "LSize: " << LSize << ", RSize: " << RSize << "\n";
|
2007-03-27 19:29:11 +08:00
|
|
|
for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
|
2007-04-05 05:14:49 +08:00
|
|
|
J!=E; ++I, ++J) {
|
|
|
|
int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
|
|
|
|
int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
|
2007-04-09 20:31:58 +08:00
|
|
|
assert((RBegin-LEnd>=1) && "Invalid case distance");
|
2007-03-27 19:29:11 +08:00
|
|
|
double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
|
|
|
|
double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
|
2007-04-10 05:57:03 +08:00
|
|
|
double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity);
|
2007-04-09 20:31:58 +08:00
|
|
|
// Should always split in some non-trivial place
|
|
|
|
DOUT <<"=>Step\n"
|
|
|
|
<< "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n"
|
|
|
|
<< "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n"
|
|
|
|
<< "Metric: " << Metric << "\n";
|
|
|
|
if (FMetric < Metric) {
|
2007-03-27 19:29:11 +08:00
|
|
|
Pivot = J;
|
2007-04-09 20:31:58 +08:00
|
|
|
FMetric = Metric;
|
|
|
|
DOUT << "Current metric set to: " << FMetric << "\n";
|
2007-03-27 19:29:11 +08:00
|
|
|
}
|
2007-04-05 05:14:49 +08:00
|
|
|
|
|
|
|
LSize += J->size();
|
|
|
|
RSize -= J->size();
|
2007-03-27 19:29:11 +08:00
|
|
|
}
|
2007-05-10 04:07:08 +08:00
|
|
|
if (areJTsAllowed(TLI)) {
|
|
|
|
// If our case is dense we *really* should handle it earlier!
|
|
|
|
assert((FMetric > 0) && "Should handle dense range earlier!");
|
|
|
|
} else {
|
|
|
|
Pivot = CR.Range.first + Size/2;
|
|
|
|
}
|
2007-03-27 19:29:11 +08:00
|
|
|
|
|
|
|
CaseRange LHSR(CR.Range.first, Pivot);
|
|
|
|
CaseRange RHSR(Pivot, CR.Range.second);
|
2007-04-05 05:14:49 +08:00
|
|
|
Constant *C = Pivot->Low;
|
2007-03-27 19:29:11 +08:00
|
|
|
MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
|
|
|
|
|
|
|
|
// We know that we branch to the LHS if the Value being switched on is
|
|
|
|
// less than the Pivot value, C. We use this to optimize our binary
|
|
|
|
// tree a bit, by recognizing that if SV is greater than or equal to the
|
|
|
|
// LHS's Case Value, and that Case Value is exactly one less than the
|
|
|
|
// Pivot's Value, then we can branch directly to the LHS's Target,
|
|
|
|
// rather than creating a leaf node for it.
|
|
|
|
if ((LHSR.second - LHSR.first) == 1 &&
|
2007-04-05 05:14:49 +08:00
|
|
|
LHSR.first->High == CR.GE &&
|
|
|
|
cast<ConstantInt>(C)->getSExtValue() ==
|
|
|
|
(cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
|
|
|
|
TrueBB = LHSR.first->BB;
|
2007-03-27 19:29:11 +08:00
|
|
|
} else {
|
|
|
|
TrueBB = new MachineBasicBlock(LLVMBB);
|
|
|
|
CurMF->getBasicBlockList().insert(BBI, TrueBB);
|
|
|
|
WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
|
|
|
|
}
|
|
|
|
|
|
|
|
// Similar to the optimization above, if the Value being switched on is
|
|
|
|
// known to be less than the Constant CR.LT, and the current Case Value
|
|
|
|
// is CR.LT - 1, then we can branch directly to the target block for
|
|
|
|
// the current Case Value, rather than emitting a RHS leaf node for it.
|
|
|
|
if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
|
2007-04-05 05:14:49 +08:00
|
|
|
cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
|
|
|
|
(cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
|
|
|
|
FalseBB = RHSR.first->BB;
|
2007-03-27 19:29:11 +08:00
|
|
|
} else {
|
|
|
|
FalseBB = new MachineBasicBlock(LLVMBB);
|
|
|
|
CurMF->getBasicBlockList().insert(BBI, FalseBB);
|
|
|
|
WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
|
|
|
|
}
|
|
|
|
|
|
|
|
// Create a CaseBlock record representing a conditional branch to
|
|
|
|
// the LHS node if the value being switched on SV is less than C.
|
|
|
|
// Otherwise, branch to LHS.
|
2007-04-05 05:14:49 +08:00
|
|
|
SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL,
|
|
|
|
TrueBB, FalseBB, CR.CaseBB);
|
2007-03-27 19:29:11 +08:00
|
|
|
|
|
|
|
if (CR.CaseBB == CurMBB)
|
|
|
|
visitSwitchCase(CB);
|
|
|
|
else
|
|
|
|
SwitchCases.push_back(CB);
|
2007-03-27 20:05:48 +08:00
|
|
|
|
|
|
|
return true;
|
2007-03-27 19:29:11 +08:00
|
|
|
}
|
|
|
|
|
2007-04-09 20:31:58 +08:00
|
|
|
/// handleBitTestsSwitchCase - if current case range has few destination and
|
|
|
|
/// range span less, than machine word bitwidth, encode case range into series
|
|
|
|
/// of masks and emit bit tests with these masks.
|
|
|
|
bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
|
|
|
|
CaseRecVector& WorkList,
|
|
|
|
Value* SV,
|
2007-04-14 10:26:56 +08:00
|
|
|
MachineBasicBlock* Default){
|
2008-06-06 20:08:01 +08:00
|
|
|
unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits();
|
2007-04-09 20:31:58 +08:00
|
|
|
|
|
|
|
Case& FrontCase = *CR.Range.first;
|
|
|
|
Case& BackCase = *(CR.Range.second-1);
|
|
|
|
|
|
|
|
// Get the MachineFunction which holds the current MBB. This is used when
|
|
|
|
// inserting any additional MBBs necessary to represent the switch.
|
|
|
|
MachineFunction *CurMF = CurMBB->getParent();
|
|
|
|
|
|
|
|
unsigned numCmps = 0;
|
|
|
|
for (CaseItr I = CR.Range.first, E = CR.Range.second;
|
|
|
|
I!=E; ++I) {
|
|
|
|
// Single case counts one, case range - two.
|
|
|
|
if (I->Low == I->High)
|
|
|
|
numCmps +=1;
|
|
|
|
else
|
|
|
|
numCmps +=2;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Count unique destinations
|
|
|
|
SmallSet<MachineBasicBlock*, 4> Dests;
|
|
|
|
for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
|
|
|
|
Dests.insert(I->BB);
|
|
|
|
if (Dests.size() > 3)
|
|
|
|
// Don't bother the code below, if there are too much unique destinations
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
DOUT << "Total number of unique destinations: " << Dests.size() << "\n"
|
|
|
|
<< "Total number of comparisons: " << numCmps << "\n";
|
|
|
|
|
|
|
|
// Compute span of values.
|
|
|
|
Constant* minValue = FrontCase.Low;
|
|
|
|
Constant* maxValue = BackCase.High;
|
|
|
|
uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() -
|
|
|
|
cast<ConstantInt>(minValue)->getSExtValue();
|
|
|
|
DOUT << "Compare range: " << range << "\n"
|
|
|
|
<< "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n"
|
|
|
|
<< "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n";
|
|
|
|
|
2007-04-27 04:44:04 +08:00
|
|
|
if (range>=IntPtrBits ||
|
2007-04-09 20:31:58 +08:00
|
|
|
(!(Dests.size() == 1 && numCmps >= 3) &&
|
|
|
|
!(Dests.size() == 2 && numCmps >= 5) &&
|
|
|
|
!(Dests.size() >= 3 && numCmps >= 6)))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
DOUT << "Emitting bit tests\n";
|
|
|
|
int64_t lowBound = 0;
|
|
|
|
|
|
|
|
// Optimize the case where all the case values fit in a
|
|
|
|
// word without having to subtract minValue. In this case,
|
|
|
|
// we can optimize away the subtraction.
|
|
|
|
if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
|
2007-04-14 21:25:55 +08:00
|
|
|
cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) {
|
2007-04-09 20:31:58 +08:00
|
|
|
range = cast<ConstantInt>(maxValue)->getSExtValue();
|
|
|
|
} else {
|
|
|
|
lowBound = cast<ConstantInt>(minValue)->getSExtValue();
|
|
|
|
}
|
|
|
|
|
|
|
|
CaseBitsVector CasesBits;
|
|
|
|
unsigned i, count = 0;
|
|
|
|
|
|
|
|
for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
|
|
|
|
MachineBasicBlock* Dest = I->BB;
|
|
|
|
for (i = 0; i < count; ++i)
|
|
|
|
if (Dest == CasesBits[i].BB)
|
|
|
|
break;
|
|
|
|
|
|
|
|
if (i == count) {
|
|
|
|
assert((count < 3) && "Too much destinations to test!");
|
|
|
|
CasesBits.push_back(CaseBits(0, Dest, 0));
|
|
|
|
count++;
|
|
|
|
}
|
|
|
|
|
|
|
|
uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound;
|
|
|
|
uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
|
|
|
|
|
|
|
|
for (uint64_t j = lo; j <= hi; j++) {
|
2007-04-14 21:25:55 +08:00
|
|
|
CasesBits[i].Mask |= 1ULL << j;
|
2007-04-09 20:31:58 +08:00
|
|
|
CasesBits[i].Bits++;
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
|
|
|
|
|
|
|
|
SelectionDAGISel::BitTestInfo BTC;
|
|
|
|
|
|
|
|
// Figure out which block is immediately after the current one.
|
|
|
|
MachineFunction::iterator BBI = CR.CaseBB;
|
|
|
|
++BBI;
|
|
|
|
|
|
|
|
const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
|
|
|
|
|
|
|
|
DOUT << "Cases:\n";
|
|
|
|
for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
|
|
|
|
DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits
|
|
|
|
<< ", BB: " << CasesBits[i].BB << "\n";
|
|
|
|
|
|
|
|
MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB);
|
|
|
|
CurMF->getBasicBlockList().insert(BBI, CaseBB);
|
|
|
|
BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask,
|
|
|
|
CaseBB,
|
|
|
|
CasesBits[i].BB));
|
|
|
|
}
|
|
|
|
|
|
|
|
SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV,
|
2007-04-09 22:32:59 +08:00
|
|
|
-1U, (CR.CaseBB == CurMBB),
|
2007-04-09 20:31:58 +08:00
|
|
|
CR.CaseBB, Default, BTC);
|
|
|
|
|
|
|
|
if (CR.CaseBB == CurMBB)
|
|
|
|
visitBitTestHeader(BTB);
|
|
|
|
|
|
|
|
BitTestCases.push_back(BTB);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2008-03-28 03:56:19 +08:00
|
|
|
/// Clusterify - Transform simple list of Cases into list of CaseRange's
|
2007-04-05 05:14:49 +08:00
|
|
|
unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
|
|
|
|
const SwitchInst& SI) {
|
|
|
|
unsigned numCmps = 0;
|
|
|
|
|
|
|
|
// Start with "simple" cases
|
|
|
|
for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
|
|
|
|
MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
|
|
|
|
Cases.push_back(Case(SI.getSuccessorValue(i),
|
|
|
|
SI.getSuccessorValue(i),
|
|
|
|
SMBB));
|
|
|
|
}
|
2007-11-27 14:14:32 +08:00
|
|
|
std::sort(Cases.begin(), Cases.end(), CaseCmp());
|
2007-04-05 05:14:49 +08:00
|
|
|
|
|
|
|
// Merge case into clusters
|
|
|
|
if (Cases.size()>=2)
|
2007-06-29 11:42:23 +08:00
|
|
|
// Must recompute end() each iteration because it may be
|
|
|
|
// invalidated by erase if we hold on to it
|
2007-11-24 15:07:01 +08:00
|
|
|
for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) {
|
2007-04-05 05:14:49 +08:00
|
|
|
int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
|
|
|
|
int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
|
|
|
|
MachineBasicBlock* nextBB = J->BB;
|
|
|
|
MachineBasicBlock* currentBB = I->BB;
|
|
|
|
|
|
|
|
// If the two neighboring cases go to the same destination, merge them
|
|
|
|
// into a single case.
|
|
|
|
if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
|
|
|
|
I->High = J->High;
|
|
|
|
J = Cases.erase(J);
|
|
|
|
} else {
|
|
|
|
I = J++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
|
|
|
|
if (I->Low != I->High)
|
|
|
|
// A range counts double, since it requires two compares.
|
|
|
|
++numCmps;
|
|
|
|
}
|
|
|
|
|
|
|
|
return numCmps;
|
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
|
2006-03-27 09:32:24 +08:00
|
|
|
// Figure out which block is immediately after the current one.
|
|
|
|
MachineBasicBlock *NextBlock = 0;
|
|
|
|
MachineFunction::iterator BBI = CurMBB;
|
2006-10-20 05:46:38 +08:00
|
|
|
|
2007-04-05 05:14:49 +08:00
|
|
|
MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
|
2006-10-23 05:36:53 +08:00
|
|
|
|
2006-03-27 09:32:24 +08:00
|
|
|
// If there is only the default destination, branch to it if it is not the
|
|
|
|
// next basic block. Otherwise, just fall through.
|
2007-04-05 05:14:49 +08:00
|
|
|
if (SI.getNumOperands() == 2) {
|
2006-03-27 09:32:24 +08:00
|
|
|
// Update machine-CFG edges.
|
2006-10-20 05:46:38 +08:00
|
|
|
|
2006-03-27 09:32:24 +08:00
|
|
|
// If this is not a fall-through branch, emit the branch.
|
2008-06-07 08:00:23 +08:00
|
|
|
CurMBB->addSuccessor(Default);
|
2006-10-23 05:36:53 +08:00
|
|
|
if (Default != NextBlock)
|
2008-03-28 03:56:19 +08:00
|
|
|
DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
|
2006-10-23 05:36:53 +08:00
|
|
|
DAG.getBasicBlock(Default)));
|
2008-06-07 08:00:23 +08:00
|
|
|
|
2006-03-27 09:32:24 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
// If there are any non-default case statements, create a vector of Cases
|
|
|
|
// representing each one, and sort the vector so that we can efficiently
|
|
|
|
// create a binary search tree from them.
|
2007-04-05 05:14:49 +08:00
|
|
|
CaseVector Cases;
|
|
|
|
unsigned numCmps = Clusterify(Cases, SI);
|
|
|
|
DOUT << "Clusterify finished. Total clusters: " << Cases.size()
|
|
|
|
<< ". Total compares: " << numCmps << "\n";
|
2006-10-20 05:46:38 +08:00
|
|
|
|
2006-03-27 09:32:24 +08:00
|
|
|
// Get the Value to be switched on and default basic blocks, which will be
|
|
|
|
// inserted into CaseBlock records, representing basic blocks in the binary
|
|
|
|
// search tree.
|
2007-04-05 05:14:49 +08:00
|
|
|
Value *SV = SI.getOperand(0);
|
2006-04-23 02:53:45 +08:00
|
|
|
|
2007-03-25 23:07:15 +08:00
|
|
|
// Push the initial CaseRec onto the worklist
|
2007-03-27 19:29:11 +08:00
|
|
|
CaseRecVector WorkList;
|
2007-03-25 23:07:15 +08:00
|
|
|
WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
|
|
|
|
|
|
|
|
while (!WorkList.empty()) {
|
|
|
|
// Grab a record representing a case range to process off the worklist
|
|
|
|
CaseRec CR = WorkList.back();
|
|
|
|
WorkList.pop_back();
|
|
|
|
|
2007-04-09 20:31:58 +08:00
|
|
|
if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
|
|
|
|
continue;
|
|
|
|
|
2007-03-25 23:07:15 +08:00
|
|
|
// If the range has few cases (two or less) emit a series of specific
|
|
|
|
// tests.
|
2007-03-27 20:05:48 +08:00
|
|
|
if (handleSmallSwitchRange(CR, WorkList, SV, Default))
|
|
|
|
continue;
|
|
|
|
|
2007-04-09 20:31:58 +08:00
|
|
|
// If the switch has more than 5 blocks, and at least 40% dense, and the
|
2007-03-25 23:07:15 +08:00
|
|
|
// target supports indirect branches, then emit a jump table rather than
|
|
|
|
// lowering the switch to a binary tree of conditional branches.
|
2007-03-27 20:05:48 +08:00
|
|
|
if (handleJTSwitchCase(CR, WorkList, SV, Default))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
// Emit binary tree. We need to pick a pivot, and push left and right ranges
|
|
|
|
// onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
|
|
|
|
handleBTSplitSwitchCase(CR, WorkList, SV, Default);
|
2006-03-27 09:32:24 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-03-25 23:07:15 +08:00
|
|
|
|
2005-04-02 13:04:50 +08:00
|
|
|
void SelectionDAGLowering::visitSub(User &I) {
|
|
|
|
// -0.0 - X --> fneg
|
2007-01-21 08:29:26 +08:00
|
|
|
const Type *Ty = I.getType();
|
2007-02-15 10:26:10 +08:00
|
|
|
if (isa<VectorType>(Ty)) {
|
2007-06-26 00:23:39 +08:00
|
|
|
if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
|
|
|
|
const VectorType *DestTy = cast<VectorType>(I.getType());
|
|
|
|
const Type *ElTy = DestTy->getElementType();
|
2007-06-30 05:44:35 +08:00
|
|
|
if (ElTy->isFloatingPoint()) {
|
|
|
|
unsigned VL = DestTy->getNumElements();
|
2007-09-15 06:26:36 +08:00
|
|
|
std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
|
2007-06-30 05:44:35 +08:00
|
|
|
Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
|
|
|
|
if (CV == CNZ) {
|
|
|
|
SDOperand Op2 = getValue(I.getOperand(1));
|
|
|
|
setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
|
|
|
|
return;
|
|
|
|
}
|
2007-06-26 00:23:39 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (Ty->isFloatingPoint()) {
|
2005-09-29 06:28:18 +08:00
|
|
|
if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
|
2007-09-15 06:26:36 +08:00
|
|
|
if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
|
2005-09-29 06:28:18 +08:00
|
|
|
SDOperand Op2 = getValue(I.getOperand(1));
|
|
|
|
setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
|
|
|
|
return;
|
|
|
|
}
|
2007-06-26 00:23:39 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
|
2005-04-02 13:04:50 +08:00
|
|
|
}
|
|
|
|
|
2007-06-26 00:23:39 +08:00
|
|
|
void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
|
2005-01-07 15:47:53 +08:00
|
|
|
SDOperand Op1 = getValue(I.getOperand(0));
|
|
|
|
SDOperand Op2 = getValue(I.getOperand(1));
|
2007-01-21 08:29:26 +08:00
|
|
|
|
|
|
|
setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
|
2006-10-26 14:15:43 +08:00
|
|
|
}
|
|
|
|
|
2005-11-18 15:42:56 +08:00
|
|
|
void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
|
|
|
|
SDOperand Op1 = getValue(I.getOperand(0));
|
|
|
|
SDOperand Op2 = getValue(I.getOperand(1));
|
|
|
|
|
2008-06-09 04:54:56 +08:00
|
|
|
if (TLI.getShiftAmountTy().bitsLT(Op2.getValueType()))
|
2007-02-02 10:16:23 +08:00
|
|
|
Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
|
2008-06-09 04:54:56 +08:00
|
|
|
else if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType()))
|
2007-02-02 10:16:23 +08:00
|
|
|
Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
|
2005-11-18 15:42:56 +08:00
|
|
|
|
2005-01-07 15:47:53 +08:00
|
|
|
setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
|
|
|
|
}
|
|
|
|
|
2006-11-20 09:22:35 +08:00
|
|
|
void SelectionDAGLowering::visitICmp(User &I) {
|
2006-12-23 14:05:41 +08:00
|
|
|
ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
|
|
|
|
if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
|
|
|
|
predicate = IC->getPredicate();
|
|
|
|
else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
|
|
|
|
predicate = ICmpInst::Predicate(IC->getPredicate());
|
|
|
|
SDOperand Op1 = getValue(I.getOperand(0));
|
|
|
|
SDOperand Op2 = getValue(I.getOperand(1));
|
2006-11-20 09:22:35 +08:00
|
|
|
ISD::CondCode Opcode;
|
2006-12-23 14:05:41 +08:00
|
|
|
switch (predicate) {
|
2006-11-20 09:22:35 +08:00
|
|
|
case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
|
|
|
|
case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
|
|
|
|
case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
|
|
|
|
case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
|
|
|
|
case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
|
|
|
|
case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
|
|
|
|
case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
|
|
|
|
case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
|
|
|
|
case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
|
|
|
|
case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
|
|
|
|
default:
|
|
|
|
assert(!"Invalid ICmp predicate value");
|
|
|
|
Opcode = ISD::SETEQ;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
|
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitFCmp(User &I) {
|
2006-12-23 14:05:41 +08:00
|
|
|
FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
|
|
|
|
if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
|
|
|
|
predicate = FC->getPredicate();
|
|
|
|
else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
|
|
|
|
predicate = FCmpInst::Predicate(FC->getPredicate());
|
|
|
|
SDOperand Op1 = getValue(I.getOperand(0));
|
|
|
|
SDOperand Op2 = getValue(I.getOperand(1));
|
|
|
|
ISD::CondCode Condition, FOC, FPC;
|
|
|
|
switch (predicate) {
|
|
|
|
case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
|
|
|
|
case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
|
|
|
|
case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
|
|
|
|
case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
|
|
|
|
case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
|
|
|
|
case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
|
|
|
|
case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
|
2008-05-02 07:40:44 +08:00
|
|
|
case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
|
|
|
|
case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
|
2006-12-23 14:05:41 +08:00
|
|
|
case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
|
|
|
|
case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
|
|
|
|
case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
|
|
|
|
case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
|
|
|
|
case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
|
|
|
|
case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
|
|
|
|
case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
|
2006-11-20 09:22:35 +08:00
|
|
|
default:
|
|
|
|
assert(!"Invalid FCmp predicate value");
|
2006-12-23 14:05:41 +08:00
|
|
|
FOC = FPC = ISD::SETFALSE;
|
2006-11-20 09:22:35 +08:00
|
|
|
break;
|
|
|
|
}
|
2006-12-23 14:05:41 +08:00
|
|
|
if (FiniteOnlyFPMath())
|
|
|
|
Condition = FOC;
|
|
|
|
else
|
|
|
|
Condition = FPC;
|
|
|
|
setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
|
2005-01-07 15:47:53 +08:00
|
|
|
}
|
|
|
|
|
2008-05-13 03:40:03 +08:00
|
|
|
void SelectionDAGLowering::visitVICmp(User &I) {
|
|
|
|
ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
|
|
|
|
if (VICmpInst *IC = dyn_cast<VICmpInst>(&I))
|
|
|
|
predicate = IC->getPredicate();
|
|
|
|
else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
|
|
|
|
predicate = ICmpInst::Predicate(IC->getPredicate());
|
|
|
|
SDOperand Op1 = getValue(I.getOperand(0));
|
|
|
|
SDOperand Op2 = getValue(I.getOperand(1));
|
|
|
|
ISD::CondCode Opcode;
|
|
|
|
switch (predicate) {
|
|
|
|
case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
|
|
|
|
case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
|
|
|
|
case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
|
|
|
|
case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
|
|
|
|
case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
|
|
|
|
case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
|
|
|
|
case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
|
|
|
|
case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
|
|
|
|
case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
|
|
|
|
case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
|
|
|
|
default:
|
|
|
|
assert(!"Invalid ICmp predicate value");
|
|
|
|
Opcode = ISD::SETEQ;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
setValue(&I, DAG.getVSetCC(Op1.getValueType(), Op1, Op2, Opcode));
|
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitVFCmp(User &I) {
|
|
|
|
FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
|
|
|
|
if (VFCmpInst *FC = dyn_cast<VFCmpInst>(&I))
|
|
|
|
predicate = FC->getPredicate();
|
|
|
|
else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
|
|
|
|
predicate = FCmpInst::Predicate(FC->getPredicate());
|
|
|
|
SDOperand Op1 = getValue(I.getOperand(0));
|
|
|
|
SDOperand Op2 = getValue(I.getOperand(1));
|
|
|
|
ISD::CondCode Condition, FOC, FPC;
|
|
|
|
switch (predicate) {
|
|
|
|
case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
|
|
|
|
case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
|
|
|
|
case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
|
|
|
|
case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
|
|
|
|
case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
|
|
|
|
case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
|
|
|
|
case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
|
|
|
|
case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
|
|
|
|
case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
|
|
|
|
case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
|
|
|
|
case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
|
|
|
|
case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
|
|
|
|
case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
|
|
|
|
case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
|
|
|
|
case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
|
|
|
|
case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
|
|
|
|
default:
|
|
|
|
assert(!"Invalid VFCmp predicate value");
|
|
|
|
FOC = FPC = ISD::SETFALSE;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (FiniteOnlyFPMath())
|
|
|
|
Condition = FOC;
|
|
|
|
else
|
|
|
|
Condition = FPC;
|
|
|
|
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT DestVT = TLI.getValueType(I.getType());
|
2008-05-13 03:40:03 +08:00
|
|
|
|
|
|
|
setValue(&I, DAG.getVSetCC(DestVT, Op1, Op2, Condition));
|
|
|
|
}
|
|
|
|
|
2005-01-07 15:47:53 +08:00
|
|
|
void SelectionDAGLowering::visitSelect(User &I) {
|
|
|
|
SDOperand Cond = getValue(I.getOperand(0));
|
|
|
|
SDOperand TrueVal = getValue(I.getOperand(1));
|
|
|
|
SDOperand FalseVal = getValue(I.getOperand(2));
|
2007-06-26 00:23:39 +08:00
|
|
|
setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
|
|
|
|
TrueVal, FalseVal));
|
2005-01-07 15:47:53 +08:00
|
|
|
}
|
|
|
|
|
2006-11-27 09:05:10 +08:00
|
|
|
|
|
|
|
void SelectionDAGLowering::visitTrunc(User &I) {
|
|
|
|
// TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
|
|
|
|
SDOperand N = getValue(I.getOperand(0));
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT DestVT = TLI.getValueType(I.getType());
|
2006-11-27 09:05:10 +08:00
|
|
|
setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
|
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitZExt(User &I) {
|
|
|
|
// ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
|
|
|
|
// ZExt also can't be a cast to bool for same reason. So, nothing much to do
|
|
|
|
SDOperand N = getValue(I.getOperand(0));
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT DestVT = TLI.getValueType(I.getType());
|
2006-11-27 09:05:10 +08:00
|
|
|
setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
|
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitSExt(User &I) {
|
|
|
|
// SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
|
|
|
|
// SExt also can't be a cast to bool for same reason. So, nothing much to do
|
|
|
|
SDOperand N = getValue(I.getOperand(0));
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT DestVT = TLI.getValueType(I.getType());
|
2006-11-27 09:05:10 +08:00
|
|
|
setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
|
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitFPTrunc(User &I) {
|
|
|
|
// FPTrunc is never a no-op cast, no need to check
|
|
|
|
SDOperand N = getValue(I.getOperand(0));
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT DestVT = TLI.getValueType(I.getType());
|
2008-01-17 15:00:52 +08:00
|
|
|
setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0)));
|
2006-11-27 09:05:10 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitFPExt(User &I){
|
|
|
|
// FPTrunc is never a no-op cast, no need to check
|
|
|
|
SDOperand N = getValue(I.getOperand(0));
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT DestVT = TLI.getValueType(I.getType());
|
2006-11-27 09:05:10 +08:00
|
|
|
setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
|
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitFPToUI(User &I) {
|
|
|
|
// FPToUI is never a no-op cast, no need to check
|
|
|
|
SDOperand N = getValue(I.getOperand(0));
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT DestVT = TLI.getValueType(I.getType());
|
2006-11-27 09:05:10 +08:00
|
|
|
setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
|
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitFPToSI(User &I) {
|
|
|
|
// FPToSI is never a no-op cast, no need to check
|
|
|
|
SDOperand N = getValue(I.getOperand(0));
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT DestVT = TLI.getValueType(I.getType());
|
2006-11-27 09:05:10 +08:00
|
|
|
setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
|
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitUIToFP(User &I) {
|
|
|
|
// UIToFP is never a no-op cast, no need to check
|
|
|
|
SDOperand N = getValue(I.getOperand(0));
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT DestVT = TLI.getValueType(I.getType());
|
2006-11-27 09:05:10 +08:00
|
|
|
setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
|
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitSIToFP(User &I){
|
|
|
|
// UIToFP is never a no-op cast, no need to check
|
|
|
|
SDOperand N = getValue(I.getOperand(0));
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT DestVT = TLI.getValueType(I.getType());
|
2006-11-27 09:05:10 +08:00
|
|
|
setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
|
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitPtrToInt(User &I) {
|
|
|
|
// What to do depends on the size of the integer and the size of the pointer.
|
|
|
|
// We can either truncate, zero extend, or no-op, accordingly.
|
2005-01-07 15:47:53 +08:00
|
|
|
SDOperand N = getValue(I.getOperand(0));
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT SrcVT = N.getValueType();
|
|
|
|
MVT DestVT = TLI.getValueType(I.getType());
|
2006-11-27 09:05:10 +08:00
|
|
|
SDOperand Result;
|
2008-06-09 04:54:56 +08:00
|
|
|
if (DestVT.bitsLT(SrcVT))
|
2006-11-27 09:05:10 +08:00
|
|
|
Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
|
|
|
|
else
|
|
|
|
// Note: ZERO_EXTEND can handle cases where the sizes are equal too
|
|
|
|
Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
|
|
|
|
setValue(&I, Result);
|
|
|
|
}
|
2005-01-07 15:47:53 +08:00
|
|
|
|
2006-11-27 09:05:10 +08:00
|
|
|
void SelectionDAGLowering::visitIntToPtr(User &I) {
|
|
|
|
// What to do depends on the size of the integer and the size of the pointer.
|
|
|
|
// We can either truncate, zero extend, or no-op, accordingly.
|
|
|
|
SDOperand N = getValue(I.getOperand(0));
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT SrcVT = N.getValueType();
|
|
|
|
MVT DestVT = TLI.getValueType(I.getType());
|
2008-06-09 04:54:56 +08:00
|
|
|
if (DestVT.bitsLT(SrcVT))
|
2006-11-27 09:05:10 +08:00
|
|
|
setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
|
|
|
|
else
|
|
|
|
// Note: ZERO_EXTEND can handle cases where the sizes are equal too
|
|
|
|
setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
|
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitBitCast(User &I) {
|
|
|
|
SDOperand N = getValue(I.getOperand(0));
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT DestVT = TLI.getValueType(I.getType());
|
2006-11-27 09:05:10 +08:00
|
|
|
|
|
|
|
// BitCast assures us that source and destination are the same size so this
|
|
|
|
// is either a BIT_CONVERT or a no-op.
|
|
|
|
if (DestVT != N.getValueType())
|
|
|
|
setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
|
|
|
|
else
|
|
|
|
setValue(&I, N); // noop cast.
|
2005-01-07 15:47:53 +08:00
|
|
|
}
|
|
|
|
|
2006-03-29 08:11:43 +08:00
|
|
|
void SelectionDAGLowering::visitInsertElement(User &I) {
|
2006-03-18 09:44:44 +08:00
|
|
|
SDOperand InVec = getValue(I.getOperand(0));
|
|
|
|
SDOperand InVal = getValue(I.getOperand(1));
|
|
|
|
SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
|
|
|
|
getValue(I.getOperand(2)));
|
|
|
|
|
2007-06-26 00:23:39 +08:00
|
|
|
setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT,
|
|
|
|
TLI.getValueType(I.getType()),
|
|
|
|
InVec, InVal, InIdx));
|
2006-03-18 09:44:44 +08:00
|
|
|
}
|
|
|
|
|
2006-03-29 08:11:43 +08:00
|
|
|
void SelectionDAGLowering::visitExtractElement(User &I) {
|
2006-03-22 04:44:12 +08:00
|
|
|
SDOperand InVec = getValue(I.getOperand(0));
|
|
|
|
SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
|
|
|
|
getValue(I.getOperand(1)));
|
2007-06-26 00:23:39 +08:00
|
|
|
setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
|
2006-03-22 04:44:12 +08:00
|
|
|
TLI.getValueType(I.getType()), InVec, InIdx));
|
|
|
|
}
|
2006-03-18 09:44:44 +08:00
|
|
|
|
2006-04-08 12:15:24 +08:00
|
|
|
void SelectionDAGLowering::visitShuffleVector(User &I) {
|
|
|
|
SDOperand V1 = getValue(I.getOperand(0));
|
|
|
|
SDOperand V2 = getValue(I.getOperand(1));
|
|
|
|
SDOperand Mask = getValue(I.getOperand(2));
|
|
|
|
|
2007-06-26 00:23:39 +08:00
|
|
|
setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE,
|
|
|
|
TLI.getValueType(I.getType()),
|
|
|
|
V1, V2, Mask));
|
2006-04-08 12:15:24 +08:00
|
|
|
}
|
|
|
|
|
2008-06-07 10:02:36 +08:00
|
|
|
void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
|
|
|
|
const Value *Op0 = I.getOperand(0);
|
|
|
|
const Value *Op1 = I.getOperand(1);
|
|
|
|
const Type *AggTy = I.getType();
|
|
|
|
const Type *ValTy = Op1->getType();
|
|
|
|
bool IntoUndef = isa<UndefValue>(Op0);
|
|
|
|
bool FromUndef = isa<UndefValue>(Op1);
|
|
|
|
|
|
|
|
unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
|
|
|
|
I.idx_begin(), I.idx_end());
|
|
|
|
|
|
|
|
SmallVector<MVT, 4> AggValueVTs;
|
|
|
|
ComputeValueVTs(TLI, AggTy, AggValueVTs);
|
|
|
|
SmallVector<MVT, 4> ValValueVTs;
|
|
|
|
ComputeValueVTs(TLI, ValTy, ValValueVTs);
|
|
|
|
|
|
|
|
unsigned NumAggValues = AggValueVTs.size();
|
|
|
|
unsigned NumValValues = ValValueVTs.size();
|
|
|
|
SmallVector<SDOperand, 4> Values(NumAggValues);
|
|
|
|
|
|
|
|
SDOperand Agg = getValue(Op0);
|
|
|
|
SDOperand Val = getValue(Op1);
|
|
|
|
unsigned i = 0;
|
|
|
|
// Copy the beginning value(s) from the original aggregate.
|
|
|
|
for (; i != LinearIndex; ++i)
|
|
|
|
Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
|
|
|
|
SDOperand(Agg.Val, Agg.ResNo + i);
|
|
|
|
// Copy values from the inserted value(s).
|
|
|
|
for (; i != LinearIndex + NumValValues; ++i)
|
|
|
|
Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
|
|
|
|
SDOperand(Val.Val, Val.ResNo + i - LinearIndex);
|
|
|
|
// Copy remaining value(s) from the original aggregate.
|
|
|
|
for (; i != NumAggValues; ++i)
|
|
|
|
Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
|
|
|
|
SDOperand(Agg.Val, Agg.ResNo + i);
|
|
|
|
|
|
|
|
setValue(&I, DAG.getNode(ISD::MERGE_VALUES,
|
|
|
|
DAG.getVTList(&AggValueVTs[0], NumAggValues),
|
|
|
|
&Values[0], NumAggValues));
|
2008-05-16 03:50:34 +08:00
|
|
|
}
|
|
|
|
|
2008-06-07 10:02:36 +08:00
|
|
|
void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
|
|
|
|
const Value *Op0 = I.getOperand(0);
|
|
|
|
const Type *AggTy = Op0->getType();
|
|
|
|
const Type *ValTy = I.getType();
|
|
|
|
bool OutOfUndef = isa<UndefValue>(Op0);
|
|
|
|
|
|
|
|
unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
|
|
|
|
I.idx_begin(), I.idx_end());
|
|
|
|
|
|
|
|
SmallVector<MVT, 4> ValValueVTs;
|
|
|
|
ComputeValueVTs(TLI, ValTy, ValValueVTs);
|
|
|
|
|
|
|
|
unsigned NumValValues = ValValueVTs.size();
|
|
|
|
SmallVector<SDOperand, 4> Values(NumValValues);
|
|
|
|
|
|
|
|
SDOperand Agg = getValue(Op0);
|
|
|
|
// Copy out the selected value(s).
|
|
|
|
for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
|
|
|
|
Values[i - LinearIndex] =
|
|
|
|
OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.Val->getValueType(i)) :
|
|
|
|
SDOperand(Agg.Val, Agg.ResNo + i - LinearIndex);
|
|
|
|
|
|
|
|
setValue(&I, DAG.getNode(ISD::MERGE_VALUES,
|
|
|
|
DAG.getVTList(&ValValueVTs[0], NumValValues),
|
|
|
|
&Values[0], NumValValues));
|
2008-05-16 03:50:34 +08:00
|
|
|
}
|
|
|
|
|
2006-04-08 12:15:24 +08:00
|
|
|
|
2005-01-07 15:47:53 +08:00
|
|
|
void SelectionDAGLowering::visitGetElementPtr(User &I) {
|
|
|
|
SDOperand N = getValue(I.getOperand(0));
|
|
|
|
const Type *Ty = I.getOperand(0)->getType();
|
|
|
|
|
|
|
|
for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
|
|
|
|
OI != E; ++OI) {
|
|
|
|
Value *Idx = *OI;
|
Fix the #1 code quality problem that I have seen on X86 (and it also affects
PPC and other targets). In a particular, consider code like this:
struct Vector3 { double x, y, z; };
struct Matrix3 { Vector3 a, b, c; };
double dot(Vector3 &a, Vector3 &b) {
return a.x * b.x + a.y * b.y + a.z * b.z;
}
Vector3 mul(Vector3 &a, Matrix3 &b) {
Vector3 r;
r.x = dot( a, b.a );
r.y = dot( a, b.b );
r.z = dot( a, b.c );
return r;
}
void transform(Matrix3 &m, Vector3 *x, int n) {
for (int i = 0; i < n; i++)
x[i] = mul( x[i], m );
}
we compile transform to a loop with all of the GEP instructions for indexing
into 'm' pulled out of the loop (9 of them). Because isel occurs a bb at a time
we are unable to fold the constant index into the loads in the loop, leading to
PPC code that looks like this:
LBB3_1: ; no_exit.preheader
li r2, 0
addi r6, r3, 64 ;; 9 values live across the loop body!
addi r7, r3, 56
addi r8, r3, 48
addi r9, r3, 40
addi r10, r3, 32
addi r11, r3, 24
addi r12, r3, 16
addi r30, r3, 8
LBB3_2: ; no_exit
lfd f0, 0(r30)
lfd f1, 8(r4)
fmul f0, f1, f0
lfd f2, 0(r3) ;; no constant indices folded into the loads!
lfd f3, 0(r4)
lfd f4, 0(r10)
lfd f5, 0(r6)
lfd f6, 0(r7)
lfd f7, 0(r8)
lfd f8, 0(r9)
lfd f9, 0(r11)
lfd f10, 0(r12)
lfd f11, 16(r4)
fmadd f0, f3, f2, f0
fmul f2, f1, f4
fmadd f0, f11, f10, f0
fmadd f2, f3, f9, f2
fmul f1, f1, f6
stfd f0, 0(r4)
fmadd f0, f11, f8, f2
fmadd f1, f3, f7, f1
stfd f0, 8(r4)
fmadd f0, f11, f5, f1
addi r29, r4, 24
stfd f0, 16(r4)
addi r2, r2, 1
cmpw cr0, r2, r5
or r4, r29, r29
bne cr0, LBB3_2 ; no_exit
uh, yuck. With this patch, we now sink the constant offsets into the loop, producing
this code:
LBB3_1: ; no_exit.preheader
li r2, 0
LBB3_2: ; no_exit
lfd f0, 8(r3)
lfd f1, 8(r4)
fmul f0, f1, f0
lfd f2, 0(r3)
lfd f3, 0(r4)
lfd f4, 32(r3) ;; much nicer.
lfd f5, 64(r3)
lfd f6, 56(r3)
lfd f7, 48(r3)
lfd f8, 40(r3)
lfd f9, 24(r3)
lfd f10, 16(r3)
lfd f11, 16(r4)
fmadd f0, f3, f2, f0
fmul f2, f1, f4
fmadd f0, f11, f10, f0
fmadd f2, f3, f9, f2
fmul f1, f1, f6
stfd f0, 0(r4)
fmadd f0, f11, f8, f2
fmadd f1, f3, f7, f1
stfd f0, 8(r4)
fmadd f0, f11, f5, f1
addi r6, r4, 24
stfd f0, 16(r4)
addi r2, r2, 1
cmpw cr0, r2, r5
or r4, r6, r6
bne cr0, LBB3_2 ; no_exit
This is much nicer as it reduces register pressure in the loop a lot. On X86,
this takes the function from having 9 spilled registers to 2. This should help
some spec programs on X86 (gzip?)
This is currently only enabled with -enable-gep-isel-opt to allow perf testing
tonight.
llvm-svn: 24606
2005-12-05 15:10:48 +08:00
|
|
|
if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
|
2006-10-20 15:07:24 +08:00
|
|
|
unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
|
2005-01-07 15:47:53 +08:00
|
|
|
if (Field) {
|
|
|
|
// N = N + Offset
|
2007-02-11 03:55:17 +08:00
|
|
|
uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
|
2005-01-07 15:47:53 +08:00
|
|
|
N = DAG.getNode(ISD::ADD, N.getValueType(), N,
|
2008-01-17 15:00:52 +08:00
|
|
|
DAG.getIntPtrConstant(Offset));
|
2005-01-07 15:47:53 +08:00
|
|
|
}
|
|
|
|
Ty = StTy->getElementType(Field);
|
|
|
|
} else {
|
|
|
|
Ty = cast<SequentialType>(Ty)->getElementType();
|
2005-11-09 12:45:33 +08:00
|
|
|
|
|
|
|
// If this is a constant subscript, handle it quickly.
|
|
|
|
if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
|
2006-10-20 15:07:24 +08:00
|
|
|
if (CI->getZExtValue() == 0) continue;
|
2006-12-31 13:55:36 +08:00
|
|
|
uint64_t Offs =
|
2007-10-02 07:08:35 +08:00
|
|
|
TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
|
2008-01-17 15:00:52 +08:00
|
|
|
N = DAG.getNode(ISD::ADD, N.getValueType(), N,
|
|
|
|
DAG.getIntPtrConstant(Offs));
|
2005-11-09 12:45:33 +08:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
// N = N + Idx * ElementSize;
|
2007-10-02 07:08:35 +08:00
|
|
|
uint64_t ElementSize = TD->getABITypeSize(Ty);
|
2005-11-09 12:45:33 +08:00
|
|
|
SDOperand IdxN = getValue(Idx);
|
|
|
|
|
|
|
|
// If the index is smaller or larger than intptr_t, truncate or extend
|
|
|
|
// it.
|
2008-06-09 04:54:56 +08:00
|
|
|
if (IdxN.getValueType().bitsLT(N.getValueType())) {
|
2006-12-31 13:55:36 +08:00
|
|
|
IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
|
2008-06-09 04:54:56 +08:00
|
|
|
} else if (IdxN.getValueType().bitsGT(N.getValueType()))
|
2005-11-09 12:45:33 +08:00
|
|
|
IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
|
|
|
|
|
|
|
|
// If this is a multiply by a power of two, turn it into a shl
|
|
|
|
// immediately. This is a very common case.
|
|
|
|
if (isPowerOf2_64(ElementSize)) {
|
|
|
|
unsigned Amt = Log2_64(ElementSize);
|
|
|
|
IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
|
2005-11-10 00:50:40 +08:00
|
|
|
DAG.getConstant(Amt, TLI.getShiftAmountTy()));
|
2005-01-07 15:47:53 +08:00
|
|
|
N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
|
2005-11-09 12:45:33 +08:00
|
|
|
continue;
|
2005-01-07 15:47:53 +08:00
|
|
|
}
|
2005-11-09 12:45:33 +08:00
|
|
|
|
2008-01-17 15:00:52 +08:00
|
|
|
SDOperand Scale = DAG.getIntPtrConstant(ElementSize);
|
2005-11-09 12:45:33 +08:00
|
|
|
IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
|
|
|
|
N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
|
2005-01-07 15:47:53 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
setValue(&I, N);
|
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
|
|
|
|
// If this is a fixed sized alloca in the entry block of the function,
|
|
|
|
// allocate it statically on the stack.
|
|
|
|
if (FuncInfo.StaticAllocaMap.count(&I))
|
|
|
|
return; // getValue will auto-populate this.
|
|
|
|
|
|
|
|
const Type *Ty = I.getAllocatedType();
|
Executive summary: getTypeSize -> getTypeStoreSize / getABITypeSize.
The meaning of getTypeSize was not clear - clarifying it is important
now that we have x86 long double and arbitrary precision integers.
The issue with long double is that it requires 80 bits, and this is
not a multiple of its alignment. This gives a primitive type for
which getTypeSize differed from getABITypeSize. For arbitrary precision
integers it is even worse: there is the minimum number of bits needed to
hold the type (eg: 36 for an i36), the maximum number of bits that will
be overwriten when storing the type (40 bits for i36) and the ABI size
(i.e. the storage size rounded up to a multiple of the alignment; 64 bits
for i36).
This patch removes getTypeSize (not really - it is still there but
deprecated to allow for a gradual transition). Instead there is:
(1) getTypeSizeInBits - a number of bits that suffices to hold all
values of the type. For a primitive type, this is the minimum number
of bits. For an i36 this is 36 bits. For x86 long double it is 80.
This corresponds to gcc's TYPE_PRECISION.
(2) getTypeStoreSizeInBits - the maximum number of bits that is
written when storing the type (or read when reading it). For an
i36 this is 40 bits, for an x86 long double it is 80 bits. This
is the size alias analysis is interested in (getTypeStoreSize
returns the number of bytes). There doesn't seem to be anything
corresponding to this in gcc.
(3) getABITypeSizeInBits - this is getTypeStoreSizeInBits rounded
up to a multiple of the alignment. For an i36 this is 64, for an
x86 long double this is 96 or 128 depending on the OS. This is the
spacing between consecutive elements when you form an array out of
this type (getABITypeSize returns the number of bytes). This is
TYPE_SIZE in gcc.
Since successive elements in a SequentialType (arrays, pointers
and vectors) need to be aligned, the spacing between them will be
given by getABITypeSize. This means that the size of an array
is the length times the getABITypeSize. It also means that GEP
computations need to use getABITypeSize when computing offsets.
Furthermore, if an alloca allocates several elements at once then
these too need to be aligned, so the size of the alloca has to be
the number of elements multiplied by getABITypeSize. Logically
speaking this doesn't have to be the case when allocating just
one element, but it is simpler to also use getABITypeSize in this
case. So alloca's and mallocs should use getABITypeSize. Finally,
since gcc's only notion of size is that given by getABITypeSize, if
you want to output assembler etc the same as gcc then getABITypeSize
is the size you want.
Since a store will overwrite no more than getTypeStoreSize bytes,
and a read will read no more than that many bytes, this is the
notion of size appropriate for alias analysis calculations.
In this patch I have corrected all type size uses except some of
those in ScalarReplAggregates, lib/Codegen, lib/Target (the hard
cases). I will get around to auditing these too at some point,
but I could do with some help.
Finally, I made one change which I think wise but others might
consider pointless and suboptimal: in an unpacked struct the
amount of space allocated for a field is now given by the ABI
size rather than getTypeStoreSize. I did this because every
other place that reserves memory for a type (eg: alloca) now
uses getABITypeSize, and I didn't want to make an exception
for unpacked structs, i.e. I did it to make things more uniform.
This only effects structs containing long doubles and arbitrary
precision integers. If someone wants to pack these types more
tightly they can always use a packed struct.
llvm-svn: 43620
2007-11-02 04:53:16 +08:00
|
|
|
uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
|
2007-01-21 06:35:55 +08:00
|
|
|
unsigned Align =
|
2007-02-14 13:52:17 +08:00
|
|
|
std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
|
2007-01-21 06:35:55 +08:00
|
|
|
I.getAlignment());
|
2005-01-07 15:47:53 +08:00
|
|
|
|
|
|
|
SDOperand AllocSize = getValue(I.getArraySize());
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT IntPtr = TLI.getPointerTy();
|
2008-06-09 04:54:56 +08:00
|
|
|
if (IntPtr.bitsLT(AllocSize.getValueType()))
|
2005-01-23 07:04:37 +08:00
|
|
|
AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
|
2008-06-09 04:54:56 +08:00
|
|
|
else if (IntPtr.bitsGT(AllocSize.getValueType()))
|
2005-01-23 07:04:37 +08:00
|
|
|
AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
|
2005-01-07 15:47:53 +08:00
|
|
|
|
2005-01-23 07:04:37 +08:00
|
|
|
AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
|
2008-01-17 15:00:52 +08:00
|
|
|
DAG.getIntPtrConstant(TySize));
|
2005-01-07 15:47:53 +08:00
|
|
|
|
2007-08-17 07:46:29 +08:00
|
|
|
// Handle alignment. If the requested alignment is less than or equal to
|
|
|
|
// the stack alignment, ignore it. If the size is greater than or equal to
|
|
|
|
// the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
|
2005-01-07 15:47:53 +08:00
|
|
|
unsigned StackAlign =
|
|
|
|
TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
|
2007-08-17 07:46:29 +08:00
|
|
|
if (Align <= StackAlign)
|
2005-01-07 15:47:53 +08:00
|
|
|
Align = 0;
|
2007-08-17 07:46:29 +08:00
|
|
|
|
|
|
|
// Round the size of the allocation up to the stack alignment size
|
|
|
|
// by add SA-1 to the size.
|
|
|
|
AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
|
2008-01-17 15:00:52 +08:00
|
|
|
DAG.getIntPtrConstant(StackAlign-1));
|
2007-08-17 07:46:29 +08:00
|
|
|
// Mask out the low bits for alignment purposes.
|
|
|
|
AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
|
2008-01-17 15:00:52 +08:00
|
|
|
DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
|
2005-01-07 15:47:53 +08:00
|
|
|
|
2008-01-17 15:00:52 +08:00
|
|
|
SDOperand Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
|
2008-06-06 20:08:01 +08:00
|
|
|
const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
|
2006-08-15 07:53:35 +08:00
|
|
|
MVT::Other);
|
|
|
|
SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
|
2007-02-04 09:31:47 +08:00
|
|
|
setValue(&I, DSA);
|
|
|
|
DAG.setRoot(DSA.getValue(1));
|
2005-01-07 15:47:53 +08:00
|
|
|
|
|
|
|
// Inform the Frame Information that we have just allocated a variable-sized
|
|
|
|
// object.
|
|
|
|
CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
|
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitLoad(LoadInst &I) {
|
|
|
|
SDOperand Ptr = getValue(I.getOperand(0));
|
2005-04-22 06:36:52 +08:00
|
|
|
|
2005-01-18 06:19:26 +08:00
|
|
|
SDOperand Root;
|
|
|
|
if (I.isVolatile())
|
|
|
|
Root = getRoot();
|
|
|
|
else {
|
|
|
|
// Do not serialize non-volatile loads against each other.
|
|
|
|
Root = DAG.getRoot();
|
|
|
|
}
|
2006-03-16 06:19:46 +08:00
|
|
|
|
2006-10-10 04:57:25 +08:00
|
|
|
setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0),
|
2007-04-23 07:15:30 +08:00
|
|
|
Root, I.isVolatile(), I.getAlignment()));
|
2006-03-16 06:19:46 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
|
2006-10-10 04:57:25 +08:00
|
|
|
const Value *SV, SDOperand Root,
|
2007-04-23 07:15:30 +08:00
|
|
|
bool isVolatile,
|
|
|
|
unsigned Alignment) {
|
2008-06-07 10:02:36 +08:00
|
|
|
SmallVector<MVT, 4> ValueVTs;
|
|
|
|
SmallVector<uint64_t, 4> Offsets;
|
|
|
|
ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
|
|
|
|
unsigned NumValues = ValueVTs.size();
|
|
|
|
|
|
|
|
SmallVector<SDOperand, 4> Values(NumValues);
|
|
|
|
SmallVector<SDOperand, 4> Chains(NumValues);
|
|
|
|
MVT PtrVT = Ptr.getValueType();
|
|
|
|
for (unsigned i = 0; i != NumValues; ++i) {
|
|
|
|
SDOperand L = DAG.getLoad(ValueVTs[i], Root,
|
|
|
|
DAG.getNode(ISD::ADD, PtrVT, Ptr,
|
|
|
|
DAG.getConstant(Offsets[i], PtrVT)),
|
|
|
|
SV, Offsets[i],
|
|
|
|
isVolatile, Alignment);
|
|
|
|
Values[i] = L;
|
|
|
|
Chains[i] = L.getValue(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
|
|
|
|
&Chains[0], NumValues);
|
2006-03-16 06:19:46 +08:00
|
|
|
if (isVolatile)
|
2008-06-07 10:02:36 +08:00
|
|
|
DAG.setRoot(Chain);
|
2005-01-18 06:19:26 +08:00
|
|
|
else
|
2008-06-07 10:02:36 +08:00
|
|
|
PendingLoads.push_back(Chain);
|
|
|
|
|
|
|
|
return DAG.getNode(ISD::MERGE_VALUES,
|
|
|
|
DAG.getVTList(&ValueVTs[0], NumValues),
|
|
|
|
&Values[0], NumValues);
|
2005-01-07 15:47:53 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitStore(StoreInst &I) {
|
|
|
|
Value *SrcV = I.getOperand(0);
|
|
|
|
SDOperand Src = getValue(SrcV);
|
2008-06-07 10:02:36 +08:00
|
|
|
Value *PtrV = I.getOperand(1);
|
|
|
|
SDOperand Ptr = getValue(PtrV);
|
|
|
|
|
|
|
|
SmallVector<MVT, 4> ValueVTs;
|
|
|
|
SmallVector<uint64_t, 4> Offsets;
|
|
|
|
ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
|
|
|
|
unsigned NumValues = ValueVTs.size();
|
|
|
|
|
|
|
|
SDOperand Root = getRoot();
|
|
|
|
SmallVector<SDOperand, 4> Chains(NumValues);
|
|
|
|
MVT PtrVT = Ptr.getValueType();
|
|
|
|
bool isVolatile = I.isVolatile();
|
|
|
|
unsigned Alignment = I.getAlignment();
|
|
|
|
for (unsigned i = 0; i != NumValues; ++i)
|
|
|
|
Chains[i] = DAG.getStore(Root, SDOperand(Src.Val, Src.ResNo + i),
|
|
|
|
DAG.getNode(ISD::ADD, PtrVT, Ptr,
|
|
|
|
DAG.getConstant(Offsets[i], PtrVT)),
|
|
|
|
PtrV, Offsets[i],
|
|
|
|
isVolatile, Alignment);
|
|
|
|
|
|
|
|
DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumValues));
|
2005-01-07 15:47:53 +08:00
|
|
|
}
|
|
|
|
|
2006-03-24 10:22:33 +08:00
|
|
|
/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
|
|
|
|
/// node.
|
|
|
|
void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
|
|
|
|
unsigned Intrinsic) {
|
2007-12-04 04:06:50 +08:00
|
|
|
bool HasChain = !I.doesNotAccessMemory();
|
|
|
|
bool OnlyLoad = HasChain && I.onlyReadsMemory();
|
|
|
|
|
2006-03-24 10:22:33 +08:00
|
|
|
// Build the operand list.
|
2006-08-08 10:23:42 +08:00
|
|
|
SmallVector<SDOperand, 8> Ops;
|
2006-04-02 11:41:14 +08:00
|
|
|
if (HasChain) { // If this intrinsic has side-effects, chainify it.
|
|
|
|
if (OnlyLoad) {
|
|
|
|
// We don't need to serialize loads against other loads.
|
|
|
|
Ops.push_back(DAG.getRoot());
|
|
|
|
} else {
|
|
|
|
Ops.push_back(getRoot());
|
|
|
|
}
|
|
|
|
}
|
2006-03-24 10:22:33 +08:00
|
|
|
|
|
|
|
// Add the intrinsic ID as an integer operand.
|
|
|
|
Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
|
|
|
|
|
|
|
|
// Add all operands of the call to the operand list.
|
|
|
|
for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
|
|
|
|
SDOperand Op = getValue(I.getOperand(i));
|
|
|
|
assert(TLI.isTypeLegal(Op.getValueType()) &&
|
|
|
|
"Intrinsic uses a non-legal type?");
|
|
|
|
Ops.push_back(Op);
|
|
|
|
}
|
|
|
|
|
2008-06-06 20:08:01 +08:00
|
|
|
std::vector<MVT> VTs;
|
2006-03-24 10:22:33 +08:00
|
|
|
if (I.getType() != Type::VoidTy) {
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT VT = TLI.getValueType(I.getType());
|
|
|
|
if (VT.isVector()) {
|
2007-02-15 10:26:10 +08:00
|
|
|
const VectorType *DestTy = cast<VectorType>(I.getType());
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT EltVT = TLI.getValueType(DestTy->getElementType());
|
2006-03-24 10:22:33 +08:00
|
|
|
|
2008-06-06 20:08:01 +08:00
|
|
|
VT = MVT::getVectorVT(EltVT, DestTy->getNumElements());
|
2006-03-24 10:22:33 +08:00
|
|
|
assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
|
|
|
|
}
|
|
|
|
|
|
|
|
assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
|
|
|
|
VTs.push_back(VT);
|
|
|
|
}
|
|
|
|
if (HasChain)
|
|
|
|
VTs.push_back(MVT::Other);
|
|
|
|
|
2008-06-06 20:08:01 +08:00
|
|
|
const MVT *VTList = DAG.getNodeValueTypes(VTs);
|
2006-08-15 07:53:35 +08:00
|
|
|
|
2006-03-24 10:22:33 +08:00
|
|
|
// Create the node.
|
2006-03-28 08:40:33 +08:00
|
|
|
SDOperand Result;
|
|
|
|
if (!HasChain)
|
2006-08-15 07:53:35 +08:00
|
|
|
Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
|
|
|
|
&Ops[0], Ops.size());
|
2006-03-28 08:40:33 +08:00
|
|
|
else if (I.getType() != Type::VoidTy)
|
2006-08-15 07:53:35 +08:00
|
|
|
Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
|
|
|
|
&Ops[0], Ops.size());
|
2006-03-28 08:40:33 +08:00
|
|
|
else
|
2006-08-15 07:53:35 +08:00
|
|
|
Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
|
|
|
|
&Ops[0], Ops.size());
|
2006-03-28 08:40:33 +08:00
|
|
|
|
2006-04-02 11:41:14 +08:00
|
|
|
if (HasChain) {
|
|
|
|
SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
|
|
|
|
if (OnlyLoad)
|
|
|
|
PendingLoads.push_back(Chain);
|
|
|
|
else
|
|
|
|
DAG.setRoot(Chain);
|
|
|
|
}
|
2006-03-24 10:22:33 +08:00
|
|
|
if (I.getType() != Type::VoidTy) {
|
2007-02-15 10:26:10 +08:00
|
|
|
if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT VT = TLI.getValueType(PTy);
|
2007-06-26 00:23:39 +08:00
|
|
|
Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
|
2006-03-24 10:22:33 +08:00
|
|
|
}
|
|
|
|
setValue(&I, Result);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-07-06 17:10:03 +08:00
|
|
|
/// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
|
2007-07-05 04:52:51 +08:00
|
|
|
static GlobalVariable *ExtractTypeInfo (Value *V) {
|
2008-05-08 06:54:15 +08:00
|
|
|
V = V->stripPointerCasts();
|
2007-07-06 17:10:03 +08:00
|
|
|
GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
|
2008-02-20 19:10:28 +08:00
|
|
|
assert ((GV || isa<ConstantPointerNull>(V)) &&
|
2007-07-05 04:52:51 +08:00
|
|
|
"TypeInfo must be a global variable or NULL");
|
|
|
|
return GV;
|
|
|
|
}
|
|
|
|
|
2007-06-16 03:04:19 +08:00
|
|
|
/// addCatchInfo - Extract the personality and type infos from an eh.selector
|
2007-07-05 04:52:51 +08:00
|
|
|
/// call, and add them to the specified machine basic block.
|
2007-06-16 03:04:19 +08:00
|
|
|
static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI,
|
|
|
|
MachineBasicBlock *MBB) {
|
|
|
|
// Inform the MachineModuleInfo of the personality for this landing pad.
|
|
|
|
ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
|
|
|
|
assert(CE->getOpcode() == Instruction::BitCast &&
|
|
|
|
isa<Function>(CE->getOperand(0)) &&
|
|
|
|
"Personality should be a function");
|
|
|
|
MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
|
|
|
|
|
|
|
|
// Gather all the type infos for this landing pad and pass them along to
|
|
|
|
// MachineModuleInfo.
|
|
|
|
std::vector<GlobalVariable *> TyInfo;
|
2007-07-05 04:52:51 +08:00
|
|
|
unsigned N = I.getNumOperands();
|
|
|
|
|
|
|
|
for (unsigned i = N - 1; i > 2; --i) {
|
|
|
|
if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
|
|
|
|
unsigned FilterLength = CI->getZExtValue();
|
There is an impedance matching problem between LLVM and
gcc exception handling: if an exception unwinds through
an invoke, then execution must branch to the invoke's
unwind target. We previously tried to enforce this by
appending a cleanup action to every selector, however
this does not always work correctly due to an optimization
in the C++ unwinding runtime: if only cleanups would be
run while unwinding an exception, then the program just
terminates without actually executing the cleanups, as
invoke semantics would require. I was hoping this
wouldn't be a problem, but in fact it turns out to be the
cause of all the remaining failures in the LLVM testsuite
(these also fail with -enable-correct-eh-support, so turning
on -enable-eh didn't make things worse!). Instead we need
to append a full-blown catch-all to the end of each
selector. The correct way of doing this depends on the
personality function, i.e. it is language dependent, so
can only be done by gcc. Thus this patch which generalizes
the eh.selector intrinsic so that it can handle all possible
kinds of action table entries (before it didn't accomodate
cleanups): now 0 indicates a cleanup, and filters have to be
specified using the number of type infos plus one rather than
the number of type infos. Related gcc patches will cause
Ada to pass a cleanup (0) to force the selector to always
fire, while C++ will use a C++ catch-all (null).
llvm-svn: 41484
2007-08-27 23:47:50 +08:00
|
|
|
unsigned FirstCatch = i + FilterLength + !FilterLength;
|
2007-07-05 04:52:51 +08:00
|
|
|
assert (FirstCatch <= N && "Invalid filter length");
|
|
|
|
|
|
|
|
if (FirstCatch < N) {
|
|
|
|
TyInfo.reserve(N - FirstCatch);
|
|
|
|
for (unsigned j = FirstCatch; j < N; ++j)
|
|
|
|
TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
|
|
|
|
MMI->addCatchTypeInfo(MBB, TyInfo);
|
|
|
|
TyInfo.clear();
|
|
|
|
}
|
|
|
|
|
There is an impedance matching problem between LLVM and
gcc exception handling: if an exception unwinds through
an invoke, then execution must branch to the invoke's
unwind target. We previously tried to enforce this by
appending a cleanup action to every selector, however
this does not always work correctly due to an optimization
in the C++ unwinding runtime: if only cleanups would be
run while unwinding an exception, then the program just
terminates without actually executing the cleanups, as
invoke semantics would require. I was hoping this
wouldn't be a problem, but in fact it turns out to be the
cause of all the remaining failures in the LLVM testsuite
(these also fail with -enable-correct-eh-support, so turning
on -enable-eh didn't make things worse!). Instead we need
to append a full-blown catch-all to the end of each
selector. The correct way of doing this depends on the
personality function, i.e. it is language dependent, so
can only be done by gcc. Thus this patch which generalizes
the eh.selector intrinsic so that it can handle all possible
kinds of action table entries (before it didn't accomodate
cleanups): now 0 indicates a cleanup, and filters have to be
specified using the number of type infos plus one rather than
the number of type infos. Related gcc patches will cause
Ada to pass a cleanup (0) to force the selector to always
fire, while C++ will use a C++ catch-all (null).
llvm-svn: 41484
2007-08-27 23:47:50 +08:00
|
|
|
if (!FilterLength) {
|
|
|
|
// Cleanup.
|
|
|
|
MMI->addCleanup(MBB);
|
|
|
|
} else {
|
|
|
|
// Filter.
|
|
|
|
TyInfo.reserve(FilterLength - 1);
|
|
|
|
for (unsigned j = i + 1; j < FirstCatch; ++j)
|
|
|
|
TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
|
|
|
|
MMI->addFilterTypeInfo(MBB, TyInfo);
|
|
|
|
TyInfo.clear();
|
|
|
|
}
|
2007-07-05 04:52:51 +08:00
|
|
|
|
|
|
|
N = i;
|
|
|
|
}
|
2007-06-16 03:04:19 +08:00
|
|
|
}
|
2007-07-05 04:52:51 +08:00
|
|
|
|
|
|
|
if (N > 3) {
|
|
|
|
TyInfo.reserve(N - 3);
|
|
|
|
for (unsigned j = 3; j < N; ++j)
|
|
|
|
TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
|
2007-06-16 03:04:19 +08:00
|
|
|
MMI->addCatchTypeInfo(MBB, TyInfo);
|
2007-07-05 04:52:51 +08:00
|
|
|
}
|
2007-06-16 03:04:19 +08:00
|
|
|
}
|
|
|
|
|
2008-05-06 03:05:59 +08:00
|
|
|
|
|
|
|
/// Inlined utility function to implement binary input atomic intrinsics for
|
|
|
|
// visitIntrinsicCall: I is a call instruction
|
|
|
|
// Op is the associated NodeType for I
|
|
|
|
const char *
|
|
|
|
SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
|
|
|
|
SDOperand Root = getRoot();
|
|
|
|
SDOperand O2 = getValue(I.getOperand(2));
|
|
|
|
SDOperand L = DAG.getAtomic(Op, Root,
|
|
|
|
getValue(I.getOperand(1)),
|
|
|
|
O2, O2.getValueType());
|
|
|
|
setValue(&I, L);
|
|
|
|
DAG.setRoot(L.getValue(1));
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2005-11-10 03:44:01 +08:00
|
|
|
/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
|
|
|
|
/// we want to emit this as a call to a named external function, return the name
|
|
|
|
/// otherwise lower it and return null.
|
|
|
|
const char *
|
|
|
|
SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
|
|
|
|
switch (Intrinsic) {
|
2006-03-24 10:22:33 +08:00
|
|
|
default:
|
|
|
|
// By default, turn this into a target intrinsic node.
|
|
|
|
visitTargetIntrinsic(I, Intrinsic);
|
|
|
|
return 0;
|
2005-11-10 03:44:01 +08:00
|
|
|
case Intrinsic::vastart: visitVAStart(I); return 0;
|
|
|
|
case Intrinsic::vaend: visitVAEnd(I); return 0;
|
|
|
|
case Intrinsic::vacopy: visitVACopy(I); return 0;
|
2007-01-30 06:58:52 +08:00
|
|
|
case Intrinsic::returnaddress:
|
|
|
|
setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
|
|
|
|
getValue(I.getOperand(1))));
|
|
|
|
return 0;
|
|
|
|
case Intrinsic::frameaddress:
|
|
|
|
setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
|
|
|
|
getValue(I.getOperand(1))));
|
|
|
|
return 0;
|
2005-11-10 03:44:01 +08:00
|
|
|
case Intrinsic::setjmp:
|
2006-12-11 07:12:42 +08:00
|
|
|
return "_setjmp"+!TLI.usesUnderscoreSetJmp();
|
2005-11-10 03:44:01 +08:00
|
|
|
break;
|
|
|
|
case Intrinsic::longjmp:
|
2006-12-11 07:12:42 +08:00
|
|
|
return "_longjmp"+!TLI.usesUnderscoreLongJmp();
|
2005-11-10 03:44:01 +08:00
|
|
|
break;
|
2006-03-03 08:00:25 +08:00
|
|
|
case Intrinsic::memcpy_i32:
|
Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal
on any current target and aren't optimized in DAGCombiner. Instead
of using intermediate nodes, expand the operations, choosing between
simple loads/stores, target-specific code, and library calls,
immediately.
Previously, the code to emit optimized code for these operations
was only used at initial SelectionDAG construction time; now it is
used at all times. This fixes some cases where rep;movs was being
used for small copies where simple loads/stores would be better.
This also cleans up code that checks for alignments less than 4;
let the targets make that decision instead of doing it in
target-independent code. This allows x86 to use rep;movs in
low-alignment cases.
Also, this fixes a bug that resulted in the use of rep;stos for
memsets of 0 with non-constant memory size when the alignment was
at least 4. It's better to use the library in this case, which
can be significantly faster when the size is large.
This also preserves more SourceValue information when memory
intrinsics are lowered into simple loads/stores.
llvm-svn: 49572
2008-04-12 12:36:06 +08:00
|
|
|
case Intrinsic::memcpy_i64: {
|
|
|
|
SDOperand Op1 = getValue(I.getOperand(1));
|
|
|
|
SDOperand Op2 = getValue(I.getOperand(2));
|
|
|
|
SDOperand Op3 = getValue(I.getOperand(3));
|
|
|
|
unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
|
|
|
|
DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
|
|
|
|
I.getOperand(1), 0, I.getOperand(2), 0));
|
2006-03-03 08:00:25 +08:00
|
|
|
return 0;
|
Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal
on any current target and aren't optimized in DAGCombiner. Instead
of using intermediate nodes, expand the operations, choosing between
simple loads/stores, target-specific code, and library calls,
immediately.
Previously, the code to emit optimized code for these operations
was only used at initial SelectionDAG construction time; now it is
used at all times. This fixes some cases where rep;movs was being
used for small copies where simple loads/stores would be better.
This also cleans up code that checks for alignments less than 4;
let the targets make that decision instead of doing it in
target-independent code. This allows x86 to use rep;movs in
low-alignment cases.
Also, this fixes a bug that resulted in the use of rep;stos for
memsets of 0 with non-constant memory size when the alignment was
at least 4. It's better to use the library in this case, which
can be significantly faster when the size is large.
This also preserves more SourceValue information when memory
intrinsics are lowered into simple loads/stores.
llvm-svn: 49572
2008-04-12 12:36:06 +08:00
|
|
|
}
|
2006-03-03 08:00:25 +08:00
|
|
|
case Intrinsic::memset_i32:
|
Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal
on any current target and aren't optimized in DAGCombiner. Instead
of using intermediate nodes, expand the operations, choosing between
simple loads/stores, target-specific code, and library calls,
immediately.
Previously, the code to emit optimized code for these operations
was only used at initial SelectionDAG construction time; now it is
used at all times. This fixes some cases where rep;movs was being
used for small copies where simple loads/stores would be better.
This also cleans up code that checks for alignments less than 4;
let the targets make that decision instead of doing it in
target-independent code. This allows x86 to use rep;movs in
low-alignment cases.
Also, this fixes a bug that resulted in the use of rep;stos for
memsets of 0 with non-constant memory size when the alignment was
at least 4. It's better to use the library in this case, which
can be significantly faster when the size is large.
This also preserves more SourceValue information when memory
intrinsics are lowered into simple loads/stores.
llvm-svn: 49572
2008-04-12 12:36:06 +08:00
|
|
|
case Intrinsic::memset_i64: {
|
|
|
|
SDOperand Op1 = getValue(I.getOperand(1));
|
|
|
|
SDOperand Op2 = getValue(I.getOperand(2));
|
|
|
|
SDOperand Op3 = getValue(I.getOperand(3));
|
|
|
|
unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
|
|
|
|
DAG.setRoot(DAG.getMemset(getRoot(), Op1, Op2, Op3, Align,
|
|
|
|
I.getOperand(1), 0));
|
2006-03-03 08:00:25 +08:00
|
|
|
return 0;
|
Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal
on any current target and aren't optimized in DAGCombiner. Instead
of using intermediate nodes, expand the operations, choosing between
simple loads/stores, target-specific code, and library calls,
immediately.
Previously, the code to emit optimized code for these operations
was only used at initial SelectionDAG construction time; now it is
used at all times. This fixes some cases where rep;movs was being
used for small copies where simple loads/stores would be better.
This also cleans up code that checks for alignments less than 4;
let the targets make that decision instead of doing it in
target-independent code. This allows x86 to use rep;movs in
low-alignment cases.
Also, this fixes a bug that resulted in the use of rep;stos for
memsets of 0 with non-constant memory size when the alignment was
at least 4. It's better to use the library in this case, which
can be significantly faster when the size is large.
This also preserves more SourceValue information when memory
intrinsics are lowered into simple loads/stores.
llvm-svn: 49572
2008-04-12 12:36:06 +08:00
|
|
|
}
|
2006-03-03 08:00:25 +08:00
|
|
|
case Intrinsic::memmove_i32:
|
Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal
on any current target and aren't optimized in DAGCombiner. Instead
of using intermediate nodes, expand the operations, choosing between
simple loads/stores, target-specific code, and library calls,
immediately.
Previously, the code to emit optimized code for these operations
was only used at initial SelectionDAG construction time; now it is
used at all times. This fixes some cases where rep;movs was being
used for small copies where simple loads/stores would be better.
This also cleans up code that checks for alignments less than 4;
let the targets make that decision instead of doing it in
target-independent code. This allows x86 to use rep;movs in
low-alignment cases.
Also, this fixes a bug that resulted in the use of rep;stos for
memsets of 0 with non-constant memory size when the alignment was
at least 4. It's better to use the library in this case, which
can be significantly faster when the size is large.
This also preserves more SourceValue information when memory
intrinsics are lowered into simple loads/stores.
llvm-svn: 49572
2008-04-12 12:36:06 +08:00
|
|
|
case Intrinsic::memmove_i64: {
|
|
|
|
SDOperand Op1 = getValue(I.getOperand(1));
|
|
|
|
SDOperand Op2 = getValue(I.getOperand(2));
|
|
|
|
SDOperand Op3 = getValue(I.getOperand(3));
|
|
|
|
unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
|
|
|
|
|
|
|
|
// If the source and destination are known to not be aliases, we can
|
|
|
|
// lower memmove as memcpy.
|
|
|
|
uint64_t Size = -1ULL;
|
|
|
|
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
|
|
|
|
Size = C->getValue();
|
|
|
|
if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
|
|
|
|
AliasAnalysis::NoAlias) {
|
|
|
|
DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
|
|
|
|
I.getOperand(1), 0, I.getOperand(2), 0));
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
DAG.setRoot(DAG.getMemmove(getRoot(), Op1, Op2, Op3, Align,
|
|
|
|
I.getOperand(1), 0, I.getOperand(2), 0));
|
2006-03-03 08:00:25 +08:00
|
|
|
return 0;
|
Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal
on any current target and aren't optimized in DAGCombiner. Instead
of using intermediate nodes, expand the operations, choosing between
simple loads/stores, target-specific code, and library calls,
immediately.
Previously, the code to emit optimized code for these operations
was only used at initial SelectionDAG construction time; now it is
used at all times. This fixes some cases where rep;movs was being
used for small copies where simple loads/stores would be better.
This also cleans up code that checks for alignments less than 4;
let the targets make that decision instead of doing it in
target-independent code. This allows x86 to use rep;movs in
low-alignment cases.
Also, this fixes a bug that resulted in the use of rep;stos for
memsets of 0 with non-constant memory size when the alignment was
at least 4. It's better to use the library in this case, which
can be significantly faster when the size is large.
This also preserves more SourceValue information when memory
intrinsics are lowered into simple loads/stores.
llvm-svn: 49572
2008-04-12 12:36:06 +08:00
|
|
|
}
|
2005-12-14 01:40:33 +08:00
|
|
|
case Intrinsic::dbg_stoppoint: {
|
2007-01-27 05:22:28 +08:00
|
|
|
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
|
2006-03-24 02:06:46 +08:00
|
|
|
DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
|
2007-01-27 05:22:28 +08:00
|
|
|
if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
|
2006-08-08 10:23:42 +08:00
|
|
|
SDOperand Ops[5];
|
2005-11-29 14:21:05 +08:00
|
|
|
|
2006-08-08 10:23:42 +08:00
|
|
|
Ops[0] = getRoot();
|
|
|
|
Ops[1] = getValue(SPI.getLineValue());
|
|
|
|
Ops[2] = getValue(SPI.getColumnValue());
|
2006-02-11 09:01:30 +08:00
|
|
|
|
2007-01-27 05:22:28 +08:00
|
|
|
DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
|
2006-02-11 09:01:30 +08:00
|
|
|
assert(DD && "Not a debug information descriptor");
|
2006-03-24 02:06:46 +08:00
|
|
|
CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
|
|
|
|
|
2006-08-08 10:23:42 +08:00
|
|
|
Ops[3] = DAG.getString(CompileUnit->getFileName());
|
|
|
|
Ops[4] = DAG.getString(CompileUnit->getDirectory());
|
2006-02-11 09:01:30 +08:00
|
|
|
|
2006-08-08 10:23:42 +08:00
|
|
|
DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5));
|
2005-12-14 01:40:33 +08:00
|
|
|
}
|
2006-03-24 02:06:46 +08:00
|
|
|
|
2005-11-16 15:22:30 +08:00
|
|
|
return 0;
|
2005-11-29 14:21:05 +08:00
|
|
|
}
|
2006-03-24 02:06:46 +08:00
|
|
|
case Intrinsic::dbg_region_start: {
|
2007-01-27 05:22:28 +08:00
|
|
|
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
|
2006-03-24 02:06:46 +08:00
|
|
|
DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
|
2007-01-27 05:22:28 +08:00
|
|
|
if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
|
|
|
|
unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
|
2007-01-26 22:34:52 +08:00
|
|
|
DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
|
2008-01-31 17:59:15 +08:00
|
|
|
DAG.getConstant(LabelID, MVT::i32),
|
|
|
|
DAG.getConstant(0, MVT::i32)));
|
2006-03-24 02:06:46 +08:00
|
|
|
}
|
|
|
|
|
2005-11-16 15:22:30 +08:00
|
|
|
return 0;
|
2006-03-24 02:06:46 +08:00
|
|
|
}
|
|
|
|
case Intrinsic::dbg_region_end: {
|
2007-01-27 05:22:28 +08:00
|
|
|
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
|
2006-03-24 02:06:46 +08:00
|
|
|
DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
|
2007-01-27 05:22:28 +08:00
|
|
|
if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
|
|
|
|
unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
|
2008-01-31 17:59:15 +08:00
|
|
|
DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
|
|
|
|
DAG.getConstant(LabelID, MVT::i32),
|
|
|
|
DAG.getConstant(0, MVT::i32)));
|
2006-03-24 02:06:46 +08:00
|
|
|
}
|
|
|
|
|
2005-11-16 15:22:30 +08:00
|
|
|
return 0;
|
2006-03-24 02:06:46 +08:00
|
|
|
}
|
|
|
|
case Intrinsic::dbg_func_start: {
|
2007-01-27 05:22:28 +08:00
|
|
|
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
|
2008-02-01 17:10:45 +08:00
|
|
|
if (!MMI) return 0;
|
2006-03-24 02:06:46 +08:00
|
|
|
DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
|
2008-02-01 17:10:45 +08:00
|
|
|
Value *SP = FSI.getSubprogram();
|
|
|
|
if (SP && MMI->Verify(SP)) {
|
|
|
|
// llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
|
|
|
|
// what (most?) gdb expects.
|
|
|
|
DebugInfoDesc *DD = MMI->getDescFor(SP);
|
|
|
|
assert(DD && "Not a debug information descriptor");
|
|
|
|
SubprogramDesc *Subprogram = cast<SubprogramDesc>(DD);
|
|
|
|
const CompileUnitDesc *CompileUnit = Subprogram->getFile();
|
|
|
|
unsigned SrcFile = MMI->RecordSource(CompileUnit->getDirectory(),
|
|
|
|
CompileUnit->getFileName());
|
|
|
|
// Record the source line but does create a label. It will be emitted
|
|
|
|
// at asm emission time.
|
|
|
|
MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile);
|
2006-03-24 02:06:46 +08:00
|
|
|
}
|
|
|
|
|
2005-11-16 15:22:30 +08:00
|
|
|
return 0;
|
2006-03-24 02:06:46 +08:00
|
|
|
}
|
|
|
|
case Intrinsic::dbg_declare: {
|
2007-01-27 05:22:28 +08:00
|
|
|
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
|
2006-03-24 02:06:46 +08:00
|
|
|
DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
|
2008-02-02 12:07:54 +08:00
|
|
|
Value *Variable = DI.getVariable();
|
|
|
|
if (MMI && Variable && MMI->Verify(Variable))
|
|
|
|
DAG.setRoot(DAG.getNode(ISD::DECLARE, MVT::Other, getRoot(),
|
|
|
|
getValue(DI.getAddress()), getValue(Variable)));
|
2006-03-24 02:06:46 +08:00
|
|
|
return 0;
|
|
|
|
}
|
2005-11-10 03:44:01 +08:00
|
|
|
|
2007-02-22 06:53:45 +08:00
|
|
|
case Intrinsic::eh_exception: {
|
2008-04-02 08:25:04 +08:00
|
|
|
if (!CurMBB->isLandingPad()) {
|
|
|
|
// FIXME: Mark exception register as live in. Hack for PR1508.
|
|
|
|
unsigned Reg = TLI.getExceptionAddressRegister();
|
|
|
|
if (Reg) CurMBB->addLiveIn(Reg);
|
2007-02-22 23:38:06 +08:00
|
|
|
}
|
2008-04-02 08:25:04 +08:00
|
|
|
// Insert the EXCEPTIONADDR instruction.
|
|
|
|
SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
|
|
|
|
SDOperand Ops[1];
|
|
|
|
Ops[0] = DAG.getRoot();
|
|
|
|
SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
|
|
|
|
setValue(&I, Op);
|
|
|
|
DAG.setRoot(Op.getValue(1));
|
2007-02-22 06:53:45 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2007-09-07 19:39:35 +08:00
|
|
|
case Intrinsic::eh_selector_i32:
|
|
|
|
case Intrinsic::eh_selector_i64: {
|
2007-02-22 06:53:45 +08:00
|
|
|
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
|
2007-09-07 19:39:35 +08:00
|
|
|
MVT::i32 : MVT::i64);
|
|
|
|
|
2008-04-02 08:25:04 +08:00
|
|
|
if (MMI) {
|
2007-06-16 03:04:19 +08:00
|
|
|
if (CurMBB->isLandingPad())
|
|
|
|
addCatchInfo(I, MMI, CurMBB);
|
2007-06-28 02:45:32 +08:00
|
|
|
else {
|
2007-06-16 03:04:19 +08:00
|
|
|
#ifndef NDEBUG
|
|
|
|
FuncInfo.CatchInfoLost.insert(&I);
|
|
|
|
#endif
|
2007-07-06 17:18:59 +08:00
|
|
|
// FIXME: Mark exception selector register as live in. Hack for PR1508.
|
|
|
|
unsigned Reg = TLI.getExceptionSelectorRegister();
|
|
|
|
if (Reg) CurMBB->addLiveIn(Reg);
|
2007-06-28 02:45:32 +08:00
|
|
|
}
|
2007-02-22 23:38:06 +08:00
|
|
|
|
|
|
|
// Insert the EHSELECTION instruction.
|
2007-09-07 19:39:35 +08:00
|
|
|
SDVTList VTs = DAG.getVTList(VT, MVT::Other);
|
2007-02-22 23:38:06 +08:00
|
|
|
SDOperand Ops[2];
|
|
|
|
Ops[0] = getValue(I.getOperand(1));
|
|
|
|
Ops[1] = getRoot();
|
|
|
|
SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
|
|
|
|
setValue(&I, Op);
|
|
|
|
DAG.setRoot(Op.getValue(1));
|
2007-02-24 17:45:44 +08:00
|
|
|
} else {
|
2007-09-07 19:39:35 +08:00
|
|
|
setValue(&I, DAG.getConstant(0, VT));
|
2007-02-22 06:53:45 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2007-09-07 19:39:35 +08:00
|
|
|
|
|
|
|
case Intrinsic::eh_typeid_for_i32:
|
|
|
|
case Intrinsic::eh_typeid_for_i64: {
|
2007-02-22 06:53:45 +08:00
|
|
|
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
|
2007-09-07 19:39:35 +08:00
|
|
|
MVT::i32 : MVT::i64);
|
2007-02-22 23:38:06 +08:00
|
|
|
|
|
|
|
if (MMI) {
|
|
|
|
// Find the type id for the given typeinfo.
|
2007-07-05 04:52:51 +08:00
|
|
|
GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
|
2007-05-05 01:12:26 +08:00
|
|
|
|
2007-02-22 23:38:06 +08:00
|
|
|
unsigned TypeID = MMI->getTypeIDFor(GV);
|
2007-09-07 19:39:35 +08:00
|
|
|
setValue(&I, DAG.getConstant(TypeID, VT));
|
2007-02-24 17:45:44 +08:00
|
|
|
} else {
|
2007-07-06 22:46:23 +08:00
|
|
|
// Return something different to eh_selector.
|
2007-09-07 19:39:35 +08:00
|
|
|
setValue(&I, DAG.getConstant(1, VT));
|
2007-02-22 06:53:45 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2007-07-14 22:06:15 +08:00
|
|
|
case Intrinsic::eh_return: {
|
|
|
|
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
|
|
|
|
|
2008-04-02 08:25:04 +08:00
|
|
|
if (MMI) {
|
2007-07-14 22:06:15 +08:00
|
|
|
MMI->setCallsEHReturn(true);
|
|
|
|
DAG.setRoot(DAG.getNode(ISD::EH_RETURN,
|
|
|
|
MVT::Other,
|
2008-03-28 03:56:19 +08:00
|
|
|
getControlRoot(),
|
2007-07-14 22:06:15 +08:00
|
|
|
getValue(I.getOperand(1)),
|
|
|
|
getValue(I.getOperand(2))));
|
|
|
|
} else {
|
|
|
|
setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
case Intrinsic::eh_unwind_init: {
|
|
|
|
if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
|
|
|
|
MMI->setCallsUnwindInit(true);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
case Intrinsic::eh_dwarf_cfa: {
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT VT = getValue(I.getOperand(1)).getValueType();
|
2008-04-02 08:25:04 +08:00
|
|
|
SDOperand CfaArg;
|
2008-06-09 04:54:56 +08:00
|
|
|
if (VT.bitsGT(TLI.getPointerTy()))
|
2008-04-02 08:25:04 +08:00
|
|
|
CfaArg = DAG.getNode(ISD::TRUNCATE,
|
|
|
|
TLI.getPointerTy(), getValue(I.getOperand(1)));
|
|
|
|
else
|
|
|
|
CfaArg = DAG.getNode(ISD::SIGN_EXTEND,
|
|
|
|
TLI.getPointerTy(), getValue(I.getOperand(1)));
|
|
|
|
|
|
|
|
SDOperand Offset = DAG.getNode(ISD::ADD,
|
|
|
|
TLI.getPointerTy(),
|
|
|
|
DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
|
|
|
|
TLI.getPointerTy()),
|
|
|
|
CfaArg);
|
|
|
|
setValue(&I, DAG.getNode(ISD::ADD,
|
|
|
|
TLI.getPointerTy(),
|
|
|
|
DAG.getNode(ISD::FRAMEADDR,
|
|
|
|
TLI.getPointerTy(),
|
|
|
|
DAG.getConstant(0,
|
|
|
|
TLI.getPointerTy())),
|
|
|
|
Offset));
|
2007-07-14 22:06:15 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2007-10-03 01:43:59 +08:00
|
|
|
case Intrinsic::sqrt:
|
2005-11-10 03:44:01 +08:00
|
|
|
setValue(&I, DAG.getNode(ISD::FSQRT,
|
|
|
|
getValue(I.getOperand(1)).getValueType(),
|
|
|
|
getValue(I.getOperand(1))));
|
|
|
|
return 0;
|
2007-10-03 01:43:59 +08:00
|
|
|
case Intrinsic::powi:
|
2006-09-09 14:03:30 +08:00
|
|
|
setValue(&I, DAG.getNode(ISD::FPOWI,
|
|
|
|
getValue(I.getOperand(1)).getValueType(),
|
|
|
|
getValue(I.getOperand(1)),
|
|
|
|
getValue(I.getOperand(2))));
|
|
|
|
return 0;
|
2007-10-12 08:01:22 +08:00
|
|
|
case Intrinsic::sin:
|
|
|
|
setValue(&I, DAG.getNode(ISD::FSIN,
|
|
|
|
getValue(I.getOperand(1)).getValueType(),
|
|
|
|
getValue(I.getOperand(1))));
|
|
|
|
return 0;
|
|
|
|
case Intrinsic::cos:
|
|
|
|
setValue(&I, DAG.getNode(ISD::FCOS,
|
|
|
|
getValue(I.getOperand(1)).getValueType(),
|
|
|
|
getValue(I.getOperand(1))));
|
|
|
|
return 0;
|
|
|
|
case Intrinsic::pow:
|
|
|
|
setValue(&I, DAG.getNode(ISD::FPOW,
|
|
|
|
getValue(I.getOperand(1)).getValueType(),
|
|
|
|
getValue(I.getOperand(1)),
|
|
|
|
getValue(I.getOperand(2))));
|
|
|
|
return 0;
|
2005-11-10 03:44:01 +08:00
|
|
|
case Intrinsic::pcmarker: {
|
|
|
|
SDOperand Tmp = getValue(I.getOperand(1));
|
|
|
|
DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
|
|
|
|
return 0;
|
|
|
|
}
|
2005-11-12 06:48:54 +08:00
|
|
|
case Intrinsic::readcyclecounter: {
|
2006-08-08 10:23:42 +08:00
|
|
|
SDOperand Op = getRoot();
|
2006-08-15 07:53:35 +08:00
|
|
|
SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
|
|
|
|
DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
|
|
|
|
&Op, 1);
|
2005-11-12 06:48:54 +08:00
|
|
|
setValue(&I, Tmp);
|
|
|
|
DAG.setRoot(Tmp.getValue(1));
|
2005-11-12 00:47:30 +08:00
|
|
|
return 0;
|
2005-11-12 06:48:54 +08:00
|
|
|
}
|
2007-04-10 11:20:39 +08:00
|
|
|
case Intrinsic::part_select: {
|
2007-04-05 09:20:18 +08:00
|
|
|
// Currently not implemented: just abort
|
2007-04-12 10:48:46 +08:00
|
|
|
assert(0 && "part_select intrinsic not implemented");
|
|
|
|
abort();
|
|
|
|
}
|
|
|
|
case Intrinsic::part_set: {
|
|
|
|
// Currently not implemented: just abort
|
|
|
|
assert(0 && "part_set intrinsic not implemented");
|
2007-04-05 09:20:18 +08:00
|
|
|
abort();
|
2007-04-05 07:48:25 +08:00
|
|
|
}
|
2007-04-01 15:34:11 +08:00
|
|
|
case Intrinsic::bswap:
|
2006-01-14 11:14:10 +08:00
|
|
|
setValue(&I, DAG.getNode(ISD::BSWAP,
|
|
|
|
getValue(I.getOperand(1)).getValueType(),
|
|
|
|
getValue(I.getOperand(1))));
|
|
|
|
return 0;
|
2007-04-01 15:34:11 +08:00
|
|
|
case Intrinsic::cttz: {
|
|
|
|
SDOperand Arg = getValue(I.getOperand(1));
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT Ty = Arg.getValueType();
|
2007-04-01 15:34:11 +08:00
|
|
|
SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg);
|
|
|
|
setValue(&I, result);
|
2005-11-10 03:44:01 +08:00
|
|
|
return 0;
|
2007-04-01 15:34:11 +08:00
|
|
|
}
|
|
|
|
case Intrinsic::ctlz: {
|
|
|
|
SDOperand Arg = getValue(I.getOperand(1));
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT Ty = Arg.getValueType();
|
2007-04-01 15:34:11 +08:00
|
|
|
SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg);
|
|
|
|
setValue(&I, result);
|
2005-11-10 03:44:01 +08:00
|
|
|
return 0;
|
2007-04-01 15:34:11 +08:00
|
|
|
}
|
|
|
|
case Intrinsic::ctpop: {
|
|
|
|
SDOperand Arg = getValue(I.getOperand(1));
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT Ty = Arg.getValueType();
|
2007-04-01 15:34:11 +08:00
|
|
|
SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg);
|
|
|
|
setValue(&I, result);
|
2005-11-10 03:44:01 +08:00
|
|
|
return 0;
|
2007-04-01 15:34:11 +08:00
|
|
|
}
|
2006-01-13 10:50:02 +08:00
|
|
|
case Intrinsic::stacksave: {
|
2006-08-08 10:23:42 +08:00
|
|
|
SDOperand Op = getRoot();
|
2006-08-15 07:53:35 +08:00
|
|
|
SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
|
|
|
|
DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
|
2006-01-13 10:50:02 +08:00
|
|
|
setValue(&I, Tmp);
|
|
|
|
DAG.setRoot(Tmp.getValue(1));
|
|
|
|
return 0;
|
|
|
|
}
|
2006-01-23 13:22:07 +08:00
|
|
|
case Intrinsic::stackrestore: {
|
|
|
|
SDOperand Tmp = getValue(I.getOperand(1));
|
|
|
|
DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
|
2006-01-13 10:50:02 +08:00
|
|
|
return 0;
|
2006-01-23 13:22:07 +08:00
|
|
|
}
|
2007-06-16 06:26:58 +08:00
|
|
|
case Intrinsic::var_annotation:
|
|
|
|
// Discard annotate attributes
|
|
|
|
return 0;
|
2007-07-27 20:58:54 +08:00
|
|
|
|
|
|
|
case Intrinsic::init_trampoline: {
|
2008-05-08 06:54:15 +08:00
|
|
|
const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
|
2007-07-27 20:58:54 +08:00
|
|
|
|
|
|
|
SDOperand Ops[6];
|
|
|
|
Ops[0] = getRoot();
|
|
|
|
Ops[1] = getValue(I.getOperand(1));
|
|
|
|
Ops[2] = getValue(I.getOperand(2));
|
|
|
|
Ops[3] = getValue(I.getOperand(3));
|
|
|
|
Ops[4] = DAG.getSrcValue(I.getOperand(1));
|
|
|
|
Ops[5] = DAG.getSrcValue(F);
|
|
|
|
|
2007-09-11 22:10:23 +08:00
|
|
|
SDOperand Tmp = DAG.getNode(ISD::TRAMPOLINE,
|
|
|
|
DAG.getNodeValueTypes(TLI.getPointerTy(),
|
|
|
|
MVT::Other), 2,
|
|
|
|
Ops, 6);
|
|
|
|
|
|
|
|
setValue(&I, Tmp);
|
|
|
|
DAG.setRoot(Tmp.getValue(1));
|
2007-07-27 20:58:54 +08:00
|
|
|
return 0;
|
|
|
|
}
|
2008-01-07 09:30:38 +08:00
|
|
|
|
|
|
|
case Intrinsic::gcroot:
|
|
|
|
if (GCI) {
|
|
|
|
Value *Alloca = I.getOperand(1);
|
|
|
|
Constant *TypeMap = cast<Constant>(I.getOperand(2));
|
|
|
|
|
|
|
|
FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).Val);
|
|
|
|
GCI->addStackRoot(FI->getIndex(), TypeMap);
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
case Intrinsic::gcread:
|
|
|
|
case Intrinsic::gcwrite:
|
|
|
|
assert(0 && "Collector failed to lower gcread/gcwrite intrinsics!");
|
|
|
|
return 0;
|
|
|
|
|
2007-11-16 07:25:33 +08:00
|
|
|
case Intrinsic::flt_rounds: {
|
2008-01-31 08:41:03 +08:00
|
|
|
setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32));
|
2007-11-16 07:25:33 +08:00
|
|
|
return 0;
|
|
|
|
}
|
2008-01-15 15:02:33 +08:00
|
|
|
|
|
|
|
case Intrinsic::trap: {
|
|
|
|
DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot()));
|
|
|
|
return 0;
|
|
|
|
}
|
2008-03-08 08:58:38 +08:00
|
|
|
case Intrinsic::prefetch: {
|
|
|
|
SDOperand Ops[4];
|
|
|
|
Ops[0] = getRoot();
|
|
|
|
Ops[1] = getValue(I.getOperand(1));
|
|
|
|
Ops[2] = getValue(I.getOperand(2));
|
|
|
|
Ops[3] = getValue(I.getOperand(3));
|
|
|
|
DAG.setRoot(DAG.getNode(ISD::PREFETCH, MVT::Other, &Ops[0], 4));
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-02-16 09:24:58 +08:00
|
|
|
case Intrinsic::memory_barrier: {
|
|
|
|
SDOperand Ops[6];
|
|
|
|
Ops[0] = getRoot();
|
|
|
|
for (int x = 1; x < 6; ++x)
|
|
|
|
Ops[x] = getValue(I.getOperand(x));
|
|
|
|
|
|
|
|
DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, MVT::Other, &Ops[0], 6));
|
|
|
|
return 0;
|
|
|
|
}
|
2008-02-21 14:45:13 +08:00
|
|
|
case Intrinsic::atomic_lcs: {
|
|
|
|
SDOperand Root = getRoot();
|
|
|
|
SDOperand O3 = getValue(I.getOperand(3));
|
|
|
|
SDOperand L = DAG.getAtomic(ISD::ATOMIC_LCS, Root,
|
|
|
|
getValue(I.getOperand(1)),
|
|
|
|
getValue(I.getOperand(2)),
|
|
|
|
O3, O3.getValueType());
|
|
|
|
setValue(&I, L);
|
|
|
|
DAG.setRoot(L.getValue(1));
|
|
|
|
return 0;
|
|
|
|
}
|
2008-05-06 03:05:59 +08:00
|
|
|
case Intrinsic::atomic_las:
|
|
|
|
return implVisitBinaryAtomic(I, ISD::ATOMIC_LAS);
|
|
|
|
case Intrinsic::atomic_lss:
|
|
|
|
return implVisitBinaryAtomic(I, ISD::ATOMIC_LSS);
|
|
|
|
case Intrinsic::atomic_load_and:
|
|
|
|
return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
|
|
|
|
case Intrinsic::atomic_load_or:
|
|
|
|
return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
|
|
|
|
case Intrinsic::atomic_load_xor:
|
|
|
|
return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
|
|
|
|
case Intrinsic::atomic_load_min:
|
|
|
|
return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
|
|
|
|
case Intrinsic::atomic_load_max:
|
|
|
|
return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
|
|
|
|
case Intrinsic::atomic_load_umin:
|
|
|
|
return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
|
|
|
|
case Intrinsic::atomic_load_umax:
|
|
|
|
return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
|
|
|
|
case Intrinsic::atomic_swap:
|
|
|
|
return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
|
2005-11-10 03:44:01 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2007-12-19 17:48:52 +08:00
|
|
|
void SelectionDAGLowering::LowerCallTo(CallSite CS, SDOperand Callee,
|
2007-02-24 05:45:01 +08:00
|
|
|
bool IsTailCall,
|
2007-05-23 19:08:31 +08:00
|
|
|
MachineBasicBlock *LandingPad) {
|
2007-12-19 17:48:52 +08:00
|
|
|
const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
|
2007-02-22 23:38:06 +08:00
|
|
|
const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
|
2007-05-23 19:08:31 +08:00
|
|
|
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
|
|
|
|
unsigned BeginLabel = 0, EndLabel = 0;
|
2007-12-19 17:48:52 +08:00
|
|
|
|
2007-02-22 23:38:06 +08:00
|
|
|
TargetLowering::ArgListTy Args;
|
|
|
|
TargetLowering::ArgListEntry Entry;
|
2007-12-19 17:48:52 +08:00
|
|
|
Args.reserve(CS.arg_size());
|
|
|
|
for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
|
|
|
|
i != e; ++i) {
|
|
|
|
SDOperand ArgNode = getValue(*i);
|
|
|
|
Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
|
|
|
|
|
|
|
|
unsigned attrInd = i - CS.arg_begin() + 1;
|
|
|
|
Entry.isSExt = CS.paramHasAttr(attrInd, ParamAttr::SExt);
|
|
|
|
Entry.isZExt = CS.paramHasAttr(attrInd, ParamAttr::ZExt);
|
|
|
|
Entry.isInReg = CS.paramHasAttr(attrInd, ParamAttr::InReg);
|
|
|
|
Entry.isSRet = CS.paramHasAttr(attrInd, ParamAttr::StructRet);
|
|
|
|
Entry.isNest = CS.paramHasAttr(attrInd, ParamAttr::Nest);
|
|
|
|
Entry.isByVal = CS.paramHasAttr(attrInd, ParamAttr::ByVal);
|
2008-02-23 01:49:45 +08:00
|
|
|
Entry.Alignment = CS.getParamAlignment(attrInd);
|
2007-02-22 23:38:06 +08:00
|
|
|
Args.push_back(Entry);
|
|
|
|
}
|
|
|
|
|
2008-04-02 08:25:04 +08:00
|
|
|
if (LandingPad && MMI) {
|
2007-05-23 19:08:31 +08:00
|
|
|
// Insert a label before the invoke call to mark the try range. This can be
|
|
|
|
// used to detect deletion of the invoke via the MachineModuleInfo.
|
|
|
|
BeginLabel = MMI->NextLabelID();
|
2008-04-05 07:48:31 +08:00
|
|
|
// Both PendingLoads and PendingExports must be flushed here;
|
|
|
|
// this call might not return.
|
|
|
|
(void)getRoot();
|
|
|
|
DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getControlRoot(),
|
2008-01-31 17:59:15 +08:00
|
|
|
DAG.getConstant(BeginLabel, MVT::i32),
|
|
|
|
DAG.getConstant(1, MVT::i32)));
|
2007-05-23 19:08:31 +08:00
|
|
|
}
|
2007-12-19 17:48:52 +08:00
|
|
|
|
2007-02-22 23:38:06 +08:00
|
|
|
std::pair<SDOperand,SDOperand> Result =
|
2007-12-19 17:48:52 +08:00
|
|
|
TLI.LowerCallTo(getRoot(), CS.getType(),
|
|
|
|
CS.paramHasAttr(0, ParamAttr::SExt),
|
2008-02-15 01:28:50 +08:00
|
|
|
CS.paramHasAttr(0, ParamAttr::ZExt),
|
2007-12-19 17:48:52 +08:00
|
|
|
FTy->isVarArg(), CS.getCallingConv(), IsTailCall,
|
2007-02-22 23:38:06 +08:00
|
|
|
Callee, Args, DAG);
|
2007-12-19 17:48:52 +08:00
|
|
|
if (CS.getType() != Type::VoidTy)
|
|
|
|
setValue(CS.getInstruction(), Result.first);
|
2007-02-22 23:38:06 +08:00
|
|
|
DAG.setRoot(Result.second);
|
2007-05-23 19:08:31 +08:00
|
|
|
|
2008-04-02 08:25:04 +08:00
|
|
|
if (LandingPad && MMI) {
|
2007-05-23 19:08:31 +08:00
|
|
|
// Insert a label at the end of the invoke call to mark the try range. This
|
|
|
|
// can be used to detect deletion of the invoke via the MachineModuleInfo.
|
|
|
|
EndLabel = MMI->NextLabelID();
|
|
|
|
DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
|
2008-01-31 17:59:15 +08:00
|
|
|
DAG.getConstant(EndLabel, MVT::i32),
|
|
|
|
DAG.getConstant(1, MVT::i32)));
|
2007-05-23 19:08:31 +08:00
|
|
|
|
2007-12-19 17:48:52 +08:00
|
|
|
// Inform MachineModuleInfo of range.
|
2007-05-23 19:08:31 +08:00
|
|
|
MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
|
|
|
|
}
|
2007-02-22 23:38:06 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2005-01-07 15:47:53 +08:00
|
|
|
void SelectionDAGLowering::visitCall(CallInst &I) {
|
2005-01-09 06:48:57 +08:00
|
|
|
const char *RenameFn = 0;
|
2005-11-10 03:44:01 +08:00
|
|
|
if (Function *F = I.getCalledFunction()) {
|
2007-09-11 05:15:22 +08:00
|
|
|
if (F->isDeclaration()) {
|
2005-11-10 03:44:01 +08:00
|
|
|
if (unsigned IID = F->getIntrinsicID()) {
|
|
|
|
RenameFn = visitIntrinsicCall(I, IID);
|
|
|
|
if (!RenameFn)
|
|
|
|
return;
|
2007-09-11 05:15:22 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Check for well-known libc/libm calls. If the function is internal, it
|
|
|
|
// can't be a library call.
|
|
|
|
unsigned NameLen = F->getNameLen();
|
|
|
|
if (!F->hasInternalLinkage() && NameLen) {
|
|
|
|
const char *NameStr = F->getNameStart();
|
|
|
|
if (NameStr[0] == 'c' &&
|
|
|
|
((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
|
|
|
|
(NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
|
|
|
|
if (I.getNumOperands() == 3 && // Basic sanity checks.
|
|
|
|
I.getOperand(1)->getType()->isFloatingPoint() &&
|
|
|
|
I.getType() == I.getOperand(1)->getType() &&
|
|
|
|
I.getType() == I.getOperand(2)->getType()) {
|
|
|
|
SDOperand LHS = getValue(I.getOperand(1));
|
|
|
|
SDOperand RHS = getValue(I.getOperand(2));
|
|
|
|
setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
|
|
|
|
LHS, RHS));
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
} else if (NameStr[0] == 'f' &&
|
|
|
|
((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
|
2007-09-27 05:10:55 +08:00
|
|
|
(NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
|
|
|
|
(NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
|
2007-09-11 05:15:22 +08:00
|
|
|
if (I.getNumOperands() == 2 && // Basic sanity checks.
|
|
|
|
I.getOperand(1)->getType()->isFloatingPoint() &&
|
|
|
|
I.getType() == I.getOperand(1)->getType()) {
|
|
|
|
SDOperand Tmp = getValue(I.getOperand(1));
|
|
|
|
setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
} else if (NameStr[0] == 's' &&
|
|
|
|
((NameLen == 3 && !strcmp(NameStr, "sin")) ||
|
2007-09-27 05:10:55 +08:00
|
|
|
(NameLen == 4 && !strcmp(NameStr, "sinf")) ||
|
|
|
|
(NameLen == 4 && !strcmp(NameStr, "sinl")))) {
|
2007-09-11 05:15:22 +08:00
|
|
|
if (I.getNumOperands() == 2 && // Basic sanity checks.
|
|
|
|
I.getOperand(1)->getType()->isFloatingPoint() &&
|
|
|
|
I.getType() == I.getOperand(1)->getType()) {
|
|
|
|
SDOperand Tmp = getValue(I.getOperand(1));
|
|
|
|
setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
} else if (NameStr[0] == 'c' &&
|
|
|
|
((NameLen == 3 && !strcmp(NameStr, "cos")) ||
|
2007-09-27 05:10:55 +08:00
|
|
|
(NameLen == 4 && !strcmp(NameStr, "cosf")) ||
|
|
|
|
(NameLen == 4 && !strcmp(NameStr, "cosl")))) {
|
2007-09-11 05:15:22 +08:00
|
|
|
if (I.getNumOperands() == 2 && // Basic sanity checks.
|
|
|
|
I.getOperand(1)->getType()->isFloatingPoint() &&
|
|
|
|
I.getType() == I.getOperand(1)->getType()) {
|
|
|
|
SDOperand Tmp = getValue(I.getOperand(1));
|
|
|
|
setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
|
|
|
|
return;
|
2005-04-30 12:43:14 +08:00
|
|
|
}
|
2005-04-02 13:26:53 +08:00
|
|
|
}
|
2007-09-11 05:15:22 +08:00
|
|
|
}
|
2006-01-27 06:24:51 +08:00
|
|
|
} else if (isa<InlineAsm>(I.getOperand(0))) {
|
2007-12-18 02:08:19 +08:00
|
|
|
visitInlineAsm(&I);
|
2006-01-27 06:24:51 +08:00
|
|
|
return;
|
2005-11-10 03:44:01 +08:00
|
|
|
}
|
2005-04-22 06:36:52 +08:00
|
|
|
|
2005-01-09 06:48:57 +08:00
|
|
|
SDOperand Callee;
|
|
|
|
if (!RenameFn)
|
|
|
|
Callee = getValue(I.getOperand(0));
|
|
|
|
else
|
|
|
|
Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
|
2007-05-23 19:08:31 +08:00
|
|
|
|
2007-12-19 17:48:52 +08:00
|
|
|
LowerCallTo(&I, Callee, I.isTailCall());
|
2005-01-07 15:47:53 +08:00
|
|
|
}
|
|
|
|
|
2007-02-22 23:38:06 +08:00
|
|
|
|
2008-03-12 05:11:25 +08:00
|
|
|
void SelectionDAGLowering::visitGetResult(GetResultInst &I) {
|
2008-04-24 04:25:16 +08:00
|
|
|
if (isa<UndefValue>(I.getOperand(0))) {
|
2008-04-24 04:21:29 +08:00
|
|
|
SDOperand Undef = DAG.getNode(ISD::UNDEF, TLI.getValueType(I.getType()));
|
|
|
|
setValue(&I, Undef);
|
2008-04-28 15:16:35 +08:00
|
|
|
return;
|
2008-04-24 04:21:29 +08:00
|
|
|
}
|
2008-04-28 15:16:35 +08:00
|
|
|
|
|
|
|
// To add support for individual return values with aggregate types,
|
|
|
|
// we'd need a way to take a getresult index and determine which
|
|
|
|
// values of the Call SDNode are associated with it.
|
|
|
|
assert(TLI.getValueType(I.getType(), true) != MVT::Other &&
|
|
|
|
"Individual return values must not be aggregates!");
|
|
|
|
|
|
|
|
SDOperand Call = getValue(I.getOperand(0));
|
|
|
|
setValue(&I, SDOperand(Call.Val, I.getIndex()));
|
2008-03-12 05:11:25 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2007-06-29 07:29:44 +08:00
|
|
|
/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
|
|
|
|
/// this value and returns the result as a ValueVT value. This uses
|
|
|
|
/// Chain/Flag as the input and updates them for the output Chain/Flag.
|
|
|
|
/// If the Flag pointer is NULL, no flag is used.
|
|
|
|
SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
|
2008-04-28 15:16:35 +08:00
|
|
|
SDOperand &Chain,
|
|
|
|
SDOperand *Flag) const {
|
2008-04-26 02:27:55 +08:00
|
|
|
// Assemble the legal parts into the final values.
|
|
|
|
SmallVector<SDOperand, 4> Values(ValueVTs.size());
|
2008-04-28 15:16:35 +08:00
|
|
|
SmallVector<SDOperand, 8> Parts;
|
|
|
|
for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
|
2008-04-26 02:27:55 +08:00
|
|
|
// Copy the legal parts from the registers.
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT ValueVT = ValueVTs[Value];
|
2008-04-26 02:27:55 +08:00
|
|
|
unsigned NumRegs = TLI->getNumRegisters(ValueVT);
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT RegisterVT = RegVTs[Value];
|
2008-04-26 02:27:55 +08:00
|
|
|
|
2008-04-28 15:16:35 +08:00
|
|
|
Parts.resize(NumRegs);
|
2008-04-26 02:27:55 +08:00
|
|
|
for (unsigned i = 0; i != NumRegs; ++i) {
|
2008-04-28 15:16:35 +08:00
|
|
|
SDOperand P;
|
|
|
|
if (Flag == 0)
|
|
|
|
P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT);
|
|
|
|
else {
|
|
|
|
P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT, *Flag);
|
2008-04-26 02:27:55 +08:00
|
|
|
*Flag = P.getValue(2);
|
2008-04-28 15:16:35 +08:00
|
|
|
}
|
|
|
|
Chain = P.getValue(1);
|
2008-04-26 02:27:55 +08:00
|
|
|
Parts[Part+i] = P;
|
|
|
|
}
|
2007-06-29 07:29:44 +08:00
|
|
|
|
2008-04-26 02:27:55 +08:00
|
|
|
Values[Value] = getCopyFromParts(DAG, &Parts[Part], NumRegs, RegisterVT,
|
|
|
|
ValueVT);
|
|
|
|
Part += NumRegs;
|
|
|
|
}
|
2008-04-28 15:16:35 +08:00
|
|
|
|
|
|
|
if (ValueVTs.size() == 1)
|
|
|
|
return Values[0];
|
|
|
|
|
2008-04-26 02:27:55 +08:00
|
|
|
return DAG.getNode(ISD::MERGE_VALUES,
|
|
|
|
DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
|
|
|
|
&Values[0], ValueVTs.size());
|
2007-06-29 07:29:44 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
|
|
|
|
/// specified value into the registers specified by this object. This uses
|
|
|
|
/// Chain/Flag as the input and updates them for the output Chain/Flag.
|
|
|
|
/// If the Flag pointer is NULL, no flag is used.
|
|
|
|
void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
|
|
|
|
SDOperand &Chain, SDOperand *Flag) const {
|
|
|
|
// Get the list of the values's legal parts.
|
2008-04-26 02:27:55 +08:00
|
|
|
unsigned NumRegs = Regs.size();
|
|
|
|
SmallVector<SDOperand, 8> Parts(NumRegs);
|
2008-04-28 15:16:35 +08:00
|
|
|
for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT ValueVT = ValueVTs[Value];
|
2008-04-26 02:27:55 +08:00
|
|
|
unsigned NumParts = TLI->getNumRegisters(ValueVT);
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT RegisterVT = RegVTs[Value];
|
2008-04-26 02:27:55 +08:00
|
|
|
|
|
|
|
getCopyToParts(DAG, Val.getValue(Val.ResNo + Value),
|
|
|
|
&Parts[Part], NumParts, RegisterVT);
|
|
|
|
Part += NumParts;
|
|
|
|
}
|
2007-06-29 07:29:44 +08:00
|
|
|
|
|
|
|
// Copy the parts into the registers.
|
2008-04-26 02:27:55 +08:00
|
|
|
SmallVector<SDOperand, 8> Chains(NumRegs);
|
|
|
|
for (unsigned i = 0; i != NumRegs; ++i) {
|
2008-04-28 15:16:35 +08:00
|
|
|
SDOperand Part;
|
|
|
|
if (Flag == 0)
|
|
|
|
Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
|
|
|
|
else {
|
|
|
|
Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag);
|
2007-06-29 07:29:44 +08:00
|
|
|
*Flag = Part.getValue(1);
|
2008-04-28 15:16:35 +08:00
|
|
|
}
|
|
|
|
Chains[i] = Part.getValue(0);
|
2006-02-24 03:21:04 +08:00
|
|
|
}
|
2008-04-28 15:16:35 +08:00
|
|
|
|
2008-04-29 06:07:13 +08:00
|
|
|
if (NumRegs == 1 || Flag)
|
|
|
|
// If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
|
|
|
|
// flagged to it. That is the CopyToReg nodes and the user are considered
|
|
|
|
// a single scheduling unit. If we create a TokenFactor and return it as
|
|
|
|
// chain, then the TokenFactor is both a predecessor (operand) of the
|
|
|
|
// user as well as a successor (the TF operands are flagged to the user).
|
|
|
|
// c1, f1 = CopyToReg
|
|
|
|
// c2, f2 = CopyToReg
|
|
|
|
// c3 = TokenFactor c1, c2
|
|
|
|
// ...
|
|
|
|
// = op c3, ..., f2
|
|
|
|
Chain = Chains[NumRegs-1];
|
2008-04-28 15:16:35 +08:00
|
|
|
else
|
|
|
|
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
|
2006-02-24 03:21:04 +08:00
|
|
|
}
|
2006-02-23 06:37:12 +08:00
|
|
|
|
2006-02-24 03:21:04 +08:00
|
|
|
/// AddInlineAsmOperands - Add this value to the specified inlineasm node
|
|
|
|
/// operand list. This adds the code marker and includes the number of
|
|
|
|
/// values added into it.
|
|
|
|
void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
|
2006-02-24 04:06:57 +08:00
|
|
|
std::vector<SDOperand> &Ops) const {
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
|
2007-04-09 08:33:58 +08:00
|
|
|
Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
|
2008-04-28 15:16:35 +08:00
|
|
|
for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
|
|
|
|
unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT RegisterVT = RegVTs[Value];
|
2008-04-28 15:16:35 +08:00
|
|
|
for (unsigned i = 0; i != NumRegs; ++i)
|
|
|
|
Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
|
2008-04-26 02:27:55 +08:00
|
|
|
}
|
2006-02-24 03:21:04 +08:00
|
|
|
}
|
2006-02-23 06:37:12 +08:00
|
|
|
|
|
|
|
/// isAllocatableRegister - If the specified register is safe to allocate,
|
|
|
|
/// i.e. it isn't a stack pointer or some other special register, return the
|
|
|
|
/// register class for the register. Otherwise, return null.
|
|
|
|
static const TargetRegisterClass *
|
2006-02-23 07:09:03 +08:00
|
|
|
isAllocatableRegister(unsigned Reg, MachineFunction &MF,
|
2008-02-11 02:45:23 +08:00
|
|
|
const TargetLowering &TLI,
|
|
|
|
const TargetRegisterInfo *TRI) {
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT FoundVT = MVT::Other;
|
2006-04-02 08:24:45 +08:00
|
|
|
const TargetRegisterClass *FoundRC = 0;
|
2008-02-11 02:45:23 +08:00
|
|
|
for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
|
|
|
|
E = TRI->regclass_end(); RCI != E; ++RCI) {
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT ThisVT = MVT::Other;
|
2006-04-02 08:24:45 +08:00
|
|
|
|
2006-02-23 07:09:03 +08:00
|
|
|
const TargetRegisterClass *RC = *RCI;
|
|
|
|
// If none of the the value types for this register class are valid, we
|
|
|
|
// can't use it. For example, 64-bit reg classes on 32-bit targets.
|
|
|
|
for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
|
|
|
|
I != E; ++I) {
|
|
|
|
if (TLI.isTypeLegal(*I)) {
|
2006-04-02 08:24:45 +08:00
|
|
|
// If we have already found this register in a different register class,
|
|
|
|
// choose the one with the largest VT specified. For example, on
|
|
|
|
// PowerPC, we favor f64 register classes over f32.
|
2008-06-09 04:54:56 +08:00
|
|
|
if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
|
2006-04-02 08:24:45 +08:00
|
|
|
ThisVT = *I;
|
|
|
|
break;
|
|
|
|
}
|
2006-02-23 07:09:03 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-04-02 08:24:45 +08:00
|
|
|
if (ThisVT == MVT::Other) continue;
|
2006-02-23 07:09:03 +08:00
|
|
|
|
2006-02-23 06:37:12 +08:00
|
|
|
// NOTE: This isn't ideal. In particular, this might allocate the
|
|
|
|
// frame pointer in functions that need it (due to them not being taken
|
|
|
|
// out of allocation, because a variable sized allocation hasn't been seen
|
|
|
|
// yet). This is a slight code pessimization, but should still work.
|
2006-02-23 07:09:03 +08:00
|
|
|
for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
|
|
|
|
E = RC->allocation_order_end(MF); I != E; ++I)
|
2006-04-02 08:24:45 +08:00
|
|
|
if (*I == Reg) {
|
|
|
|
// We found a matching register class. Keep looking at others in case
|
|
|
|
// we find one with larger registers that this physreg is also in.
|
|
|
|
FoundRC = RC;
|
|
|
|
FoundVT = ThisVT;
|
|
|
|
break;
|
|
|
|
}
|
2006-02-23 06:37:12 +08:00
|
|
|
}
|
2006-04-02 08:24:45 +08:00
|
|
|
return FoundRC;
|
2006-02-23 06:37:12 +08:00
|
|
|
}
|
|
|
|
|
2007-05-01 01:29:31 +08:00
|
|
|
|
|
|
|
namespace {
|
|
|
|
/// AsmOperandInfo - This contains information for each constraint that we are
|
|
|
|
/// lowering.
|
2008-02-26 10:33:44 +08:00
|
|
|
struct SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
|
|
|
|
/// CallOperand - If this is the result output operand or a clobber
|
|
|
|
/// this is null, otherwise it is the incoming operand to the CallInst.
|
|
|
|
/// This gets modified as the asm is processed.
|
2007-05-01 01:29:31 +08:00
|
|
|
SDOperand CallOperand;
|
2008-02-26 10:33:44 +08:00
|
|
|
|
2007-05-01 05:11:17 +08:00
|
|
|
/// AssignedRegs - If this is a register or register class operand, this
|
|
|
|
/// contains the set of register corresponding to the operand.
|
|
|
|
RegsForValue AssignedRegs;
|
|
|
|
|
2008-04-26 02:27:55 +08:00
|
|
|
explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
|
2008-02-26 10:33:44 +08:00
|
|
|
: TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
|
2007-05-01 01:29:31 +08:00
|
|
|
}
|
|
|
|
|
2007-05-01 05:11:17 +08:00
|
|
|
/// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
|
|
|
|
/// busy in OutputRegs/InputRegs.
|
|
|
|
void MarkAllocatedRegs(bool isOutReg, bool isInReg,
|
|
|
|
std::set<unsigned> &OutputRegs,
|
2008-02-21 12:55:52 +08:00
|
|
|
std::set<unsigned> &InputRegs,
|
|
|
|
const TargetRegisterInfo &TRI) const {
|
|
|
|
if (isOutReg) {
|
|
|
|
for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
|
|
|
|
MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
|
|
|
|
}
|
|
|
|
if (isInReg) {
|
|
|
|
for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
|
|
|
|
MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
private:
|
|
|
|
/// MarkRegAndAliases - Mark the specified register and all aliases in the
|
|
|
|
/// specified set.
|
|
|
|
static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
|
|
|
|
const TargetRegisterInfo &TRI) {
|
|
|
|
assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
|
|
|
|
Regs.insert(Reg);
|
|
|
|
if (const unsigned *Aliases = TRI.getAliasSet(Reg))
|
|
|
|
for (; *Aliases; ++Aliases)
|
|
|
|
Regs.insert(*Aliases);
|
|
|
|
}
|
2007-05-01 01:29:31 +08:00
|
|
|
};
|
|
|
|
} // end anon namespace.
|
|
|
|
|
|
|
|
|
2008-02-22 03:43:13 +08:00
|
|
|
/// GetRegistersForValue - Assign registers (virtual or physical) for the
|
|
|
|
/// specified operand. We prefer to assign virtual registers, to allow the
|
|
|
|
/// register allocator handle the assignment process. However, if the asm uses
|
|
|
|
/// features that we can't model on machineinstrs, we have SDISel do the
|
|
|
|
/// allocation. This produces generally horrible, but correct, code.
|
|
|
|
///
|
|
|
|
/// OpInfo describes the operand.
|
|
|
|
/// HasEarlyClobber is true if there are any early clobber constraints (=&r)
|
|
|
|
/// or any explicitly clobbered registers.
|
|
|
|
/// Input and OutputRegs are the set of already allocated physical registers.
|
|
|
|
///
|
2007-05-01 05:11:17 +08:00
|
|
|
void SelectionDAGLowering::
|
2008-02-26 10:33:44 +08:00
|
|
|
GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
|
2006-02-23 06:37:12 +08:00
|
|
|
std::set<unsigned> &OutputRegs,
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
llvm-svn: 25878
2006-02-02 02:59:47 +08:00
|
|
|
std::set<unsigned> &InputRegs) {
|
2007-05-01 05:11:17 +08:00
|
|
|
// Compute whether this value requires an input register, an output register,
|
|
|
|
// or both.
|
|
|
|
bool isOutReg = false;
|
|
|
|
bool isInReg = false;
|
|
|
|
switch (OpInfo.Type) {
|
|
|
|
case InlineAsm::isOutput:
|
|
|
|
isOutReg = true;
|
|
|
|
|
|
|
|
// If this is an early-clobber output, or if there is an input
|
|
|
|
// constraint that matches this, we need to reserve the input register
|
|
|
|
// so no other inputs allocate to it.
|
|
|
|
isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput;
|
|
|
|
break;
|
|
|
|
case InlineAsm::isInput:
|
|
|
|
isInReg = true;
|
|
|
|
isOutReg = false;
|
|
|
|
break;
|
|
|
|
case InlineAsm::isClobber:
|
|
|
|
isOutReg = true;
|
|
|
|
isInReg = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
2008-04-28 14:44:42 +08:00
|
|
|
SmallVector<unsigned, 4> Regs;
|
2007-05-01 05:11:17 +08:00
|
|
|
|
|
|
|
// If this is a constraint for a single physreg, or a constraint for a
|
|
|
|
// register class, find it.
|
|
|
|
std::pair<unsigned, const TargetRegisterClass*> PhysReg =
|
|
|
|
TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
|
|
|
|
OpInfo.ConstraintVT);
|
2006-02-23 06:37:12 +08:00
|
|
|
|
2007-05-01 01:29:31 +08:00
|
|
|
unsigned NumRegs = 1;
|
|
|
|
if (OpInfo.ConstraintVT != MVT::Other)
|
2007-06-21 22:42:22 +08:00
|
|
|
NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT RegVT;
|
|
|
|
MVT ValueVT = OpInfo.ConstraintVT;
|
2006-02-23 06:37:12 +08:00
|
|
|
|
2007-05-01 01:29:31 +08:00
|
|
|
|
2006-11-02 09:41:49 +08:00
|
|
|
// If this is a constraint for a specific physical register, like {r17},
|
|
|
|
// assign it now.
|
2006-02-23 06:37:12 +08:00
|
|
|
if (PhysReg.first) {
|
2007-05-01 01:29:31 +08:00
|
|
|
if (OpInfo.ConstraintVT == MVT::Other)
|
2006-02-23 06:37:12 +08:00
|
|
|
ValueVT = *PhysReg.second->vt_begin();
|
2006-06-09 02:22:48 +08:00
|
|
|
|
|
|
|
// Get the actual register value type. This is important, because the user
|
|
|
|
// may have asked for (e.g.) the AX register in i32 type. We need to
|
|
|
|
// remember that AX is actually i16 to get the right extension.
|
|
|
|
RegVT = *PhysReg.second->vt_begin();
|
2006-02-23 06:37:12 +08:00
|
|
|
|
|
|
|
// This is a explicit reference to a physical register.
|
|
|
|
Regs.push_back(PhysReg.first);
|
|
|
|
|
|
|
|
// If this is an expanded reference, add the rest of the regs to Regs.
|
|
|
|
if (NumRegs != 1) {
|
|
|
|
TargetRegisterClass::iterator I = PhysReg.second->begin();
|
|
|
|
for (; *I != PhysReg.first; ++I)
|
2008-05-15 04:07:51 +08:00
|
|
|
assert(I != PhysReg.second->end() && "Didn't find reg!");
|
2006-02-23 06:37:12 +08:00
|
|
|
|
|
|
|
// Already added the first reg.
|
|
|
|
--NumRegs; ++I;
|
|
|
|
for (; NumRegs; --NumRegs, ++I) {
|
2008-05-15 04:07:51 +08:00
|
|
|
assert(I != PhysReg.second->end() && "Ran out of registers to allocate!");
|
2006-02-23 06:37:12 +08:00
|
|
|
Regs.push_back(*I);
|
|
|
|
}
|
|
|
|
}
|
2008-04-26 02:27:55 +08:00
|
|
|
OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
|
2008-02-21 12:55:52 +08:00
|
|
|
const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
|
|
|
|
OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
|
2007-05-01 05:11:17 +08:00
|
|
|
return;
|
2006-02-23 06:37:12 +08:00
|
|
|
}
|
|
|
|
|
2006-11-02 09:41:49 +08:00
|
|
|
// Otherwise, if this was a reference to an LLVM register class, create vregs
|
|
|
|
// for this reference.
|
|
|
|
std::vector<unsigned> RegClassRegs;
|
2007-06-16 03:11:01 +08:00
|
|
|
const TargetRegisterClass *RC = PhysReg.second;
|
|
|
|
if (RC) {
|
2006-11-02 09:41:49 +08:00
|
|
|
// If this is an early clobber or tied register, our regalloc doesn't know
|
|
|
|
// how to maintain the constraint. If it isn't, go ahead and create vreg
|
|
|
|
// and let the regalloc do the right thing.
|
2007-05-01 05:11:17 +08:00
|
|
|
if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber &&
|
|
|
|
// If there is some other early clobber and this is an input register,
|
|
|
|
// then we are forced to pre-allocate the input reg so it doesn't
|
|
|
|
// conflict with the earlyclobber.
|
|
|
|
!(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) {
|
2006-11-02 09:41:49 +08:00
|
|
|
RegVT = *PhysReg.second->vt_begin();
|
2007-04-12 14:00:20 +08:00
|
|
|
|
2007-05-01 01:29:31 +08:00
|
|
|
if (OpInfo.ConstraintVT == MVT::Other)
|
2007-04-12 14:00:20 +08:00
|
|
|
ValueVT = RegVT;
|
2006-11-02 09:41:49 +08:00
|
|
|
|
|
|
|
// Create the appropriate number of virtual registers.
|
2007-12-31 12:13:23 +08:00
|
|
|
MachineRegisterInfo &RegInfo = MF.getRegInfo();
|
2006-11-02 09:41:49 +08:00
|
|
|
for (; NumRegs; --NumRegs)
|
2007-12-31 12:13:23 +08:00
|
|
|
Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
|
2006-11-02 09:41:49 +08:00
|
|
|
|
2008-04-26 02:27:55 +08:00
|
|
|
OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
|
2007-05-01 05:11:17 +08:00
|
|
|
return;
|
2006-11-02 09:41:49 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Otherwise, we can't allocate it. Let the code below figure out how to
|
|
|
|
// maintain these constraints.
|
|
|
|
RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
|
|
|
|
|
|
|
|
} else {
|
|
|
|
// This is a reference to a register class that doesn't directly correspond
|
|
|
|
// to an LLVM register class. Allocate NumRegs consecutive, available,
|
|
|
|
// registers from the class.
|
2007-05-01 01:29:31 +08:00
|
|
|
RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
|
|
|
|
OpInfo.ConstraintVT);
|
2006-11-02 09:41:49 +08:00
|
|
|
}
|
2007-05-01 05:11:17 +08:00
|
|
|
|
2008-02-11 02:45:23 +08:00
|
|
|
const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
|
2006-02-23 06:37:12 +08:00
|
|
|
unsigned NumAllocated = 0;
|
|
|
|
for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
|
|
|
|
unsigned Reg = RegClassRegs[i];
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
llvm-svn: 25878
2006-02-02 02:59:47 +08:00
|
|
|
// See if this register is available.
|
2006-02-23 06:37:12 +08:00
|
|
|
if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
|
|
|
|
(isInReg && InputRegs.count(Reg))) { // Already used.
|
|
|
|
// Make sure we find consecutive registers.
|
|
|
|
NumAllocated = 0;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
llvm-svn: 25878
2006-02-02 02:59:47 +08:00
|
|
|
// Check to see if this register is allocatable (i.e. don't give out the
|
|
|
|
// stack pointer).
|
2007-06-16 03:11:01 +08:00
|
|
|
if (RC == 0) {
|
2008-02-11 02:45:23 +08:00
|
|
|
RC = isAllocatableRegister(Reg, MF, TLI, TRI);
|
2007-06-16 03:11:01 +08:00
|
|
|
if (!RC) { // Couldn't allocate this register.
|
|
|
|
// Reset NumAllocated to make sure we return consecutive registers.
|
|
|
|
NumAllocated = 0;
|
|
|
|
continue;
|
|
|
|
}
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
llvm-svn: 25878
2006-02-02 02:59:47 +08:00
|
|
|
}
|
|
|
|
|
2006-02-23 06:37:12 +08:00
|
|
|
// Okay, this register is good, we can use it.
|
|
|
|
++NumAllocated;
|
|
|
|
|
2007-04-07 01:47:14 +08:00
|
|
|
// If we allocated enough consecutive registers, succeed.
|
2006-02-23 06:37:12 +08:00
|
|
|
if (NumAllocated == NumRegs) {
|
|
|
|
unsigned RegStart = (i-NumAllocated)+1;
|
|
|
|
unsigned RegEnd = i+1;
|
|
|
|
// Mark all of the allocated registers used.
|
2007-05-01 05:11:17 +08:00
|
|
|
for (unsigned i = RegStart; i != RegEnd; ++i)
|
|
|
|
Regs.push_back(RegClassRegs[i]);
|
2006-02-23 06:37:12 +08:00
|
|
|
|
2008-04-26 02:27:55 +08:00
|
|
|
OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
|
2007-05-01 05:11:17 +08:00
|
|
|
OpInfo.ConstraintVT);
|
2008-02-21 12:55:52 +08:00
|
|
|
OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
|
2007-05-01 05:11:17 +08:00
|
|
|
return;
|
2006-02-23 06:37:12 +08:00
|
|
|
}
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
llvm-svn: 25878
2006-02-02 02:59:47 +08:00
|
|
|
}
|
2006-02-23 06:37:12 +08:00
|
|
|
|
|
|
|
// Otherwise, we couldn't allocate enough registers for this.
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
llvm-svn: 25878
2006-02-02 02:59:47 +08:00
|
|
|
}
|
|
|
|
|
2007-05-01 01:16:27 +08:00
|
|
|
|
2006-01-27 06:24:51 +08:00
|
|
|
/// visitInlineAsm - Handle a call to an InlineAsm object.
|
|
|
|
///
|
2007-12-18 02:08:19 +08:00
|
|
|
void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
|
|
|
|
InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
|
2006-01-27 06:24:51 +08:00
|
|
|
|
2007-04-29 04:49:53 +08:00
|
|
|
/// ConstraintOperands - Information about all of the constraints.
|
2008-02-26 10:33:44 +08:00
|
|
|
std::vector<SDISelAsmOperandInfo> ConstraintOperands;
|
2006-01-27 06:24:51 +08:00
|
|
|
|
|
|
|
SDOperand Chain = getRoot();
|
|
|
|
SDOperand Flag;
|
|
|
|
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
llvm-svn: 25878
2006-02-02 02:59:47 +08:00
|
|
|
std::set<unsigned> OutputRegs, InputRegs;
|
2007-04-29 04:49:53 +08:00
|
|
|
|
|
|
|
// Do a prepass over the constraints, canonicalizing them, and building up the
|
|
|
|
// ConstraintOperands list.
|
|
|
|
std::vector<InlineAsm::ConstraintInfo>
|
|
|
|
ConstraintInfos = IA->ParseConstraints();
|
2007-05-01 05:11:17 +08:00
|
|
|
|
|
|
|
// SawEarlyClobber - Keep track of whether we saw an earlyclobber output
|
|
|
|
// constraint. If so, we can't let the register allocator allocate any input
|
|
|
|
// registers, because it will not know to avoid the earlyclobbered output reg.
|
|
|
|
bool SawEarlyClobber = false;
|
|
|
|
|
2007-12-18 02:08:19 +08:00
|
|
|
unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
|
2008-04-28 07:44:28 +08:00
|
|
|
unsigned ResNo = 0; // ResNo - The result number of the next output.
|
2007-04-29 04:49:53 +08:00
|
|
|
for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
|
2008-02-26 10:33:44 +08:00
|
|
|
ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
|
|
|
|
SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
|
2007-04-29 04:49:53 +08:00
|
|
|
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT OpVT = MVT::Other;
|
2006-02-22 08:56:39 +08:00
|
|
|
|
2007-04-29 04:49:53 +08:00
|
|
|
// Compute the value type for each operand.
|
|
|
|
switch (OpInfo.Type) {
|
2006-02-22 08:56:39 +08:00
|
|
|
case InlineAsm::isOutput:
|
2008-04-28 07:44:28 +08:00
|
|
|
// Indirect outputs just consume an argument.
|
|
|
|
if (OpInfo.isIndirect) {
|
2007-12-18 02:08:19 +08:00
|
|
|
OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
|
2008-04-28 07:44:28 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
// The return value of the call is this value. As such, there is no
|
|
|
|
// corresponding argument.
|
|
|
|
assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
|
|
|
|
if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
|
|
|
|
OpVT = TLI.getValueType(STy->getElementType(ResNo));
|
|
|
|
} else {
|
|
|
|
assert(ResNo == 0 && "Asm only has one result!");
|
|
|
|
OpVT = TLI.getValueType(CS.getType());
|
2006-02-22 08:56:39 +08:00
|
|
|
}
|
2008-04-28 07:44:28 +08:00
|
|
|
++ResNo;
|
2006-02-22 08:56:39 +08:00
|
|
|
break;
|
|
|
|
case InlineAsm::isInput:
|
2007-12-18 02:08:19 +08:00
|
|
|
OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
|
2006-02-22 08:56:39 +08:00
|
|
|
break;
|
|
|
|
case InlineAsm::isClobber:
|
2007-04-29 04:49:53 +08:00
|
|
|
// Nothing to do.
|
2006-02-22 08:56:39 +08:00
|
|
|
break;
|
|
|
|
}
|
2007-04-29 04:49:53 +08:00
|
|
|
|
|
|
|
// If this is an input or an indirect output, process the call argument.
|
2007-11-06 05:20:28 +08:00
|
|
|
// BasicBlocks are labels, currently appearing only in asm's.
|
2007-04-29 04:49:53 +08:00
|
|
|
if (OpInfo.CallOperandVal) {
|
2008-04-27 08:16:18 +08:00
|
|
|
if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal))
|
|
|
|
OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
|
2007-11-06 05:20:28 +08:00
|
|
|
else {
|
|
|
|
OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
|
|
|
|
const Type *OpTy = OpInfo.CallOperandVal->getType();
|
|
|
|
// If this is an indirect operand, the operand is a pointer to the
|
|
|
|
// accessed type.
|
|
|
|
if (OpInfo.isIndirect)
|
|
|
|
OpTy = cast<PointerType>(OpTy)->getElementType();
|
|
|
|
|
2008-05-23 08:34:04 +08:00
|
|
|
// If OpTy is not a single value, it may be a struct/union that we
|
2007-11-06 05:20:28 +08:00
|
|
|
// can tile with integers.
|
2008-05-23 08:34:04 +08:00
|
|
|
if (!OpTy->isSingleValueType() && OpTy->isSized()) {
|
2007-11-06 05:20:28 +08:00
|
|
|
unsigned BitSize = TD->getTypeSizeInBits(OpTy);
|
|
|
|
switch (BitSize) {
|
|
|
|
default: break;
|
|
|
|
case 1:
|
|
|
|
case 8:
|
|
|
|
case 16:
|
|
|
|
case 32:
|
|
|
|
case 64:
|
|
|
|
OpTy = IntegerType::get(BitSize);
|
|
|
|
break;
|
|
|
|
}
|
2007-04-30 02:58:03 +08:00
|
|
|
}
|
2007-11-06 05:20:28 +08:00
|
|
|
|
|
|
|
OpVT = TLI.getValueType(OpTy, true);
|
2007-04-29 04:49:53 +08:00
|
|
|
}
|
|
|
|
}
|
2006-02-22 08:56:39 +08:00
|
|
|
|
2007-04-29 04:49:53 +08:00
|
|
|
OpInfo.ConstraintVT = OpVT;
|
2007-04-29 05:01:43 +08:00
|
|
|
|
2007-05-01 01:16:27 +08:00
|
|
|
// Compute the constraint code and ConstraintType to use.
|
2008-04-27 08:37:18 +08:00
|
|
|
TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
|
2006-02-22 08:56:39 +08:00
|
|
|
|
2007-05-01 05:11:17 +08:00
|
|
|
// Keep track of whether we see an earlyclobber.
|
|
|
|
SawEarlyClobber |= OpInfo.isEarlyClobber;
|
2007-04-29 05:12:06 +08:00
|
|
|
|
2008-02-22 03:43:13 +08:00
|
|
|
// If we see a clobber of a register, it is an early clobber.
|
2008-02-22 04:54:31 +08:00
|
|
|
if (!SawEarlyClobber &&
|
|
|
|
OpInfo.Type == InlineAsm::isClobber &&
|
|
|
|
OpInfo.ConstraintType == TargetLowering::C_Register) {
|
|
|
|
// Note that we want to ignore things that we don't trick here, like
|
|
|
|
// dirflag, fpsr, flags, etc.
|
|
|
|
std::pair<unsigned, const TargetRegisterClass*> PhysReg =
|
|
|
|
TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
|
|
|
|
OpInfo.ConstraintVT);
|
|
|
|
if (PhysReg.first || PhysReg.second) {
|
|
|
|
// This is a register we know of.
|
|
|
|
SawEarlyClobber = true;
|
|
|
|
}
|
|
|
|
}
|
2008-02-22 03:43:13 +08:00
|
|
|
|
2007-04-29 05:12:06 +08:00
|
|
|
// If this is a memory input, and if the operand is not indirect, do what we
|
|
|
|
// need to to provide an address for the memory input.
|
|
|
|
if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
|
|
|
|
!OpInfo.isIndirect) {
|
|
|
|
assert(OpInfo.Type == InlineAsm::isInput &&
|
|
|
|
"Can only indirectify direct input operands!");
|
|
|
|
|
|
|
|
// Memory operands really want the address of the value. If we don't have
|
|
|
|
// an indirect input, put it in the constpool if we can, otherwise spill
|
|
|
|
// it to a stack slot.
|
|
|
|
|
|
|
|
// If the operand is a float, integer, or vector constant, spill to a
|
|
|
|
// constant pool entry to get its address.
|
|
|
|
Value *OpVal = OpInfo.CallOperandVal;
|
|
|
|
if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
|
|
|
|
isa<ConstantVector>(OpVal)) {
|
|
|
|
OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
|
|
|
|
TLI.getPointerTy());
|
|
|
|
} else {
|
|
|
|
// Otherwise, create a stack slot and emit a store to it before the
|
|
|
|
// asm.
|
|
|
|
const Type *Ty = OpVal->getType();
|
Executive summary: getTypeSize -> getTypeStoreSize / getABITypeSize.
The meaning of getTypeSize was not clear - clarifying it is important
now that we have x86 long double and arbitrary precision integers.
The issue with long double is that it requires 80 bits, and this is
not a multiple of its alignment. This gives a primitive type for
which getTypeSize differed from getABITypeSize. For arbitrary precision
integers it is even worse: there is the minimum number of bits needed to
hold the type (eg: 36 for an i36), the maximum number of bits that will
be overwriten when storing the type (40 bits for i36) and the ABI size
(i.e. the storage size rounded up to a multiple of the alignment; 64 bits
for i36).
This patch removes getTypeSize (not really - it is still there but
deprecated to allow for a gradual transition). Instead there is:
(1) getTypeSizeInBits - a number of bits that suffices to hold all
values of the type. For a primitive type, this is the minimum number
of bits. For an i36 this is 36 bits. For x86 long double it is 80.
This corresponds to gcc's TYPE_PRECISION.
(2) getTypeStoreSizeInBits - the maximum number of bits that is
written when storing the type (or read when reading it). For an
i36 this is 40 bits, for an x86 long double it is 80 bits. This
is the size alias analysis is interested in (getTypeStoreSize
returns the number of bytes). There doesn't seem to be anything
corresponding to this in gcc.
(3) getABITypeSizeInBits - this is getTypeStoreSizeInBits rounded
up to a multiple of the alignment. For an i36 this is 64, for an
x86 long double this is 96 or 128 depending on the OS. This is the
spacing between consecutive elements when you form an array out of
this type (getABITypeSize returns the number of bytes). This is
TYPE_SIZE in gcc.
Since successive elements in a SequentialType (arrays, pointers
and vectors) need to be aligned, the spacing between them will be
given by getABITypeSize. This means that the size of an array
is the length times the getABITypeSize. It also means that GEP
computations need to use getABITypeSize when computing offsets.
Furthermore, if an alloca allocates several elements at once then
these too need to be aligned, so the size of the alloca has to be
the number of elements multiplied by getABITypeSize. Logically
speaking this doesn't have to be the case when allocating just
one element, but it is simpler to also use getABITypeSize in this
case. So alloca's and mallocs should use getABITypeSize. Finally,
since gcc's only notion of size is that given by getABITypeSize, if
you want to output assembler etc the same as gcc then getABITypeSize
is the size you want.
Since a store will overwrite no more than getTypeStoreSize bytes,
and a read will read no more than that many bytes, this is the
notion of size appropriate for alias analysis calculations.
In this patch I have corrected all type size uses except some of
those in ScalarReplAggregates, lib/Codegen, lib/Target (the hard
cases). I will get around to auditing these too at some point,
but I could do with some help.
Finally, I made one change which I think wise but others might
consider pointless and suboptimal: in an unpacked struct the
amount of space allocated for a field is now given by the ABI
size rather than getTypeStoreSize. I did this because every
other place that reserves memory for a type (eg: alloca) now
uses getABITypeSize, and I didn't want to make an exception
for unpacked structs, i.e. I did it to make things more uniform.
This only effects structs containing long doubles and arbitrary
precision integers. If someone wants to pack these types more
tightly they can always use a packed struct.
llvm-svn: 43620
2007-11-02 04:53:16 +08:00
|
|
|
uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
|
2007-04-29 05:12:06 +08:00
|
|
|
unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
|
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
|
|
int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
|
|
|
|
SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
|
|
|
|
Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
|
|
|
|
OpInfo.CallOperand = StackSlot;
|
|
|
|
}
|
|
|
|
|
|
|
|
// There is no longer a Value* corresponding to this operand.
|
|
|
|
OpInfo.CallOperandVal = 0;
|
|
|
|
// It is now an indirect operand.
|
|
|
|
OpInfo.isIndirect = true;
|
|
|
|
}
|
|
|
|
|
2007-05-01 05:11:17 +08:00
|
|
|
// If this constraint is for a specific register, allocate it before
|
|
|
|
// anything else.
|
|
|
|
if (OpInfo.ConstraintType == TargetLowering::C_Register)
|
|
|
|
GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
|
2007-04-29 04:49:53 +08:00
|
|
|
}
|
|
|
|
ConstraintInfos.clear();
|
|
|
|
|
|
|
|
|
2007-05-01 05:11:17 +08:00
|
|
|
// Second pass - Loop over all of the operands, assigning virtual or physregs
|
|
|
|
// to registerclass operands.
|
|
|
|
for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
|
2008-02-26 10:33:44 +08:00
|
|
|
SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
|
2007-05-01 05:11:17 +08:00
|
|
|
|
|
|
|
// C_Register operands have already been allocated, Other/Memory don't need
|
|
|
|
// to be.
|
|
|
|
if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
|
|
|
|
GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
|
|
|
|
}
|
|
|
|
|
2007-04-29 04:49:53 +08:00
|
|
|
// AsmNodeOperands - The operands for the ISD::INLINEASM node.
|
|
|
|
std::vector<SDOperand> AsmNodeOperands;
|
|
|
|
AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
|
|
|
|
AsmNodeOperands.push_back(
|
|
|
|
DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
|
|
|
|
|
2006-02-01 09:28:23 +08:00
|
|
|
|
2006-02-22 07:12:12 +08:00
|
|
|
// Loop over all of the inputs, copying the operand values into the
|
|
|
|
// appropriate registers and processing the output regs.
|
2006-02-23 06:37:12 +08:00
|
|
|
RegsForValue RetValRegs;
|
2008-04-29 12:29:54 +08:00
|
|
|
|
2007-04-29 04:49:53 +08:00
|
|
|
// IndirectStoresToEmit - The set of stores to emit after the inline asm node.
|
2006-02-23 06:37:12 +08:00
|
|
|
std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
|
2006-02-22 07:12:12 +08:00
|
|
|
|
2007-04-29 04:49:53 +08:00
|
|
|
for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
|
2008-02-26 10:33:44 +08:00
|
|
|
SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
|
2006-02-22 08:56:39 +08:00
|
|
|
|
2007-04-29 04:49:53 +08:00
|
|
|
switch (OpInfo.Type) {
|
2006-02-01 09:28:23 +08:00
|
|
|
case InlineAsm::isOutput: {
|
2007-04-29 05:03:16 +08:00
|
|
|
if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
|
|
|
|
OpInfo.ConstraintType != TargetLowering::C_Register) {
|
2007-04-28 14:08:13 +08:00
|
|
|
// Memory output, or 'other' output (e.g. 'X' constraint).
|
2007-04-29 05:12:06 +08:00
|
|
|
assert(OpInfo.isIndirect && "Memory output must be indirect operand");
|
2006-02-28 07:45:39 +08:00
|
|
|
|
|
|
|
// Add information to the INLINEASM node to know about this output.
|
|
|
|
unsigned ResOpType = 4/*MEM*/ | (1 << 3);
|
2007-05-15 09:33:58 +08:00
|
|
|
AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
|
|
|
|
TLI.getPointerTy()));
|
2007-04-29 05:12:06 +08:00
|
|
|
AsmNodeOperands.push_back(OpInfo.CallOperand);
|
2006-02-28 07:45:39 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2007-04-29 05:01:43 +08:00
|
|
|
// Otherwise, this is a register or register class output.
|
2006-02-28 07:45:39 +08:00
|
|
|
|
2006-02-23 06:37:12 +08:00
|
|
|
// Copy the output from the appropriate register. Find a register that
|
|
|
|
// we can use.
|
2007-05-01 05:11:17 +08:00
|
|
|
if (OpInfo.AssignedRegs.Regs.empty()) {
|
2006-12-08 04:04:42 +08:00
|
|
|
cerr << "Couldn't allocate output reg for contraint '"
|
2007-04-29 04:49:53 +08:00
|
|
|
<< OpInfo.ConstraintCode << "'!\n";
|
2006-10-31 15:33:13 +08:00
|
|
|
exit(1);
|
|
|
|
}
|
2006-02-01 09:28:23 +08:00
|
|
|
|
2008-04-29 12:29:54 +08:00
|
|
|
// If this is an indirect operand, store through the pointer after the
|
|
|
|
// asm.
|
|
|
|
if (OpInfo.isIndirect) {
|
2007-05-01 05:11:17 +08:00
|
|
|
IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
|
2007-04-29 04:49:53 +08:00
|
|
|
OpInfo.CallOperandVal));
|
2008-04-29 12:29:54 +08:00
|
|
|
} else {
|
|
|
|
// This is the result value of the call.
|
|
|
|
assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
|
|
|
|
// Concatenate this output onto the outputs list.
|
|
|
|
RetValRegs.append(OpInfo.AssignedRegs);
|
2006-02-01 09:28:23 +08:00
|
|
|
}
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
llvm-svn: 25827
2006-01-31 10:03:41 +08:00
|
|
|
|
|
|
|
// Add information to the INLINEASM node to know that this register is
|
|
|
|
// set.
|
2007-05-01 05:11:17 +08:00
|
|
|
OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG,
|
|
|
|
AsmNodeOperands);
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
llvm-svn: 25827
2006-01-31 10:03:41 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
case InlineAsm::isInput: {
|
2007-04-29 04:49:53 +08:00
|
|
|
SDOperand InOperandVal = OpInfo.CallOperand;
|
2006-02-04 10:16:44 +08:00
|
|
|
|
2007-04-29 04:49:53 +08:00
|
|
|
if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint?
|
Implement matching constraints. We can now say things like this:
%C = call int asm "xyz $0, $1, $2, $3", "=r,r,r,0"(int %A, int %B, int 4)
and get:
xyz r2, r3, r4, r2
note that the r2's are pinned together. Yaay for 2-address instructions.
2342 ----------------------------------------------------------------------
llvm-svn: 25893
2006-02-02 08:25:23 +08:00
|
|
|
// If this is required to match an output register we have already set,
|
|
|
|
// just use its register.
|
2007-04-29 04:49:53 +08:00
|
|
|
unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str());
|
2006-02-04 10:16:44 +08:00
|
|
|
|
2006-02-24 03:21:04 +08:00
|
|
|
// Scan until we find the definition we already emitted of this operand.
|
|
|
|
// When we find it, create a RegsForValue operand.
|
|
|
|
unsigned CurOp = 2; // The first operand.
|
|
|
|
for (; OperandNo; --OperandNo) {
|
|
|
|
// Advance to the next operand.
|
|
|
|
unsigned NumOps =
|
|
|
|
cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
|
2006-07-21 03:02:21 +08:00
|
|
|
assert(((NumOps & 7) == 2 /*REGDEF*/ ||
|
|
|
|
(NumOps & 7) == 4 /*MEM*/) &&
|
2006-02-24 03:21:04 +08:00
|
|
|
"Skipped past definitions?");
|
|
|
|
CurOp += (NumOps>>3)+1;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned NumOps =
|
|
|
|
cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
|
2007-02-01 09:21:12 +08:00
|
|
|
if ((NumOps & 7) == 2 /*REGDEF*/) {
|
|
|
|
// Add NumOps>>3 registers to MatchedRegs.
|
|
|
|
RegsForValue MatchedRegs;
|
2008-04-26 02:27:55 +08:00
|
|
|
MatchedRegs.TLI = &TLI;
|
2008-05-02 08:03:54 +08:00
|
|
|
MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
|
|
|
|
MatchedRegs.RegVTs.push_back(AsmNodeOperands[CurOp+1].getValueType());
|
2007-02-01 09:21:12 +08:00
|
|
|
for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
|
|
|
|
unsigned Reg =
|
|
|
|
cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
|
|
|
|
MatchedRegs.Regs.push_back(Reg);
|
|
|
|
}
|
2006-02-24 03:21:04 +08:00
|
|
|
|
2007-02-01 09:21:12 +08:00
|
|
|
// Use the produced MatchedRegs object to
|
2007-06-29 07:29:44 +08:00
|
|
|
MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
|
2007-02-01 09:21:12 +08:00
|
|
|
MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
|
|
|
|
break;
|
|
|
|
} else {
|
|
|
|
assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
|
2008-02-21 13:27:19 +08:00
|
|
|
assert((NumOps >> 3) == 1 && "Unexpected number of operands");
|
|
|
|
// Add information to the INLINEASM node to know about this input.
|
|
|
|
unsigned ResOpType = 4/*MEM*/ | (1 << 3);
|
|
|
|
AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
|
|
|
|
TLI.getPointerTy()));
|
|
|
|
AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
|
|
|
|
break;
|
2006-02-24 03:21:04 +08:00
|
|
|
}
|
2006-02-24 09:11:24 +08:00
|
|
|
}
|
|
|
|
|
2007-04-29 05:01:43 +08:00
|
|
|
if (OpInfo.ConstraintType == TargetLowering::C_Other) {
|
2007-04-29 04:49:53 +08:00
|
|
|
assert(!OpInfo.isIndirect &&
|
2007-04-28 14:42:38 +08:00
|
|
|
"Don't know how to handle indirect other inputs yet!");
|
|
|
|
|
2007-08-25 08:47:38 +08:00
|
|
|
std::vector<SDOperand> Ops;
|
|
|
|
TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
|
|
|
|
Ops, DAG);
|
|
|
|
if (Ops.empty()) {
|
2006-12-08 04:04:42 +08:00
|
|
|
cerr << "Invalid operand for inline asm constraint '"
|
2007-04-29 04:49:53 +08:00
|
|
|
<< OpInfo.ConstraintCode << "'!\n";
|
2006-11-01 03:41:18 +08:00
|
|
|
exit(1);
|
|
|
|
}
|
2006-02-24 03:21:04 +08:00
|
|
|
|
2006-02-24 09:11:24 +08:00
|
|
|
// Add information to the INLINEASM node to know about this input.
|
2007-08-25 08:47:38 +08:00
|
|
|
unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
|
2007-05-15 09:33:58 +08:00
|
|
|
AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
|
|
|
|
TLI.getPointerTy()));
|
2007-08-25 08:47:38 +08:00
|
|
|
AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
|
2006-02-24 09:11:24 +08:00
|
|
|
break;
|
2007-04-29 05:01:43 +08:00
|
|
|
} else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
|
2007-04-29 05:12:06 +08:00
|
|
|
assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
|
2007-04-28 14:42:38 +08:00
|
|
|
assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
|
|
|
|
"Memory operands expect pointer values");
|
|
|
|
|
2006-02-24 09:11:24 +08:00
|
|
|
// Add information to the INLINEASM node to know about this input.
|
|
|
|
unsigned ResOpType = 4/*MEM*/ | (1 << 3);
|
2007-05-15 09:33:58 +08:00
|
|
|
AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
|
|
|
|
TLI.getPointerTy()));
|
2006-02-24 09:11:24 +08:00
|
|
|
AsmNodeOperands.push_back(InOperandVal);
|
2006-02-24 03:21:04 +08:00
|
|
|
break;
|
Implement matching constraints. We can now say things like this:
%C = call int asm "xyz $0, $1, $2, $3", "=r,r,r,0"(int %A, int %B, int 4)
and get:
xyz r2, r3, r4, r2
note that the r2's are pinned together. Yaay for 2-address instructions.
2342 ----------------------------------------------------------------------
llvm-svn: 25893
2006-02-02 08:25:23 +08:00
|
|
|
}
|
2006-02-24 09:11:24 +08:00
|
|
|
|
2007-04-29 05:01:43 +08:00
|
|
|
assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
|
|
|
|
OpInfo.ConstraintType == TargetLowering::C_Register) &&
|
|
|
|
"Unknown constraint type!");
|
2007-04-29 04:49:53 +08:00
|
|
|
assert(!OpInfo.isIndirect &&
|
2007-04-28 14:42:38 +08:00
|
|
|
"Don't know how to handle indirect register inputs yet!");
|
2006-02-24 09:11:24 +08:00
|
|
|
|
|
|
|
// Copy the input into the appropriate registers.
|
2007-05-01 05:11:17 +08:00
|
|
|
assert(!OpInfo.AssignedRegs.Regs.empty() &&
|
|
|
|
"Couldn't allocate input reg!");
|
2006-02-24 09:11:24 +08:00
|
|
|
|
2007-06-29 07:29:44 +08:00
|
|
|
OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
|
2006-02-24 09:11:24 +08:00
|
|
|
|
2007-05-01 05:11:17 +08:00
|
|
|
OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG,
|
|
|
|
AsmNodeOperands);
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
llvm-svn: 25827
2006-01-31 10:03:41 +08:00
|
|
|
break;
|
|
|
|
}
|
2006-02-24 03:21:04 +08:00
|
|
|
case InlineAsm::isClobber: {
|
|
|
|
// Add the clobbered value to the operand list, so that the register
|
|
|
|
// allocator is aware that the physreg got clobbered.
|
2007-05-01 05:11:17 +08:00
|
|
|
if (!OpInfo.AssignedRegs.Regs.empty())
|
|
|
|
OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG,
|
|
|
|
AsmNodeOperands);
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
llvm-svn: 25827
2006-01-31 10:03:41 +08:00
|
|
|
break;
|
|
|
|
}
|
2006-02-24 03:21:04 +08:00
|
|
|
}
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
llvm-svn: 25827
2006-01-31 10:03:41 +08:00
|
|
|
}
|
2006-01-27 06:24:51 +08:00
|
|
|
|
|
|
|
// Finish up input operands.
|
|
|
|
AsmNodeOperands[0] = Chain;
|
|
|
|
if (Flag.Val) AsmNodeOperands.push_back(Flag);
|
|
|
|
|
2006-08-15 07:53:35 +08:00
|
|
|
Chain = DAG.getNode(ISD::INLINEASM,
|
|
|
|
DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
|
2006-08-08 10:23:42 +08:00
|
|
|
&AsmNodeOperands[0], AsmNodeOperands.size());
|
2006-01-27 06:24:51 +08:00
|
|
|
Flag = Chain.getValue(1);
|
|
|
|
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
llvm-svn: 25827
2006-01-31 10:03:41 +08:00
|
|
|
// If this asm returns a register value, copy the result from that register
|
|
|
|
// and set it as the value of the call.
|
2007-04-12 14:00:20 +08:00
|
|
|
if (!RetValRegs.Regs.empty()) {
|
2007-06-29 07:29:44 +08:00
|
|
|
SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
|
2008-04-29 12:48:56 +08:00
|
|
|
|
|
|
|
// If any of the results of the inline asm is a vector, it may have the
|
|
|
|
// wrong width/num elts. This can happen for register classes that can
|
|
|
|
// contain multiple different value types. The preg or vreg allocated may
|
|
|
|
// not have the same VT as was expected. Convert it to the right type with
|
2007-06-26 00:23:39 +08:00
|
|
|
// bit_convert.
|
2008-04-29 12:48:56 +08:00
|
|
|
if (const StructType *ResSTy = dyn_cast<StructType>(CS.getType())) {
|
|
|
|
for (unsigned i = 0, e = ResSTy->getNumElements(); i != e; ++i) {
|
2008-06-06 20:08:01 +08:00
|
|
|
if (Val.Val->getValueType(i).isVector())
|
2008-04-29 12:48:56 +08:00
|
|
|
Val = DAG.getNode(ISD::BIT_CONVERT,
|
|
|
|
TLI.getValueType(ResSTy->getElementType(i)), Val);
|
|
|
|
}
|
|
|
|
} else {
|
2008-06-06 20:08:01 +08:00
|
|
|
if (Val.getValueType().isVector())
|
2008-04-29 12:48:56 +08:00
|
|
|
Val = DAG.getNode(ISD::BIT_CONVERT, TLI.getValueType(CS.getType()),
|
|
|
|
Val);
|
2007-04-12 14:00:20 +08:00
|
|
|
}
|
2008-04-29 12:48:56 +08:00
|
|
|
|
2007-12-18 02:08:19 +08:00
|
|
|
setValue(CS.getInstruction(), Val);
|
2007-04-12 14:00:20 +08:00
|
|
|
}
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
llvm-svn: 25827
2006-01-31 10:03:41 +08:00
|
|
|
|
|
|
|
std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
|
|
|
|
|
|
|
|
// Process indirect outputs, first output all of the flagged copies out of
|
|
|
|
// physregs.
|
|
|
|
for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
|
2006-02-23 06:37:12 +08:00
|
|
|
RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
llvm-svn: 25827
2006-01-31 10:03:41 +08:00
|
|
|
Value *Ptr = IndirectStoresToEmit[i].second;
|
2007-06-29 07:29:44 +08:00
|
|
|
SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
|
2006-02-23 06:37:12 +08:00
|
|
|
StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
llvm-svn: 25827
2006-01-31 10:03:41 +08:00
|
|
|
}
|
2006-01-27 06:24:51 +08:00
|
|
|
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
llvm-svn: 25827
2006-01-31 10:03:41 +08:00
|
|
|
// Emit the non-flagged stores from the physregs.
|
2006-08-08 10:23:42 +08:00
|
|
|
SmallVector<SDOperand, 8> OutChains;
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
llvm-svn: 25827
2006-01-31 10:03:41 +08:00
|
|
|
for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
|
2007-04-29 04:49:53 +08:00
|
|
|
OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
llvm-svn: 25827
2006-01-31 10:03:41 +08:00
|
|
|
getValue(StoresToEmit[i].second),
|
2006-10-14 05:14:26 +08:00
|
|
|
StoresToEmit[i].second, 0));
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
llvm-svn: 25827
2006-01-31 10:03:41 +08:00
|
|
|
if (!OutChains.empty())
|
2006-08-08 10:23:42 +08:00
|
|
|
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
|
|
|
|
&OutChains[0], OutChains.size());
|
2006-01-27 06:24:51 +08:00
|
|
|
DAG.setRoot(Chain);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2005-01-07 15:47:53 +08:00
|
|
|
void SelectionDAGLowering::visitMalloc(MallocInst &I) {
|
|
|
|
SDOperand Src = getValue(I.getOperand(0));
|
|
|
|
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT IntPtr = TLI.getPointerTy();
|
2005-01-23 07:04:37 +08:00
|
|
|
|
2008-06-09 04:54:56 +08:00
|
|
|
if (IntPtr.bitsLT(Src.getValueType()))
|
2005-01-23 07:04:37 +08:00
|
|
|
Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
|
2008-06-09 04:54:56 +08:00
|
|
|
else if (IntPtr.bitsGT(Src.getValueType()))
|
2005-01-23 07:04:37 +08:00
|
|
|
Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
|
2005-01-07 15:47:53 +08:00
|
|
|
|
|
|
|
// Scale the source by the type size.
|
Executive summary: getTypeSize -> getTypeStoreSize / getABITypeSize.
The meaning of getTypeSize was not clear - clarifying it is important
now that we have x86 long double and arbitrary precision integers.
The issue with long double is that it requires 80 bits, and this is
not a multiple of its alignment. This gives a primitive type for
which getTypeSize differed from getABITypeSize. For arbitrary precision
integers it is even worse: there is the minimum number of bits needed to
hold the type (eg: 36 for an i36), the maximum number of bits that will
be overwriten when storing the type (40 bits for i36) and the ABI size
(i.e. the storage size rounded up to a multiple of the alignment; 64 bits
for i36).
This patch removes getTypeSize (not really - it is still there but
deprecated to allow for a gradual transition). Instead there is:
(1) getTypeSizeInBits - a number of bits that suffices to hold all
values of the type. For a primitive type, this is the minimum number
of bits. For an i36 this is 36 bits. For x86 long double it is 80.
This corresponds to gcc's TYPE_PRECISION.
(2) getTypeStoreSizeInBits - the maximum number of bits that is
written when storing the type (or read when reading it). For an
i36 this is 40 bits, for an x86 long double it is 80 bits. This
is the size alias analysis is interested in (getTypeStoreSize
returns the number of bytes). There doesn't seem to be anything
corresponding to this in gcc.
(3) getABITypeSizeInBits - this is getTypeStoreSizeInBits rounded
up to a multiple of the alignment. For an i36 this is 64, for an
x86 long double this is 96 or 128 depending on the OS. This is the
spacing between consecutive elements when you form an array out of
this type (getABITypeSize returns the number of bytes). This is
TYPE_SIZE in gcc.
Since successive elements in a SequentialType (arrays, pointers
and vectors) need to be aligned, the spacing between them will be
given by getABITypeSize. This means that the size of an array
is the length times the getABITypeSize. It also means that GEP
computations need to use getABITypeSize when computing offsets.
Furthermore, if an alloca allocates several elements at once then
these too need to be aligned, so the size of the alloca has to be
the number of elements multiplied by getABITypeSize. Logically
speaking this doesn't have to be the case when allocating just
one element, but it is simpler to also use getABITypeSize in this
case. So alloca's and mallocs should use getABITypeSize. Finally,
since gcc's only notion of size is that given by getABITypeSize, if
you want to output assembler etc the same as gcc then getABITypeSize
is the size you want.
Since a store will overwrite no more than getTypeStoreSize bytes,
and a read will read no more than that many bytes, this is the
notion of size appropriate for alias analysis calculations.
In this patch I have corrected all type size uses except some of
those in ScalarReplAggregates, lib/Codegen, lib/Target (the hard
cases). I will get around to auditing these too at some point,
but I could do with some help.
Finally, I made one change which I think wise but others might
consider pointless and suboptimal: in an unpacked struct the
amount of space allocated for a field is now given by the ABI
size rather than getTypeStoreSize. I did this because every
other place that reserves memory for a type (eg: alloca) now
uses getABITypeSize, and I didn't want to make an exception
for unpacked structs, i.e. I did it to make things more uniform.
This only effects structs containing long doubles and arbitrary
precision integers. If someone wants to pack these types more
tightly they can always use a packed struct.
llvm-svn: 43620
2007-11-02 04:53:16 +08:00
|
|
|
uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType());
|
2005-01-07 15:47:53 +08:00
|
|
|
Src = DAG.getNode(ISD::MUL, Src.getValueType(),
|
2008-01-17 15:00:52 +08:00
|
|
|
Src, DAG.getIntPtrConstant(ElementSize));
|
2005-01-07 15:47:53 +08:00
|
|
|
|
2006-12-31 13:55:36 +08:00
|
|
|
TargetLowering::ArgListTy Args;
|
|
|
|
TargetLowering::ArgListEntry Entry;
|
|
|
|
Entry.Node = Src;
|
|
|
|
Entry.Ty = TLI.getTargetData()->getIntPtrType();
|
|
|
|
Args.push_back(Entry);
|
2005-01-09 03:26:18 +08:00
|
|
|
|
|
|
|
std::pair<SDOperand,SDOperand> Result =
|
2008-02-15 01:28:50 +08:00
|
|
|
TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, CallingConv::C,
|
|
|
|
true, DAG.getExternalSymbol("malloc", IntPtr), Args, DAG);
|
2005-01-09 03:26:18 +08:00
|
|
|
setValue(&I, Result.first); // Pointers always fit in registers
|
|
|
|
DAG.setRoot(Result.second);
|
2005-01-07 15:47:53 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitFree(FreeInst &I) {
|
2006-12-31 13:55:36 +08:00
|
|
|
TargetLowering::ArgListTy Args;
|
|
|
|
TargetLowering::ArgListEntry Entry;
|
|
|
|
Entry.Node = getValue(I.getOperand(0));
|
|
|
|
Entry.Ty = TLI.getTargetData()->getIntPtrType();
|
|
|
|
Args.push_back(Entry);
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT IntPtr = TLI.getPointerTy();
|
2005-01-09 03:26:18 +08:00
|
|
|
std::pair<SDOperand,SDOperand> Result =
|
2008-02-15 01:28:50 +08:00
|
|
|
TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false,
|
|
|
|
CallingConv::C, true,
|
2005-01-09 03:26:18 +08:00
|
|
|
DAG.getExternalSymbol("free", IntPtr), Args, DAG);
|
|
|
|
DAG.setRoot(Result.second);
|
2005-01-07 15:47:53 +08:00
|
|
|
}
|
|
|
|
|
2008-01-31 02:18:23 +08:00
|
|
|
// EmitInstrWithCustomInserter - This method should be implemented by targets
|
|
|
|
// that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
|
2005-08-27 04:54:47 +08:00
|
|
|
// instructions are special in various ways, which require special support to
|
|
|
|
// insert. The specified MachineInstr is created but not inserted into any
|
|
|
|
// basic blocks, and the scheduler passes ownership of it to this method.
|
2008-01-31 02:18:23 +08:00
|
|
|
MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
2005-08-27 04:54:47 +08:00
|
|
|
MachineBasicBlock *MBB) {
|
2006-12-08 04:04:42 +08:00
|
|
|
cerr << "If a target marks an instruction with "
|
|
|
|
<< "'usesCustomDAGSchedInserter', it must implement "
|
2008-01-31 02:18:23 +08:00
|
|
|
<< "TargetLowering::EmitInstrWithCustomInserter!\n";
|
2005-08-27 04:54:47 +08:00
|
|
|
abort();
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2005-01-09 08:00:49 +08:00
|
|
|
void SelectionDAGLowering::visitVAStart(CallInst &I) {
|
2006-01-26 02:21:52 +08:00
|
|
|
DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
|
|
|
|
getValue(I.getOperand(1)),
|
|
|
|
DAG.getSrcValue(I.getOperand(1))));
|
2005-01-09 08:00:49 +08:00
|
|
|
}
|
|
|
|
|
2005-01-07 15:47:53 +08:00
|
|
|
void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
|
2006-01-26 02:21:52 +08:00
|
|
|
SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
|
|
|
|
getValue(I.getOperand(0)),
|
|
|
|
DAG.getSrcValue(I.getOperand(0)));
|
|
|
|
setValue(&I, V);
|
|
|
|
DAG.setRoot(V.getValue(1));
|
2005-01-07 15:47:53 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitVAEnd(CallInst &I) {
|
2006-01-26 02:21:52 +08:00
|
|
|
DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
|
|
|
|
getValue(I.getOperand(1)),
|
|
|
|
DAG.getSrcValue(I.getOperand(1))));
|
2005-01-07 15:47:53 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitVACopy(CallInst &I) {
|
2006-01-26 02:21:52 +08:00
|
|
|
DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
|
|
|
|
getValue(I.getOperand(1)),
|
|
|
|
getValue(I.getOperand(2)),
|
|
|
|
DAG.getSrcValue(I.getOperand(1)),
|
|
|
|
DAG.getSrcValue(I.getOperand(2))));
|
2005-01-07 15:47:53 +08:00
|
|
|
}
|
|
|
|
|
2006-04-13 00:20:43 +08:00
|
|
|
/// TargetLowering::LowerArguments - This is the default LowerArguments
|
|
|
|
/// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
|
2006-05-17 06:53:20 +08:00
|
|
|
/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
|
|
|
|
/// integrated into SDISel.
|
2006-04-13 00:20:43 +08:00
|
|
|
std::vector<SDOperand>
|
|
|
|
TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
|
|
|
|
// Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
|
|
|
|
std::vector<SDOperand> Ops;
|
2006-05-16 14:45:34 +08:00
|
|
|
Ops.push_back(DAG.getRoot());
|
2006-04-13 00:20:43 +08:00
|
|
|
Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
|
|
|
|
Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
|
|
|
|
|
|
|
|
// Add one result value for each formal argument.
|
2008-06-06 20:08:01 +08:00
|
|
|
std::vector<MVT> RetVals;
|
2007-01-29 02:01:49 +08:00
|
|
|
unsigned j = 1;
|
2007-01-29 00:04:40 +08:00
|
|
|
for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
|
|
|
|
I != E; ++I, ++j) {
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT VT = getValueType(I->getType());
|
2008-03-21 17:14:45 +08:00
|
|
|
ISD::ArgFlagsTy Flags;
|
2007-02-13 21:50:08 +08:00
|
|
|
unsigned OriginalAlignment =
|
2007-02-14 13:52:17 +08:00
|
|
|
getTargetData()->getABITypeAlignment(I->getType());
|
2007-02-13 21:50:08 +08:00
|
|
|
|
2007-11-29 01:07:01 +08:00
|
|
|
if (F.paramHasAttr(j, ParamAttr::ZExt))
|
2008-03-21 17:14:45 +08:00
|
|
|
Flags.setZExt();
|
2007-11-29 01:07:01 +08:00
|
|
|
if (F.paramHasAttr(j, ParamAttr::SExt))
|
2008-03-21 17:14:45 +08:00
|
|
|
Flags.setSExt();
|
2007-11-29 01:07:01 +08:00
|
|
|
if (F.paramHasAttr(j, ParamAttr::InReg))
|
2008-03-21 17:14:45 +08:00
|
|
|
Flags.setInReg();
|
2007-11-29 01:07:01 +08:00
|
|
|
if (F.paramHasAttr(j, ParamAttr::StructRet))
|
2008-03-21 17:14:45 +08:00
|
|
|
Flags.setSRet();
|
2007-11-29 01:07:01 +08:00
|
|
|
if (F.paramHasAttr(j, ParamAttr::ByVal)) {
|
2008-03-21 17:14:45 +08:00
|
|
|
Flags.setByVal();
|
2007-08-10 22:44:42 +08:00
|
|
|
const PointerType *Ty = cast<PointerType>(I->getType());
|
2008-01-14 05:19:59 +08:00
|
|
|
const Type *ElementTy = Ty->getElementType();
|
2008-03-21 17:14:45 +08:00
|
|
|
unsigned FrameAlign = getByValTypeAlignment(ElementTy);
|
2008-01-14 05:19:59 +08:00
|
|
|
unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
|
2008-02-23 01:49:45 +08:00
|
|
|
// For ByVal, alignment should be passed from FE. BE will guess if
|
|
|
|
// this info is not there but there are cases it cannot get right.
|
|
|
|
if (F.getParamAlignment(j))
|
2008-03-21 17:14:45 +08:00
|
|
|
FrameAlign = F.getParamAlignment(j);
|
|
|
|
Flags.setByValAlign(FrameAlign);
|
|
|
|
Flags.setByValSize(FrameSize);
|
2007-08-10 22:44:42 +08:00
|
|
|
}
|
2007-11-29 01:07:01 +08:00
|
|
|
if (F.paramHasAttr(j, ParamAttr::Nest))
|
2008-03-21 17:14:45 +08:00
|
|
|
Flags.setNest();
|
|
|
|
Flags.setOrigAlign(OriginalAlignment);
|
2008-02-12 04:58:28 +08:00
|
|
|
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT RegisterVT = getRegisterType(VT);
|
2008-02-12 04:58:28 +08:00
|
|
|
unsigned NumRegs = getNumRegisters(VT);
|
|
|
|
for (unsigned i = 0; i != NumRegs; ++i) {
|
|
|
|
RetVals.push_back(RegisterVT);
|
2008-04-15 01:17:14 +08:00
|
|
|
ISD::ArgFlagsTy MyFlags = Flags;
|
2008-04-13 21:40:22 +08:00
|
|
|
if (NumRegs > 1 && i == 0)
|
2008-04-15 16:08:50 +08:00
|
|
|
MyFlags.setSplit();
|
2008-02-12 04:58:28 +08:00
|
|
|
// if it isn't first piece, alignment must be 1
|
2008-04-13 21:40:22 +08:00
|
|
|
else if (i > 0)
|
2008-04-15 01:17:14 +08:00
|
|
|
MyFlags.setOrigAlign(1);
|
|
|
|
Ops.push_back(DAG.getArgFlags(MyFlags));
|
2007-06-29 07:29:44 +08:00
|
|
|
}
|
2006-04-13 00:20:43 +08:00
|
|
|
}
|
2006-04-26 07:03:35 +08:00
|
|
|
|
2006-05-16 14:45:34 +08:00
|
|
|
RetVals.push_back(MVT::Other);
|
2006-04-13 00:20:43 +08:00
|
|
|
|
|
|
|
// Create the node.
|
2006-08-15 07:53:35 +08:00
|
|
|
SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
|
In SDISel, for targets that support FORMAL_ARGUMENTS nodes, lower this
node as soon as we create it in SDISel. Previously we would lower it in
legalize. The problem with this is that it only exposes the argument
loads implied by FORMAL_ARGUMENTs after legalize, so that only dag combine 2
can hack on them. This causes us to miss some optimizations because
datatype expansion also happens here.
Exposing the loads early allows us to do optimizations on them. For example
we now compile arg-cast.ll to:
_foo:
movl $2147483647, %eax
andl 8(%esp), %eax
ret
where we previously produced:
_foo:
subl $12, %esp
movsd 16(%esp), %xmm0
movsd %xmm0, (%esp)
movl $2147483647, %eax
andl 4(%esp), %eax
addl $12, %esp
ret
It might also make sense to do this for ISD::CALL nodes, which have implicit
stores on many targets.
llvm-svn: 47054
2008-02-13 15:39:09 +08:00
|
|
|
DAG.getVTList(&RetVals[0], RetVals.size()),
|
2006-08-08 10:23:42 +08:00
|
|
|
&Ops[0], Ops.size()).Val;
|
In SDISel, for targets that support FORMAL_ARGUMENTS nodes, lower this
node as soon as we create it in SDISel. Previously we would lower it in
legalize. The problem with this is that it only exposes the argument
loads implied by FORMAL_ARGUMENTs after legalize, so that only dag combine 2
can hack on them. This causes us to miss some optimizations because
datatype expansion also happens here.
Exposing the loads early allows us to do optimizations on them. For example
we now compile arg-cast.ll to:
_foo:
movl $2147483647, %eax
andl 8(%esp), %eax
ret
where we previously produced:
_foo:
subl $12, %esp
movsd 16(%esp), %xmm0
movsd %xmm0, (%esp)
movl $2147483647, %eax
andl 4(%esp), %eax
addl $12, %esp
ret
It might also make sense to do this for ISD::CALL nodes, which have implicit
stores on many targets.
llvm-svn: 47054
2008-02-13 15:39:09 +08:00
|
|
|
|
|
|
|
// Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
|
|
|
|
// allows exposing the loads that may be part of the argument access to the
|
|
|
|
// first DAGCombiner pass.
|
|
|
|
SDOperand TmpRes = LowerOperation(SDOperand(Result, 0), DAG);
|
|
|
|
|
|
|
|
// The number of results should match up, except that the lowered one may have
|
|
|
|
// an extra flag result.
|
|
|
|
assert((Result->getNumValues() == TmpRes.Val->getNumValues() ||
|
|
|
|
(Result->getNumValues()+1 == TmpRes.Val->getNumValues() &&
|
|
|
|
TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
|
|
|
|
&& "Lowering produced unexpected number of results!");
|
|
|
|
Result = TmpRes.Val;
|
|
|
|
|
2007-07-03 00:18:06 +08:00
|
|
|
unsigned NumArgRegs = Result->getNumValues() - 1;
|
|
|
|
DAG.setRoot(SDOperand(Result, NumArgRegs));
|
2006-04-13 00:20:43 +08:00
|
|
|
|
|
|
|
// Set up the return result vector.
|
|
|
|
Ops.clear();
|
|
|
|
unsigned i = 0;
|
2006-12-31 13:55:36 +08:00
|
|
|
unsigned Idx = 1;
|
|
|
|
for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
|
|
|
|
++I, ++Idx) {
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT VT = getValueType(I->getType());
|
|
|
|
MVT PartVT = getRegisterType(VT);
|
2008-02-12 04:58:28 +08:00
|
|
|
|
|
|
|
unsigned NumParts = getNumRegisters(VT);
|
|
|
|
SmallVector<SDOperand, 4> Parts(NumParts);
|
|
|
|
for (unsigned j = 0; j != NumParts; ++j)
|
|
|
|
Parts[j] = SDOperand(Result, i++);
|
|
|
|
|
|
|
|
ISD::NodeType AssertOp = ISD::DELETED_NODE;
|
|
|
|
if (F.paramHasAttr(Idx, ParamAttr::SExt))
|
|
|
|
AssertOp = ISD::AssertSext;
|
|
|
|
else if (F.paramHasAttr(Idx, ParamAttr::ZExt))
|
|
|
|
AssertOp = ISD::AssertZext;
|
|
|
|
|
|
|
|
Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT,
|
2008-03-09 17:38:46 +08:00
|
|
|
AssertOp));
|
2006-04-13 00:20:43 +08:00
|
|
|
}
|
2007-07-03 00:18:06 +08:00
|
|
|
assert(i == NumArgRegs && "Argument register count mismatch!");
|
2006-04-13 00:20:43 +08:00
|
|
|
return Ops;
|
|
|
|
}
|
|
|
|
|
2006-05-17 06:53:20 +08:00
|
|
|
|
|
|
|
/// TargetLowering::LowerCallTo - This is the default LowerCallTo
|
|
|
|
/// implementation, which just inserts an ISD::CALL node, which is later custom
|
|
|
|
/// lowered by the target to something concrete. FIXME: When all targets are
|
|
|
|
/// migrated to using ISD::CALL, this hook should be integrated into SDISel.
|
|
|
|
std::pair<SDOperand, SDOperand>
|
2008-02-15 01:28:50 +08:00
|
|
|
TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
|
|
|
|
bool RetSExt, bool RetZExt, bool isVarArg,
|
|
|
|
unsigned CallingConv, bool isTailCall,
|
2006-05-17 06:53:20 +08:00
|
|
|
SDOperand Callee,
|
|
|
|
ArgListTy &Args, SelectionDAG &DAG) {
|
2006-08-17 06:57:46 +08:00
|
|
|
SmallVector<SDOperand, 32> Ops;
|
2006-05-17 06:53:20 +08:00
|
|
|
Ops.push_back(Chain); // Op#0 - Chain
|
|
|
|
Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
|
|
|
|
Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
|
|
|
|
Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
|
|
|
|
Ops.push_back(Callee);
|
|
|
|
|
|
|
|
// Handle all of the outgoing arguments.
|
|
|
|
for (unsigned i = 0, e = Args.size(); i != e; ++i) {
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT VT = getValueType(Args[i].Ty);
|
2006-12-31 13:55:36 +08:00
|
|
|
SDOperand Op = Args[i].Node;
|
2008-03-21 17:14:45 +08:00
|
|
|
ISD::ArgFlagsTy Flags;
|
2007-02-13 21:50:08 +08:00
|
|
|
unsigned OriginalAlignment =
|
2007-02-14 13:52:17 +08:00
|
|
|
getTargetData()->getABITypeAlignment(Args[i].Ty);
|
2008-03-21 17:14:45 +08:00
|
|
|
|
2007-03-08 00:25:09 +08:00
|
|
|
if (Args[i].isZExt)
|
2008-03-21 17:14:45 +08:00
|
|
|
Flags.setZExt();
|
|
|
|
if (Args[i].isSExt)
|
|
|
|
Flags.setSExt();
|
2007-03-06 14:10:33 +08:00
|
|
|
if (Args[i].isInReg)
|
2008-03-21 17:14:45 +08:00
|
|
|
Flags.setInReg();
|
2007-03-06 14:10:33 +08:00
|
|
|
if (Args[i].isSRet)
|
2008-03-21 17:14:45 +08:00
|
|
|
Flags.setSRet();
|
2007-08-20 23:18:24 +08:00
|
|
|
if (Args[i].isByVal) {
|
2008-03-21 17:14:45 +08:00
|
|
|
Flags.setByVal();
|
2007-08-20 23:18:24 +08:00
|
|
|
const PointerType *Ty = cast<PointerType>(Args[i].Ty);
|
2008-01-14 05:19:59 +08:00
|
|
|
const Type *ElementTy = Ty->getElementType();
|
2008-03-21 17:14:45 +08:00
|
|
|
unsigned FrameAlign = getByValTypeAlignment(ElementTy);
|
2008-01-14 05:19:59 +08:00
|
|
|
unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
|
2008-02-23 01:49:45 +08:00
|
|
|
// For ByVal, alignment should come from FE. BE will guess if this
|
|
|
|
// info is not there but there are cases it cannot get right.
|
|
|
|
if (Args[i].Alignment)
|
2008-03-21 17:14:45 +08:00
|
|
|
FrameAlign = Args[i].Alignment;
|
|
|
|
Flags.setByValAlign(FrameAlign);
|
|
|
|
Flags.setByValSize(FrameSize);
|
2007-08-20 23:18:24 +08:00
|
|
|
}
|
2007-07-27 20:58:54 +08:00
|
|
|
if (Args[i].isNest)
|
2008-03-21 17:14:45 +08:00
|
|
|
Flags.setNest();
|
|
|
|
Flags.setOrigAlign(OriginalAlignment);
|
2008-02-12 04:58:28 +08:00
|
|
|
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT PartVT = getRegisterType(VT);
|
2008-02-12 04:58:28 +08:00
|
|
|
unsigned NumParts = getNumRegisters(VT);
|
|
|
|
SmallVector<SDOperand, 4> Parts(NumParts);
|
|
|
|
ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
|
|
|
|
|
|
|
|
if (Args[i].isSExt)
|
|
|
|
ExtendKind = ISD::SIGN_EXTEND;
|
|
|
|
else if (Args[i].isZExt)
|
|
|
|
ExtendKind = ISD::ZERO_EXTEND;
|
|
|
|
|
|
|
|
getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, ExtendKind);
|
|
|
|
|
|
|
|
for (unsigned i = 0; i != NumParts; ++i) {
|
|
|
|
// if it isn't first piece, alignment must be 1
|
2008-03-21 17:14:45 +08:00
|
|
|
ISD::ArgFlagsTy MyFlags = Flags;
|
2008-04-13 21:40:22 +08:00
|
|
|
if (NumParts > 1 && i == 0)
|
2008-04-15 16:08:50 +08:00
|
|
|
MyFlags.setSplit();
|
2008-04-13 21:40:22 +08:00
|
|
|
else if (i != 0)
|
2008-03-21 17:14:45 +08:00
|
|
|
MyFlags.setOrigAlign(1);
|
2008-02-12 04:58:28 +08:00
|
|
|
|
|
|
|
Ops.push_back(Parts[i]);
|
2008-03-21 17:14:45 +08:00
|
|
|
Ops.push_back(DAG.getArgFlags(MyFlags));
|
2007-07-03 00:18:06 +08:00
|
|
|
}
|
2006-05-17 06:53:20 +08:00
|
|
|
}
|
|
|
|
|
2008-03-12 05:11:25 +08:00
|
|
|
// Figure out the result value types. We start by making a list of
|
2008-04-26 02:27:55 +08:00
|
|
|
// the potentially illegal return value types.
|
2008-06-06 20:08:01 +08:00
|
|
|
SmallVector<MVT, 4> LoweredRetTys;
|
|
|
|
SmallVector<MVT, 4> RetTys;
|
2008-04-26 02:27:55 +08:00
|
|
|
ComputeValueVTs(*this, RetTy, RetTys);
|
2008-03-12 05:11:25 +08:00
|
|
|
|
2008-04-26 02:27:55 +08:00
|
|
|
// Then we translate that to a list of legal types.
|
|
|
|
for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT VT = RetTys[I];
|
|
|
|
MVT RegisterVT = getRegisterType(VT);
|
2008-03-12 05:11:25 +08:00
|
|
|
unsigned NumRegs = getNumRegisters(VT);
|
|
|
|
for (unsigned i = 0; i != NumRegs; ++i)
|
|
|
|
LoweredRetTys.push_back(RegisterVT);
|
|
|
|
}
|
2006-05-17 06:53:20 +08:00
|
|
|
|
2008-03-12 05:11:25 +08:00
|
|
|
LoweredRetTys.push_back(MVT::Other); // Always has a chain.
|
2006-05-17 06:53:20 +08:00
|
|
|
|
2007-06-29 07:29:44 +08:00
|
|
|
// Create the CALL node.
|
2006-08-17 06:57:46 +08:00
|
|
|
SDOperand Res = DAG.getNode(ISD::CALL,
|
2008-03-12 05:11:25 +08:00
|
|
|
DAG.getVTList(&LoweredRetTys[0],
|
|
|
|
LoweredRetTys.size()),
|
2006-08-17 06:57:46 +08:00
|
|
|
&Ops[0], Ops.size());
|
2008-03-12 05:11:25 +08:00
|
|
|
Chain = Res.getValue(LoweredRetTys.size() - 1);
|
2007-06-29 07:29:44 +08:00
|
|
|
|
|
|
|
// Gather up the call result into a single value.
|
|
|
|
if (RetTy != Type::VoidTy) {
|
2008-02-15 01:28:50 +08:00
|
|
|
ISD::NodeType AssertOp = ISD::DELETED_NODE;
|
|
|
|
|
|
|
|
if (RetSExt)
|
|
|
|
AssertOp = ISD::AssertSext;
|
|
|
|
else if (RetZExt)
|
2007-06-29 07:29:44 +08:00
|
|
|
AssertOp = ISD::AssertZext;
|
2008-02-15 01:28:50 +08:00
|
|
|
|
2008-03-12 05:11:25 +08:00
|
|
|
SmallVector<SDOperand, 4> ReturnValues;
|
|
|
|
unsigned RegNo = 0;
|
2008-04-26 02:27:55 +08:00
|
|
|
for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT VT = RetTys[I];
|
|
|
|
MVT RegisterVT = getRegisterType(VT);
|
2008-03-12 05:11:25 +08:00
|
|
|
unsigned NumRegs = getNumRegisters(VT);
|
|
|
|
unsigned RegNoEnd = NumRegs + RegNo;
|
|
|
|
SmallVector<SDOperand, 4> Results;
|
|
|
|
for (; RegNo != RegNoEnd; ++RegNo)
|
|
|
|
Results.push_back(Res.getValue(RegNo));
|
|
|
|
SDOperand ReturnValue =
|
|
|
|
getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT,
|
|
|
|
AssertOp);
|
|
|
|
ReturnValues.push_back(ReturnValue);
|
|
|
|
}
|
|
|
|
Res = ReturnValues.size() == 1 ? ReturnValues.front() :
|
|
|
|
DAG.getNode(ISD::MERGE_VALUES,
|
|
|
|
DAG.getVTList(&RetTys[0], RetTys.size()),
|
|
|
|
&ReturnValues[0], ReturnValues.size());
|
2006-05-17 06:53:20 +08:00
|
|
|
}
|
2007-06-29 07:29:44 +08:00
|
|
|
|
|
|
|
return std::make_pair(Res, Chain);
|
2006-05-17 06:53:20 +08:00
|
|
|
}
|
|
|
|
|
2005-05-14 13:50:48 +08:00
|
|
|
SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
|
2005-01-16 15:28:41 +08:00
|
|
|
assert(0 && "LowerOperation not implemented for this target!");
|
|
|
|
abort();
|
2005-02-18 05:39:27 +08:00
|
|
|
return SDOperand();
|
2005-01-16 15:28:41 +08:00
|
|
|
}
|
|
|
|
|
2006-01-28 11:14:31 +08:00
|
|
|
SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
|
|
|
|
SelectionDAG &DAG) {
|
|
|
|
assert(0 && "CustomPromoteOperation not implemented for this target!");
|
|
|
|
abort();
|
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
|
2005-01-11 13:56:49 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// SelectionDAGISel code
|
|
|
|
//===----------------------------------------------------------------------===//
|
2005-01-07 15:47:53 +08:00
|
|
|
|
2008-06-06 20:08:01 +08:00
|
|
|
unsigned SelectionDAGISel::MakeReg(MVT VT) {
|
2007-12-31 12:13:23 +08:00
|
|
|
return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
|
2005-01-07 15:47:53 +08:00
|
|
|
}
|
|
|
|
|
2005-08-17 14:37:43 +08:00
|
|
|
void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
|
2006-10-17 04:52:31 +08:00
|
|
|
AU.addRequired<AliasAnalysis>();
|
2008-01-07 09:30:38 +08:00
|
|
|
AU.addRequired<CollectorModuleMetadata>();
|
2007-03-31 12:18:03 +08:00
|
|
|
AU.setPreservesAll();
|
2005-08-17 14:37:43 +08:00
|
|
|
}
|
2005-01-07 15:47:53 +08:00
|
|
|
|
|
|
|
bool SelectionDAGISel::runOnFunction(Function &Fn) {
|
2007-08-28 00:26:13 +08:00
|
|
|
// Get alias analysis for load/store combining.
|
|
|
|
AA = &getAnalysis<AliasAnalysis>();
|
|
|
|
|
2005-01-07 15:47:53 +08:00
|
|
|
MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
|
2008-01-07 09:30:38 +08:00
|
|
|
if (MF.getFunction()->hasCollector())
|
|
|
|
GCI = &getAnalysis<CollectorModuleMetadata>().get(*MF.getFunction());
|
|
|
|
else
|
|
|
|
GCI = 0;
|
2007-12-31 12:13:23 +08:00
|
|
|
RegInfo = &MF.getRegInfo();
|
2006-12-08 04:04:42 +08:00
|
|
|
DOUT << "\n\n\n=== " << Fn.getName() << "\n";
|
2005-01-07 15:47:53 +08:00
|
|
|
|
|
|
|
FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
|
|
|
|
|
2008-04-02 08:25:04 +08:00
|
|
|
for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
|
|
|
|
if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
|
|
|
|
// Mark landing pad.
|
|
|
|
FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
|
2007-06-06 18:05:18 +08:00
|
|
|
|
2005-01-07 15:47:53 +08:00
|
|
|
for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
|
|
|
|
SelectBasicBlock(I, MF, FuncInfo);
|
2005-04-22 06:36:52 +08:00
|
|
|
|
2007-02-10 10:43:39 +08:00
|
|
|
// Add function live-ins to entry block live-in set.
|
|
|
|
BasicBlock *EntryBB = &Fn.getEntryBlock();
|
|
|
|
BB = FuncInfo.MBBMap[EntryBB];
|
2007-12-31 12:13:23 +08:00
|
|
|
if (!RegInfo->livein_empty())
|
|
|
|
for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
|
|
|
|
E = RegInfo->livein_end(); I != E; ++I)
|
2007-02-10 10:43:39 +08:00
|
|
|
BB->addLiveIn(I->first);
|
|
|
|
|
2007-06-16 03:04:19 +08:00
|
|
|
#ifndef NDEBUG
|
|
|
|
assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() &&
|
|
|
|
"Not all catch info was assigned to a landing pad!");
|
|
|
|
#endif
|
|
|
|
|
2005-01-07 15:47:53 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2008-04-28 15:16:35 +08:00
|
|
|
void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
|
Turn conditions like x<Y|z==q into multiple blocks.
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
llvm-svn: 31230
2006-10-28 05:36:01 +08:00
|
|
|
SDOperand Op = getValue(V);
|
2005-01-14 04:50:02 +08:00
|
|
|
assert((Op.getOpcode() != ISD::CopyFromReg ||
|
2005-08-17 05:55:35 +08:00
|
|
|
cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
|
2005-01-14 04:50:02 +08:00
|
|
|
"Copy from a reg to the same reg!");
|
2008-03-28 03:56:19 +08:00
|
|
|
assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
|
2007-06-29 07:29:44 +08:00
|
|
|
|
2008-04-26 02:27:55 +08:00
|
|
|
RegsForValue RFV(TLI, Reg, V->getType());
|
|
|
|
SDOperand Chain = DAG.getEntryNode();
|
|
|
|
RFV.getCopyToRegs(Op, DAG, Chain, 0);
|
|
|
|
PendingExports.push_back(Chain);
|
2005-01-07 15:47:53 +08:00
|
|
|
}
|
|
|
|
|
2005-01-18 01:15:02 +08:00
|
|
|
void SelectionDAGISel::
|
2008-03-28 03:56:19 +08:00
|
|
|
LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL) {
|
2005-01-07 15:47:53 +08:00
|
|
|
// If this is the entry block, emit arguments.
|
2007-02-10 09:08:18 +08:00
|
|
|
Function &F = *LLVMBB->getParent();
|
Implement a target independent optimization to codegen arguments only into
the basic block that uses them if possible. This is a big win on X86, as it
lets us fold the argument loads into instructions and reduce register pressure
(by not loading all of the arguments in the entry block).
For this (contrived to show the optimization) testcase:
int %argtest(int %A, int %B) {
%X = sub int 12345, %A
br label %L
L:
%Y = add int %X, %B
ret int %Y
}
we used to produce:
argtest:
mov %ECX, DWORD PTR [%ESP + 4]
mov %EAX, 12345
sub %EAX, %ECX
mov %EDX, DWORD PTR [%ESP + 8]
.LBBargtest_1: # L
add %EAX, %EDX
ret
now we produce:
argtest:
mov %EAX, 12345
sub %EAX, DWORD PTR [%ESP + 4]
.LBBargtest_1: # L
add %EAX, DWORD PTR [%ESP + 8]
ret
This also fixes the FIXME in the code.
BTW, this occurs in real code. 164.gzip shrinks from 8623 to 8608 lines of
.s file. The stack frame in huft_build shrinks from 1644->1628 bytes,
inflate_codes shrinks from 116->108 bytes, and inflate_block from 2620->2612,
due to fewer spills.
Take that alkis. :-)
llvm-svn: 19639
2005-01-18 01:55:19 +08:00
|
|
|
FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
|
Significantly simplify this code and make it more aggressive. Instead of having
a special case hack for X86, make the hack more general: if an incoming argument
register is not used in any block other than the entry block, don't copy it to
a vreg. This helps us compile code like this:
%struct.foo = type { int, int, [0 x ubyte] }
int %test(%struct.foo* %X) {
%tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
%tmp = load ubyte* %tmp1 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
lbz r3, 108(r3)
blr
instead of:
_test:
lbz r2, 108(r3)
or r3, r2, r2
blr
The (dead) copy emitted to copy r3 into a vreg for extra-block uses was
increasing the live range of r3 past the load, preventing the coallescing.
This implements CodeGen/PowerPC/reg-coallesce-simple.ll
llvm-svn: 24115
2005-10-31 03:42:35 +08:00
|
|
|
SDOperand OldRoot = SDL.DAG.getRoot();
|
|
|
|
std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
|
|
|
|
|
|
|
|
unsigned a = 0;
|
|
|
|
for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
|
|
|
|
AI != E; ++AI, ++a)
|
|
|
|
if (!AI->use_empty()) {
|
|
|
|
SDL.setValue(AI, Args[a]);
|
2006-04-27 16:29:42 +08:00
|
|
|
|
Significantly simplify this code and make it more aggressive. Instead of having
a special case hack for X86, make the hack more general: if an incoming argument
register is not used in any block other than the entry block, don't copy it to
a vreg. This helps us compile code like this:
%struct.foo = type { int, int, [0 x ubyte] }
int %test(%struct.foo* %X) {
%tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
%tmp = load ubyte* %tmp1 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
lbz r3, 108(r3)
blr
instead of:
_test:
lbz r2, 108(r3)
or r3, r2, r2
blr
The (dead) copy emitted to copy r3 into a vreg for extra-block uses was
increasing the live range of r3 past the load, preventing the coallescing.
This implements CodeGen/PowerPC/reg-coallesce-simple.ll
llvm-svn: 24115
2005-10-31 03:42:35 +08:00
|
|
|
// If this argument is live outside of the entry block, insert a copy from
|
|
|
|
// whereever we got it to the vreg that other BB's will reference it as.
|
2007-02-26 02:40:32 +08:00
|
|
|
DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI);
|
|
|
|
if (VMI != FuncInfo.ValueMap.end()) {
|
2008-03-28 03:56:19 +08:00
|
|
|
SDL.CopyValueToVirtualRegister(AI, VMI->second);
|
Significantly simplify this code and make it more aggressive. Instead of having
a special case hack for X86, make the hack more general: if an incoming argument
register is not used in any block other than the entry block, don't copy it to
a vreg. This helps us compile code like this:
%struct.foo = type { int, int, [0 x ubyte] }
int %test(%struct.foo* %X) {
%tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
%tmp = load ubyte* %tmp1 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
lbz r3, 108(r3)
blr
instead of:
_test:
lbz r2, 108(r3)
or r3, r2, r2
blr
The (dead) copy emitted to copy r3 into a vreg for extra-block uses was
increasing the live range of r3 past the load, preventing the coallescing.
This implements CodeGen/PowerPC/reg-coallesce-simple.ll
llvm-svn: 24115
2005-10-31 03:42:35 +08:00
|
|
|
}
|
Implement a target independent optimization to codegen arguments only into
the basic block that uses them if possible. This is a big win on X86, as it
lets us fold the argument loads into instructions and reduce register pressure
(by not loading all of the arguments in the entry block).
For this (contrived to show the optimization) testcase:
int %argtest(int %A, int %B) {
%X = sub int 12345, %A
br label %L
L:
%Y = add int %X, %B
ret int %Y
}
we used to produce:
argtest:
mov %ECX, DWORD PTR [%ESP + 4]
mov %EAX, 12345
sub %EAX, %ECX
mov %EDX, DWORD PTR [%ESP + 8]
.LBBargtest_1: # L
add %EAX, %EDX
ret
now we produce:
argtest:
mov %EAX, 12345
sub %EAX, DWORD PTR [%ESP + 4]
.LBBargtest_1: # L
add %EAX, DWORD PTR [%ESP + 8]
ret
This also fixes the FIXME in the code.
BTW, this occurs in real code. 164.gzip shrinks from 8623 to 8608 lines of
.s file. The stack frame in huft_build shrinks from 1644->1628 bytes,
inflate_codes shrinks from 116->108 bytes, and inflate_block from 2620->2612,
due to fewer spills.
Take that alkis. :-)
llvm-svn: 19639
2005-01-18 01:55:19 +08:00
|
|
|
}
|
Significantly simplify this code and make it more aggressive. Instead of having
a special case hack for X86, make the hack more general: if an incoming argument
register is not used in any block other than the entry block, don't copy it to
a vreg. This helps us compile code like this:
%struct.foo = type { int, int, [0 x ubyte] }
int %test(%struct.foo* %X) {
%tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
%tmp = load ubyte* %tmp1 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
lbz r3, 108(r3)
blr
instead of:
_test:
lbz r2, 108(r3)
or r3, r2, r2
blr
The (dead) copy emitted to copy r3 into a vreg for extra-block uses was
increasing the live range of r3 past the load, preventing the coallescing.
This implements CodeGen/PowerPC/reg-coallesce-simple.ll
llvm-svn: 24115
2005-10-31 03:42:35 +08:00
|
|
|
|
|
|
|
// Finally, if the target has anything special to do, allow it to do so.
|
2006-05-16 14:10:58 +08:00
|
|
|
// FIXME: this should insert code into the DAG!
|
Significantly simplify this code and make it more aggressive. Instead of having
a special case hack for X86, make the hack more general: if an incoming argument
register is not used in any block other than the entry block, don't copy it to
a vreg. This helps us compile code like this:
%struct.foo = type { int, int, [0 x ubyte] }
int %test(%struct.foo* %X) {
%tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
%tmp = load ubyte* %tmp1 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
lbz r3, 108(r3)
blr
instead of:
_test:
lbz r2, 108(r3)
or r3, r2, r2
blr
The (dead) copy emitted to copy r3 into a vreg for extra-block uses was
increasing the live range of r3 past the load, preventing the coallescing.
This implements CodeGen/PowerPC/reg-coallesce-simple.ll
llvm-svn: 24115
2005-10-31 03:42:35 +08:00
|
|
|
EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
|
2005-01-18 01:15:02 +08:00
|
|
|
}
|
|
|
|
|
2007-06-16 03:04:19 +08:00
|
|
|
static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
|
|
|
|
MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
|
|
|
|
for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
|
2007-07-05 04:52:51 +08:00
|
|
|
if (isSelector(I)) {
|
2007-06-16 03:04:19 +08:00
|
|
|
// Apply the catch info to DestBB.
|
|
|
|
addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]);
|
|
|
|
#ifndef NDEBUG
|
2007-11-15 17:54:37 +08:00
|
|
|
if (!FLI.MBBMap[SrcBB]->isLandingPad())
|
|
|
|
FLI.CatchInfoFound.insert(I);
|
2007-06-16 03:04:19 +08:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-04-30 17:16:33 +08:00
|
|
|
/// IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and
|
|
|
|
/// whether object offset >= 0.
|
|
|
|
static bool
|
|
|
|
IsFixedFrameObjectWithPosOffset(MachineFrameInfo * MFI, SDOperand Op) {
|
|
|
|
if (!isa<FrameIndexSDNode>(Op)) return false;
|
|
|
|
|
|
|
|
FrameIndexSDNode * FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op);
|
|
|
|
int FrameIdx = FrameIdxNode->getIndex();
|
|
|
|
return MFI->isFixedObjectIndex(FrameIdx) &&
|
|
|
|
MFI->getObjectOffset(FrameIdx) >= 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could
|
|
|
|
/// possibly be overwritten when lowering the outgoing arguments in a tail
|
|
|
|
/// call. Currently the implementation of this call is very conservative and
|
|
|
|
/// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with
|
|
|
|
/// virtual registers would be overwritten by direct lowering.
|
|
|
|
static bool IsPossiblyOverwrittenArgumentOfTailCall(SDOperand Op,
|
|
|
|
MachineFrameInfo * MFI) {
|
|
|
|
RegisterSDNode * OpReg = NULL;
|
|
|
|
if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS ||
|
|
|
|
(Op.getOpcode()== ISD::CopyFromReg &&
|
|
|
|
(OpReg = dyn_cast<RegisterSDNode>(Op.getOperand(1))) &&
|
|
|
|
(OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) ||
|
|
|
|
(Op.getOpcode() == ISD::LOAD &&
|
|
|
|
IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(1))) ||
|
|
|
|
(Op.getOpcode() == ISD::MERGE_VALUES &&
|
|
|
|
Op.getOperand(Op.ResNo).getOpcode() == ISD::LOAD &&
|
|
|
|
IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.ResNo).
|
|
|
|
getOperand(1))))
|
|
|
|
return true;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2007-10-12 03:40:01 +08:00
|
|
|
/// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
|
2007-10-13 05:30:57 +08:00
|
|
|
/// DAG and fixes their tailcall attribute operand.
|
2007-10-12 03:40:01 +08:00
|
|
|
static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
|
|
|
|
TargetLowering& TLI) {
|
|
|
|
SDNode * Ret = NULL;
|
|
|
|
SDOperand Terminator = DAG.getRoot();
|
|
|
|
|
|
|
|
// Find RET node.
|
|
|
|
if (Terminator.getOpcode() == ISD::RET) {
|
|
|
|
Ret = Terminator.Val;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Fix tail call attribute of CALL nodes.
|
|
|
|
for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
|
|
|
|
BI = prior(DAG.allnodes_end()); BI != BE; --BI) {
|
|
|
|
if (BI->getOpcode() == ISD::CALL) {
|
|
|
|
SDOperand OpRet(Ret, 0);
|
|
|
|
SDOperand OpCall(static_cast<SDNode*>(BI), 0);
|
|
|
|
bool isMarkedTailCall =
|
|
|
|
cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0;
|
|
|
|
// If CALL node has tail call attribute set to true and the call is not
|
|
|
|
// eligible (no RET or the target rejects) the attribute is fixed to
|
2007-10-13 05:30:57 +08:00
|
|
|
// false. The TargetLowering::IsEligibleForTailCallOptimization function
|
2007-10-12 03:40:01 +08:00
|
|
|
// must correctly identify tail call optimizable calls.
|
2008-04-30 17:16:33 +08:00
|
|
|
if (!isMarkedTailCall) continue;
|
|
|
|
if (Ret==NULL ||
|
|
|
|
!TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG)) {
|
|
|
|
// Not eligible. Mark CALL node as non tail call.
|
2007-10-12 03:40:01 +08:00
|
|
|
SmallVector<SDOperand, 32> Ops;
|
|
|
|
unsigned idx=0;
|
2008-04-30 17:16:33 +08:00
|
|
|
for(SDNode::op_iterator I =OpCall.Val->op_begin(),
|
|
|
|
E = OpCall.Val->op_end(); I != E; I++, idx++) {
|
2007-10-12 03:40:01 +08:00
|
|
|
if (idx!=3)
|
|
|
|
Ops.push_back(*I);
|
2008-04-30 17:16:33 +08:00
|
|
|
else
|
2007-10-12 03:40:01 +08:00
|
|
|
Ops.push_back(DAG.getConstant(false, TLI.getPointerTy()));
|
|
|
|
}
|
|
|
|
DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
|
2008-04-30 17:16:33 +08:00
|
|
|
} else {
|
|
|
|
// Look for tail call clobbered arguments. Emit a series of
|
|
|
|
// copyto/copyfrom virtual register nodes to protect them.
|
|
|
|
SmallVector<SDOperand, 32> Ops;
|
|
|
|
SDOperand Chain = OpCall.getOperand(0), InFlag;
|
|
|
|
unsigned idx=0;
|
|
|
|
for(SDNode::op_iterator I = OpCall.Val->op_begin(),
|
|
|
|
E = OpCall.Val->op_end(); I != E; I++, idx++) {
|
|
|
|
SDOperand Arg = *I;
|
|
|
|
if (idx > 4 && (idx % 2)) {
|
|
|
|
bool isByVal = cast<ARG_FLAGSSDNode>(OpCall.getOperand(idx+1))->
|
|
|
|
getArgFlags().isByVal();
|
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
|
|
if (!isByVal &&
|
|
|
|
IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) {
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT VT = Arg.getValueType();
|
2008-04-30 17:16:33 +08:00
|
|
|
unsigned VReg = MF.getRegInfo().
|
|
|
|
createVirtualRegister(TLI.getRegClassFor(VT));
|
|
|
|
Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag);
|
|
|
|
InFlag = Chain.getValue(1);
|
|
|
|
Arg = DAG.getCopyFromReg(Chain, VReg, VT, InFlag);
|
|
|
|
Chain = Arg.getValue(1);
|
|
|
|
InFlag = Arg.getValue(2);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
Ops.push_back(Arg);
|
|
|
|
}
|
|
|
|
// Link in chain of CopyTo/CopyFromReg.
|
|
|
|
Ops[0] = Chain;
|
|
|
|
DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
|
2007-10-12 03:40:01 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2005-01-18 01:15:02 +08:00
|
|
|
void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
|
|
|
|
std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
|
2006-03-27 09:32:24 +08:00
|
|
|
FunctionLoweringInfo &FuncInfo) {
|
2008-01-07 09:30:38 +08:00
|
|
|
SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo, GCI);
|
2005-01-18 01:15:02 +08:00
|
|
|
|
Significantly simplify this code and make it more aggressive. Instead of having
a special case hack for X86, make the hack more general: if an incoming argument
register is not used in any block other than the entry block, don't copy it to
a vreg. This helps us compile code like this:
%struct.foo = type { int, int, [0 x ubyte] }
int %test(%struct.foo* %X) {
%tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
%tmp = load ubyte* %tmp1 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
lbz r3, 108(r3)
blr
instead of:
_test:
lbz r2, 108(r3)
or r3, r2, r2
blr
The (dead) copy emitted to copy r3 into a vreg for extra-block uses was
increasing the live range of r3 past the load, preventing the coallescing.
This implements CodeGen/PowerPC/reg-coallesce-simple.ll
llvm-svn: 24115
2005-10-31 03:42:35 +08:00
|
|
|
// Lower any arguments needed in this block if this is the entry block.
|
2007-03-23 00:38:57 +08:00
|
|
|
if (LLVMBB == &LLVMBB->getParent()->getEntryBlock())
|
2008-03-28 03:56:19 +08:00
|
|
|
LowerArguments(LLVMBB, SDL);
|
2005-01-07 15:47:53 +08:00
|
|
|
|
|
|
|
BB = FuncInfo.MBBMap[LLVMBB];
|
|
|
|
SDL.setCurrentBasicBlock(BB);
|
|
|
|
|
2007-06-16 03:04:19 +08:00
|
|
|
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
|
2007-06-06 18:05:18 +08:00
|
|
|
|
2008-04-02 08:25:04 +08:00
|
|
|
if (MMI && BB->isLandingPad()) {
|
2007-06-16 03:04:19 +08:00
|
|
|
// Add a label to mark the beginning of the landing pad. Deletion of the
|
|
|
|
// landing pad can thus be detected via the MachineModuleInfo.
|
|
|
|
unsigned LabelID = MMI->addLandingPad(BB);
|
|
|
|
DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(),
|
2008-01-31 17:59:15 +08:00
|
|
|
DAG.getConstant(LabelID, MVT::i32),
|
|
|
|
DAG.getConstant(1, MVT::i32)));
|
2007-06-16 03:04:19 +08:00
|
|
|
|
2007-06-28 02:45:32 +08:00
|
|
|
// Mark exception register as live in.
|
|
|
|
unsigned Reg = TLI.getExceptionAddressRegister();
|
|
|
|
if (Reg) BB->addLiveIn(Reg);
|
|
|
|
|
|
|
|
// Mark exception selector register as live in.
|
|
|
|
Reg = TLI.getExceptionSelectorRegister();
|
|
|
|
if (Reg) BB->addLiveIn(Reg);
|
|
|
|
|
2007-06-16 03:04:19 +08:00
|
|
|
// FIXME: Hack around an exception handling flaw (PR1508): the personality
|
|
|
|
// function and list of typeids logically belong to the invoke (or, if you
|
|
|
|
// like, the basic block containing the invoke), and need to be associated
|
|
|
|
// with it in the dwarf exception handling tables. Currently however the
|
2007-07-05 04:52:51 +08:00
|
|
|
// information is provided by an intrinsic (eh.selector) that can be moved
|
|
|
|
// to unexpected places by the optimizers: if the unwind edge is critical,
|
|
|
|
// then breaking it can result in the intrinsics being in the successor of
|
|
|
|
// the landing pad, not the landing pad itself. This results in exceptions
|
|
|
|
// not being caught because no typeids are associated with the invoke.
|
|
|
|
// This may not be the only way things can go wrong, but it is the only way
|
|
|
|
// we try to work around for the moment.
|
2007-06-16 03:04:19 +08:00
|
|
|
BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
|
|
|
|
|
|
|
|
if (Br && Br->isUnconditional()) { // Critical edge?
|
|
|
|
BasicBlock::iterator I, E;
|
|
|
|
for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
|
2007-07-05 04:52:51 +08:00
|
|
|
if (isSelector(I))
|
2007-06-16 03:04:19 +08:00
|
|
|
break;
|
|
|
|
|
|
|
|
if (I == E)
|
|
|
|
// No catch info found - try to extract some from the successor.
|
|
|
|
copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo);
|
2007-06-06 18:05:18 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2005-01-07 15:47:53 +08:00
|
|
|
// Lower all of the non-terminator instructions.
|
|
|
|
for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
|
|
|
|
I != E; ++I)
|
|
|
|
SDL.visit(*I);
|
2007-06-13 13:51:31 +08:00
|
|
|
|
2005-01-07 15:47:53 +08:00
|
|
|
// Ensure that all instructions which are used outside of their defining
|
2007-06-13 13:51:31 +08:00
|
|
|
// blocks are available as virtual registers. Invoke is handled elsewhere.
|
2005-01-07 15:47:53 +08:00
|
|
|
for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
|
2007-06-13 13:51:31 +08:00
|
|
|
if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
|
2007-02-04 09:35:11 +08:00
|
|
|
DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
|
2005-01-07 15:47:53 +08:00
|
|
|
if (VMI != FuncInfo.ValueMap.end())
|
2008-03-28 03:56:19 +08:00
|
|
|
SDL.CopyValueToVirtualRegister(I, VMI->second);
|
2005-01-07 15:47:53 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
|
|
|
|
// ensure constants are generated when needed. Remember the virtual registers
|
|
|
|
// that need to be added to the Machine PHI nodes as input. We cannot just
|
|
|
|
// directly add them, because expansion might result in multiple MBB's for one
|
|
|
|
// BB. As such, the start of the BB might correspond to a different MBB than
|
|
|
|
// the end.
|
2005-04-22 06:36:52 +08:00
|
|
|
//
|
2006-10-28 07:50:33 +08:00
|
|
|
TerminatorInst *TI = LLVMBB->getTerminator();
|
2005-01-07 15:47:53 +08:00
|
|
|
|
|
|
|
// Emit constants only once even if used by multiple PHI nodes.
|
|
|
|
std::map<Constant*, unsigned> ConstantsOut;
|
2006-09-07 09:59:34 +08:00
|
|
|
|
2006-10-28 07:50:33 +08:00
|
|
|
// Vector bool would be better, but vector<bool> is really slow.
|
|
|
|
std::vector<unsigned char> SuccsHandled;
|
|
|
|
if (TI->getNumSuccessors())
|
|
|
|
SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
|
|
|
|
|
2007-07-10 04:59:04 +08:00
|
|
|
// Check successor nodes' PHI nodes that expect a constant to be available
|
|
|
|
// from this block.
|
2005-01-07 15:47:53 +08:00
|
|
|
for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
|
|
|
|
BasicBlock *SuccBB = TI->getSuccessor(succ);
|
2006-09-07 09:59:34 +08:00
|
|
|
if (!isa<PHINode>(SuccBB->begin())) continue;
|
2006-10-28 07:50:33 +08:00
|
|
|
MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
|
2006-09-07 09:59:34 +08:00
|
|
|
|
2006-10-28 07:50:33 +08:00
|
|
|
// If this terminator has multiple identical successors (common for
|
|
|
|
// switches), only handle each succ once.
|
|
|
|
unsigned SuccMBBNo = SuccMBB->getNumber();
|
|
|
|
if (SuccsHandled[SuccMBBNo]) continue;
|
|
|
|
SuccsHandled[SuccMBBNo] = true;
|
|
|
|
|
|
|
|
MachineBasicBlock::iterator MBBI = SuccMBB->begin();
|
2005-01-07 15:47:53 +08:00
|
|
|
PHINode *PN;
|
|
|
|
|
|
|
|
// At this point we know that there is a 1-1 correspondence between LLVM PHI
|
|
|
|
// nodes and Machine PHI nodes, but the incoming operands have not been
|
|
|
|
// emitted yet.
|
|
|
|
for (BasicBlock::iterator I = SuccBB->begin();
|
2006-10-28 07:50:33 +08:00
|
|
|
(PN = dyn_cast<PHINode>(I)); ++I) {
|
|
|
|
// Ignore dead phi's.
|
|
|
|
if (PN->use_empty()) continue;
|
|
|
|
|
|
|
|
unsigned Reg;
|
|
|
|
Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
|
2006-11-29 09:12:32 +08:00
|
|
|
|
2006-10-28 07:50:33 +08:00
|
|
|
if (Constant *C = dyn_cast<Constant>(PHIOp)) {
|
|
|
|
unsigned &RegOut = ConstantsOut[C];
|
|
|
|
if (RegOut == 0) {
|
|
|
|
RegOut = FuncInfo.CreateRegForValue(C);
|
2008-03-28 03:56:19 +08:00
|
|
|
SDL.CopyValueToVirtualRegister(C, RegOut);
|
2005-01-07 15:47:53 +08:00
|
|
|
}
|
2006-10-28 07:50:33 +08:00
|
|
|
Reg = RegOut;
|
|
|
|
} else {
|
|
|
|
Reg = FuncInfo.ValueMap[PHIOp];
|
|
|
|
if (Reg == 0) {
|
|
|
|
assert(isa<AllocaInst>(PHIOp) &&
|
|
|
|
FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
|
|
|
|
"Didn't codegen value into a register!??");
|
|
|
|
Reg = FuncInfo.CreateRegForValue(PHIOp);
|
2008-03-28 03:56:19 +08:00
|
|
|
SDL.CopyValueToVirtualRegister(PHIOp, Reg);
|
2006-03-31 10:12:18 +08:00
|
|
|
}
|
2005-01-07 15:47:53 +08:00
|
|
|
}
|
2006-10-28 07:50:33 +08:00
|
|
|
|
|
|
|
// Remember that this register needs to added to the machine PHI node as
|
|
|
|
// the input for this MBB.
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT VT = TLI.getValueType(PN->getType());
|
2007-06-26 00:23:39 +08:00
|
|
|
unsigned NumRegisters = TLI.getNumRegisters(VT);
|
2007-06-21 22:42:22 +08:00
|
|
|
for (unsigned i = 0, e = NumRegisters; i != e; ++i)
|
2006-10-28 07:50:33 +08:00
|
|
|
PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
|
|
|
|
}
|
2005-01-07 15:47:53 +08:00
|
|
|
}
|
|
|
|
ConstantsOut.clear();
|
|
|
|
|
|
|
|
// Lower the terminator after the copies are emitted.
|
2007-06-13 13:51:31 +08:00
|
|
|
SDL.visit(*LLVMBB->getTerminator());
|
2005-01-18 03:43:36 +08:00
|
|
|
|
2006-03-27 09:32:24 +08:00
|
|
|
// Copy over any CaseBlock records that may now exist due to SwitchInst
|
2006-04-23 02:53:45 +08:00
|
|
|
// lowering, as well as any jump table information.
|
2006-03-27 09:32:24 +08:00
|
|
|
SwitchCases.clear();
|
|
|
|
SwitchCases = SDL.SwitchCases;
|
2007-03-25 23:07:15 +08:00
|
|
|
JTCases.clear();
|
|
|
|
JTCases = SDL.JTCases;
|
2007-04-09 20:31:58 +08:00
|
|
|
BitTestCases.clear();
|
|
|
|
BitTestCases = SDL.BitTestCases;
|
|
|
|
|
2005-01-18 03:43:36 +08:00
|
|
|
// Make sure the root of the DAG is up-to-date.
|
2008-03-28 03:56:19 +08:00
|
|
|
DAG.setRoot(SDL.getControlRoot());
|
2007-10-12 03:40:01 +08:00
|
|
|
|
|
|
|
// Check whether calls in this block are real tail calls. Fix up CALL nodes
|
|
|
|
// with correct tailcall attribute so that the target can rely on the tailcall
|
|
|
|
// attribute indicating whether the call is really eligible for tail call
|
|
|
|
// optimization.
|
|
|
|
CheckDAGForTailCallsAndFixThem(DAG, TLI);
|
2005-01-07 15:47:53 +08:00
|
|
|
}
|
|
|
|
|
2006-03-27 09:32:24 +08:00
|
|
|
void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
|
2007-10-08 23:12:17 +08:00
|
|
|
DOUT << "Lowered selection DAG:\n";
|
|
|
|
DEBUG(DAG.dump());
|
|
|
|
|
2005-10-11 00:47:10 +08:00
|
|
|
// Run the DAG combiner in pre-legalize mode.
|
2007-08-28 00:26:13 +08:00
|
|
|
DAG.Combine(false, *AA);
|
2005-09-07 08:15:36 +08:00
|
|
|
|
2007-10-08 23:12:17 +08:00
|
|
|
DOUT << "Optimized lowered selection DAG:\n";
|
2005-01-07 15:47:53 +08:00
|
|
|
DEBUG(DAG.dump());
|
2006-03-27 09:32:24 +08:00
|
|
|
|
2005-01-07 15:47:53 +08:00
|
|
|
// Second step, hack on the DAG until it only uses operations and types that
|
|
|
|
// the target supports.
|
One mundane change: Change ReplaceAllUsesOfValueWith to *optionally*
take a deleted nodes vector, instead of requiring it.
One more significant change: Implement the start of a legalizer that
just works on types. This legalizer is designed to run before the
operation legalizer and ensure just that the input dag is transformed
into an output dag whose operand and result types are all legal, even
if the operations on those types are not.
This design/impl has the following advantages:
1. When finished, this will *significantly* reduce the amount of code in
LegalizeDAG.cpp. It will remove all the code related to promotion and
expansion as well as splitting and scalarizing vectors.
2. The new code is very simple, idiomatic, and modular: unlike
LegalizeDAG.cpp, it has no 3000 line long functions. :)
3. The implementation is completely iterative instead of recursive, good
for hacking on large dags without blowing out your stack.
4. The implementation updates nodes in place when possible instead of
deallocating and reallocating the entire graph that points to some
mutated node.
5. The code nicely separates out handling of operations with invalid
results from operations with invalid operands, making some cases
simpler and easier to understand.
6. The new -debug-only=legalize-types option is very very handy :),
allowing you to easily understand what legalize types is doing.
This is not yet done. Until the ifdef added to SelectionDAGISel.cpp is
enabled, this does nothing. However, this code is sufficient to legalize
all of the code in 186.crafty, olden and freebench on an x86 machine. The
biggest issues are:
1. Vectors aren't implemented at all yet
2. SoftFP is a mess, I need to talk to Evan about it.
3. No lowering to libcalls is implemented yet.
4. Various operations are missing etc.
5. There are FIXME's for stuff I hax0r'd out, like softfp.
Hey, at least it is a step in the right direction :). If you'd like to help,
just enable the #ifdef in SelectionDAGISel.cpp and compile code with it. If
this explodes it will tell you what needs to be implemented. Help is
certainly appreciated.
Once this goes in, we can do three things:
1. Add a new pass of dag combine between the "type legalizer" and "operation
legalizer" passes. This will let us catch some long-standing isel issues
that we miss because operation legalization often obfuscates the dag with
target-specific nodes.
2. We can rip out all of the type legalization code from LegalizeDAG.cpp,
making it much smaller and simpler. When that happens we can then
reimplement the core functionality left in it in a much more efficient and
non-recursive way.
3. Once the whole legalizer is non-recursive, we can implement whole-function
selectiondags maybe...
llvm-svn: 42981
2007-10-15 14:10:22 +08:00
|
|
|
#if 0 // Enable this some day.
|
|
|
|
DAG.LegalizeTypes();
|
|
|
|
// Someday even later, enable a dag combine pass here.
|
|
|
|
#endif
|
2005-01-23 12:36:26 +08:00
|
|
|
DAG.Legalize();
|
2006-03-27 09:32:24 +08:00
|
|
|
|
2006-12-08 04:04:42 +08:00
|
|
|
DOUT << "Legalized selection DAG:\n";
|
2005-01-07 15:47:53 +08:00
|
|
|
DEBUG(DAG.dump());
|
2006-03-27 09:32:24 +08:00
|
|
|
|
2005-10-11 00:47:10 +08:00
|
|
|
// Run the DAG combiner in post-legalize mode.
|
2007-08-28 00:26:13 +08:00
|
|
|
DAG.Combine(true, *AA);
|
2005-09-07 08:15:36 +08:00
|
|
|
|
2007-10-08 23:12:17 +08:00
|
|
|
DOUT << "Optimized legalized selection DAG:\n";
|
|
|
|
DEBUG(DAG.dump());
|
|
|
|
|
2006-01-21 10:32:06 +08:00
|
|
|
if (ViewISelDAGs) DAG.viewGraph();
|
2006-04-28 10:09:19 +08:00
|
|
|
|
2005-03-30 09:10:47 +08:00
|
|
|
// Third, instruction select all of the operations to machine code, adding the
|
|
|
|
// code to the MachineBasicBlock.
|
2005-01-07 15:47:53 +08:00
|
|
|
InstructionSelectBasicBlock(DAG);
|
2006-03-27 09:32:24 +08:00
|
|
|
|
2006-12-08 04:04:42 +08:00
|
|
|
DOUT << "Selected machine code:\n";
|
2005-01-07 15:47:53 +08:00
|
|
|
DEBUG(BB->dump());
|
2006-03-27 09:32:24 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
|
|
|
|
FunctionLoweringInfo &FuncInfo) {
|
|
|
|
std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
|
|
|
|
{
|
2007-01-27 05:22:28 +08:00
|
|
|
SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
|
2006-03-27 09:32:24 +08:00
|
|
|
CurDAG = &DAG;
|
|
|
|
|
|
|
|
// First step, lower LLVM code to some DAG. This DAG may use operations and
|
|
|
|
// types that are not supported by the target.
|
|
|
|
BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
|
2005-01-07 15:47:53 +08:00
|
|
|
|
2006-03-27 09:32:24 +08:00
|
|
|
// Second step, emit the lowered DAG as machine code.
|
|
|
|
CodeGenAndEmitDAG(DAG);
|
|
|
|
}
|
2007-04-09 20:31:58 +08:00
|
|
|
|
|
|
|
DOUT << "Total amount of phi nodes to update: "
|
|
|
|
<< PHINodesToUpdate.size() << "\n";
|
|
|
|
DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i)
|
|
|
|
DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first
|
|
|
|
<< ", " << PHINodesToUpdate[i].second << ")\n";);
|
2006-03-27 09:32:24 +08:00
|
|
|
|
2005-03-30 09:10:47 +08:00
|
|
|
// Next, now that we know what the last MBB the LLVM BB expanded is, update
|
2005-01-07 15:47:53 +08:00
|
|
|
// PHI nodes in successors.
|
2007-04-09 20:31:58 +08:00
|
|
|
if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) {
|
2006-03-27 09:32:24 +08:00
|
|
|
for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
|
|
|
|
MachineInstr *PHI = PHINodesToUpdate[i].first;
|
|
|
|
assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
|
|
|
|
"This is not a machine PHI node that we are updating!");
|
2007-12-30 08:57:42 +08:00
|
|
|
PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
|
|
|
|
false));
|
|
|
|
PHI->addOperand(MachineOperand::CreateMBB(BB));
|
2006-03-27 09:32:24 +08:00
|
|
|
}
|
|
|
|
return;
|
2005-01-07 15:47:53 +08:00
|
|
|
}
|
2007-04-09 20:31:58 +08:00
|
|
|
|
|
|
|
for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) {
|
|
|
|
// Lower header first, if it wasn't already lowered
|
|
|
|
if (!BitTestCases[i].Emitted) {
|
|
|
|
SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
|
|
|
|
CurDAG = &HSDAG;
|
2008-01-07 09:30:38 +08:00
|
|
|
SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
|
2007-04-09 20:31:58 +08:00
|
|
|
// Set the current basic block to the mbb we wish to insert the code into
|
|
|
|
BB = BitTestCases[i].Parent;
|
|
|
|
HSDL.setCurrentBasicBlock(BB);
|
|
|
|
// Emit the code
|
|
|
|
HSDL.visitBitTestHeader(BitTestCases[i]);
|
|
|
|
HSDAG.setRoot(HSDL.getRoot());
|
|
|
|
CodeGenAndEmitDAG(HSDAG);
|
|
|
|
}
|
|
|
|
|
|
|
|
for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
|
|
|
|
SelectionDAG BSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
|
|
|
|
CurDAG = &BSDAG;
|
2008-01-07 09:30:38 +08:00
|
|
|
SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo, GCI);
|
2007-04-09 20:31:58 +08:00
|
|
|
// Set the current basic block to the mbb we wish to insert the code into
|
|
|
|
BB = BitTestCases[i].Cases[j].ThisBB;
|
|
|
|
BSDL.setCurrentBasicBlock(BB);
|
|
|
|
// Emit the code
|
|
|
|
if (j+1 != ej)
|
|
|
|
BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB,
|
|
|
|
BitTestCases[i].Reg,
|
|
|
|
BitTestCases[i].Cases[j]);
|
|
|
|
else
|
|
|
|
BSDL.visitBitTestCase(BitTestCases[i].Default,
|
|
|
|
BitTestCases[i].Reg,
|
|
|
|
BitTestCases[i].Cases[j]);
|
|
|
|
|
|
|
|
|
|
|
|
BSDAG.setRoot(BSDL.getRoot());
|
|
|
|
CodeGenAndEmitDAG(BSDAG);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Update PHI Nodes
|
|
|
|
for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
|
|
|
|
MachineInstr *PHI = PHINodesToUpdate[pi].first;
|
|
|
|
MachineBasicBlock *PHIBB = PHI->getParent();
|
|
|
|
assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
|
|
|
|
"This is not a machine PHI node that we are updating!");
|
|
|
|
// This is "default" BB. We have two jumps to it. From "header" BB and
|
|
|
|
// from last "case" BB.
|
|
|
|
if (PHIBB == BitTestCases[i].Default) {
|
2007-12-30 08:57:42 +08:00
|
|
|
PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
|
|
|
|
false));
|
|
|
|
PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Parent));
|
|
|
|
PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
|
|
|
|
false));
|
|
|
|
PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Cases.
|
|
|
|
back().ThisBB));
|
2007-04-09 20:31:58 +08:00
|
|
|
}
|
|
|
|
// One of "cases" BB.
|
|
|
|
for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
|
|
|
|
MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB;
|
|
|
|
if (cBB->succ_end() !=
|
|
|
|
std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
|
2007-12-30 08:57:42 +08:00
|
|
|
PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
|
|
|
|
false));
|
|
|
|
PHI->addOperand(MachineOperand::CreateMBB(cBB));
|
2007-04-09 20:31:58 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-04-23 14:26:20 +08:00
|
|
|
// If the JumpTable record is filled in, then we need to emit a jump table.
|
|
|
|
// Updating the PHI nodes is tricky in this case, since we need to determine
|
|
|
|
// whether the PHI is a successor of the range check MBB or the jump table MBB
|
2007-03-25 23:07:15 +08:00
|
|
|
for (unsigned i = 0, e = JTCases.size(); i != e; ++i) {
|
|
|
|
// Lower header first, if it wasn't already lowered
|
|
|
|
if (!JTCases[i].first.Emitted) {
|
|
|
|
SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
|
|
|
|
CurDAG = &HSDAG;
|
2008-01-07 09:30:38 +08:00
|
|
|
SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
|
2007-03-25 23:07:15 +08:00
|
|
|
// Set the current basic block to the mbb we wish to insert the code into
|
|
|
|
BB = JTCases[i].first.HeaderBB;
|
|
|
|
HSDL.setCurrentBasicBlock(BB);
|
|
|
|
// Emit the code
|
|
|
|
HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first);
|
|
|
|
HSDAG.setRoot(HSDL.getRoot());
|
|
|
|
CodeGenAndEmitDAG(HSDAG);
|
2007-04-09 20:31:58 +08:00
|
|
|
}
|
2007-03-25 23:07:15 +08:00
|
|
|
|
|
|
|
SelectionDAG JSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
|
|
|
|
CurDAG = &JSDAG;
|
2008-01-07 09:30:38 +08:00
|
|
|
SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo, GCI);
|
2006-04-23 02:53:45 +08:00
|
|
|
// Set the current basic block to the mbb we wish to insert the code into
|
2007-03-25 23:07:15 +08:00
|
|
|
BB = JTCases[i].second.MBB;
|
|
|
|
JSDL.setCurrentBasicBlock(BB);
|
2006-04-23 02:53:45 +08:00
|
|
|
// Emit the code
|
2007-03-25 23:07:15 +08:00
|
|
|
JSDL.visitJumpTable(JTCases[i].second);
|
|
|
|
JSDAG.setRoot(JSDL.getRoot());
|
|
|
|
CodeGenAndEmitDAG(JSDAG);
|
|
|
|
|
2006-04-23 02:53:45 +08:00
|
|
|
// Update PHI Nodes
|
|
|
|
for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
|
|
|
|
MachineInstr *PHI = PHINodesToUpdate[pi].first;
|
|
|
|
MachineBasicBlock *PHIBB = PHI->getParent();
|
|
|
|
assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
|
|
|
|
"This is not a machine PHI node that we are updating!");
|
2007-04-09 20:31:58 +08:00
|
|
|
// "default" BB. We can go there only from header BB.
|
2007-03-25 23:07:15 +08:00
|
|
|
if (PHIBB == JTCases[i].second.Default) {
|
2007-12-30 08:57:42 +08:00
|
|
|
PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
|
|
|
|
false));
|
|
|
|
PHI->addOperand(MachineOperand::CreateMBB(JTCases[i].first.HeaderBB));
|
2006-05-03 11:48:02 +08:00
|
|
|
}
|
2007-04-09 20:31:58 +08:00
|
|
|
// JT BB. Just iterate over successors here
|
2006-05-03 11:48:02 +08:00
|
|
|
if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
|
2007-12-30 08:57:42 +08:00
|
|
|
PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
|
|
|
|
false));
|
|
|
|
PHI->addOperand(MachineOperand::CreateMBB(BB));
|
2006-04-23 02:53:45 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-10-23 07:00:53 +08:00
|
|
|
// If the switch block involved a branch to one of the actual successors, we
|
|
|
|
// need to update PHI nodes in that block.
|
|
|
|
for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
|
|
|
|
MachineInstr *PHI = PHINodesToUpdate[i].first;
|
|
|
|
assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
|
|
|
|
"This is not a machine PHI node that we are updating!");
|
|
|
|
if (BB->isSuccessor(PHI->getParent())) {
|
2007-12-30 08:57:42 +08:00
|
|
|
PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
|
|
|
|
false));
|
|
|
|
PHI->addOperand(MachineOperand::CreateMBB(BB));
|
2006-10-23 07:00:53 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-03-27 09:32:24 +08:00
|
|
|
// If we generated any switch lowering information, build and codegen any
|
|
|
|
// additional DAGs necessary.
|
2006-09-07 09:59:34 +08:00
|
|
|
for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
|
2007-01-27 05:22:28 +08:00
|
|
|
SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
|
2006-03-27 09:32:24 +08:00
|
|
|
CurDAG = &SDAG;
|
2008-01-07 09:30:38 +08:00
|
|
|
SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo, GCI);
|
2006-09-07 09:59:34 +08:00
|
|
|
|
2006-03-27 09:32:24 +08:00
|
|
|
// Set the current basic block to the mbb we wish to insert the code into
|
|
|
|
BB = SwitchCases[i].ThisBB;
|
|
|
|
SDL.setCurrentBasicBlock(BB);
|
2006-09-07 09:59:34 +08:00
|
|
|
|
2006-03-27 09:32:24 +08:00
|
|
|
// Emit the code
|
|
|
|
SDL.visitSwitchCase(SwitchCases[i]);
|
|
|
|
SDAG.setRoot(SDL.getRoot());
|
|
|
|
CodeGenAndEmitDAG(SDAG);
|
2006-09-07 09:59:34 +08:00
|
|
|
|
|
|
|
// Handle any PHI nodes in successors of this chunk, as if we were coming
|
|
|
|
// from the original BB before switch expansion. Note that PHI nodes can
|
|
|
|
// occur multiple times in PHINodesToUpdate. We have to be very careful to
|
|
|
|
// handle them the right number of times.
|
2006-10-25 01:57:59 +08:00
|
|
|
while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
|
2006-09-07 09:59:34 +08:00
|
|
|
for (MachineBasicBlock::iterator Phi = BB->begin();
|
|
|
|
Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
|
|
|
|
// This value for this PHI node is recorded in PHINodesToUpdate, get it.
|
|
|
|
for (unsigned pn = 0; ; ++pn) {
|
|
|
|
assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
|
|
|
|
if (PHINodesToUpdate[pn].first == Phi) {
|
2007-12-30 08:57:42 +08:00
|
|
|
Phi->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pn].
|
|
|
|
second, false));
|
|
|
|
Phi->addOperand(MachineOperand::CreateMBB(SwitchCases[i].ThisBB));
|
2006-09-07 09:59:34 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2006-03-27 09:32:24 +08:00
|
|
|
}
|
2006-09-07 09:59:34 +08:00
|
|
|
|
|
|
|
// Don't process RHS if same block as LHS.
|
2006-10-25 01:57:59 +08:00
|
|
|
if (BB == SwitchCases[i].FalseBB)
|
|
|
|
SwitchCases[i].FalseBB = 0;
|
2006-09-07 09:59:34 +08:00
|
|
|
|
|
|
|
// If we haven't handled the RHS, do so now. Otherwise, we're done.
|
2006-10-25 02:07:37 +08:00
|
|
|
SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
|
2006-10-25 01:57:59 +08:00
|
|
|
SwitchCases[i].FalseBB = 0;
|
2006-03-27 09:32:24 +08:00
|
|
|
}
|
2006-10-25 01:57:59 +08:00
|
|
|
assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
|
2005-03-30 09:10:47 +08:00
|
|
|
}
|
2005-01-07 15:47:53 +08:00
|
|
|
}
|
2006-01-21 10:32:06 +08:00
|
|
|
|
2006-08-01 22:21:23 +08:00
|
|
|
|
2006-01-21 10:32:06 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
|
|
|
|
/// target node in the graph.
|
|
|
|
void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
|
|
|
|
if (ViewSchedDAGs) DAG.viewGraph();
|
2006-08-01 22:21:23 +08:00
|
|
|
|
2006-08-02 20:30:23 +08:00
|
|
|
RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
|
2006-08-01 22:21:23 +08:00
|
|
|
|
|
|
|
if (!Ctor) {
|
2006-08-02 20:30:23 +08:00
|
|
|
Ctor = ISHeuristic;
|
2006-08-02 03:14:14 +08:00
|
|
|
RegisterScheduler::setDefault(Ctor);
|
2006-01-23 15:01:07 +08:00
|
|
|
}
|
2006-08-01 22:21:23 +08:00
|
|
|
|
2006-08-02 02:29:48 +08:00
|
|
|
ScheduleDAG *SL = Ctor(this, &DAG, BB);
|
2006-01-22 03:12:11 +08:00
|
|
|
BB = SL->Run();
|
2007-08-29 04:32:58 +08:00
|
|
|
|
|
|
|
if (ViewSUnitDAGs) SL->viewGraph();
|
|
|
|
|
2006-02-04 14:49:00 +08:00
|
|
|
delete SL;
|
2006-01-21 10:32:06 +08:00
|
|
|
}
|
2006-02-24 10:13:54 +08:00
|
|
|
|
2006-03-06 08:22:00 +08:00
|
|
|
|
2006-08-02 02:29:48 +08:00
|
|
|
HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
|
|
|
|
return new HazardRecognizer();
|
|
|
|
}
|
|
|
|
|
2006-10-11 11:58:02 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Helper functions used by the generated instruction selector.
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Calls to these methods are generated by tblgen.
|
|
|
|
|
|
|
|
/// CheckAndMask - The isel is trying to match something like (and X, 255). If
|
|
|
|
/// the dag combiner simplified the 255, we still want to match. RHS is the
|
|
|
|
/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
|
|
|
|
/// specified in the .td file (e.g. 255).
|
|
|
|
bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
|
2007-07-25 07:00:27 +08:00
|
|
|
int64_t DesiredMaskS) const {
|
2008-02-26 05:11:39 +08:00
|
|
|
const APInt &ActualMask = RHS->getAPIntValue();
|
|
|
|
const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
|
2006-10-11 11:58:02 +08:00
|
|
|
|
|
|
|
// If the actual mask exactly matches, success!
|
|
|
|
if (ActualMask == DesiredMask)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
// If the actual AND mask is allowing unallowed bits, this doesn't match.
|
2008-02-26 05:11:39 +08:00
|
|
|
if (ActualMask.intersects(~DesiredMask))
|
2006-10-11 11:58:02 +08:00
|
|
|
return false;
|
|
|
|
|
|
|
|
// Otherwise, the DAG Combiner may have proven that the value coming in is
|
|
|
|
// either already zero or is not demanded. Check for known zero input bits.
|
2008-02-26 05:11:39 +08:00
|
|
|
APInt NeededMask = DesiredMask & ~ActualMask;
|
2007-06-22 22:59:07 +08:00
|
|
|
if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
|
2006-10-11 11:58:02 +08:00
|
|
|
return true;
|
|
|
|
|
|
|
|
// TODO: check to see if missing bits are just not demanded.
|
|
|
|
|
|
|
|
// Otherwise, this pattern doesn't match.
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// CheckOrMask - The isel is trying to match something like (or X, 255). If
|
|
|
|
/// the dag combiner simplified the 255, we still want to match. RHS is the
|
|
|
|
/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
|
|
|
|
/// specified in the .td file (e.g. 255).
|
|
|
|
bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
|
2008-02-26 05:11:39 +08:00
|
|
|
int64_t DesiredMaskS) const {
|
|
|
|
const APInt &ActualMask = RHS->getAPIntValue();
|
|
|
|
const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
|
2006-10-11 11:58:02 +08:00
|
|
|
|
|
|
|
// If the actual mask exactly matches, success!
|
|
|
|
if (ActualMask == DesiredMask)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
// If the actual AND mask is allowing unallowed bits, this doesn't match.
|
2008-02-26 05:11:39 +08:00
|
|
|
if (ActualMask.intersects(~DesiredMask))
|
2006-10-11 11:58:02 +08:00
|
|
|
return false;
|
|
|
|
|
|
|
|
// Otherwise, the DAG Combiner may have proven that the value coming in is
|
|
|
|
// either already zero or is not demanded. Check for known zero input bits.
|
2008-02-26 05:11:39 +08:00
|
|
|
APInt NeededMask = DesiredMask & ~ActualMask;
|
2006-10-11 11:58:02 +08:00
|
|
|
|
2008-02-26 05:11:39 +08:00
|
|
|
APInt KnownZero, KnownOne;
|
2007-06-22 22:59:07 +08:00
|
|
|
CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
|
2006-10-11 11:58:02 +08:00
|
|
|
|
|
|
|
// If all the missing bits in the or are already known to be set, match!
|
|
|
|
if ((NeededMask & KnownOne) == NeededMask)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
// TODO: check to see if missing bits are just not demanded.
|
|
|
|
|
|
|
|
// Otherwise, this pattern doesn't match.
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2006-08-02 02:29:48 +08:00
|
|
|
|
2006-02-24 10:13:54 +08:00
|
|
|
/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
|
|
|
|
/// by tblgen. Others should not call it.
|
|
|
|
void SelectionDAGISel::
|
|
|
|
SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
|
|
|
|
std::vector<SDOperand> InOps;
|
|
|
|
std::swap(InOps, Ops);
|
|
|
|
|
|
|
|
Ops.push_back(InOps[0]); // input chain.
|
|
|
|
Ops.push_back(InOps[1]); // input asm string.
|
|
|
|
|
|
|
|
unsigned i = 2, e = InOps.size();
|
|
|
|
if (InOps[e-1].getValueType() == MVT::Flag)
|
|
|
|
--e; // Don't process a flag operand if it is here.
|
|
|
|
|
|
|
|
while (i != e) {
|
|
|
|
unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
|
|
|
|
if ((Flags & 7) != 4 /*MEM*/) {
|
|
|
|
// Just skip over this operand, copying the operands verbatim.
|
|
|
|
Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
|
|
|
|
i += (Flags >> 3) + 1;
|
|
|
|
} else {
|
|
|
|
assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
|
|
|
|
// Otherwise, this is a memory operand. Ask the target to select it.
|
|
|
|
std::vector<SDOperand> SelOps;
|
|
|
|
if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
|
2006-12-08 04:04:42 +08:00
|
|
|
cerr << "Could not match memory address. Inline asm failure!\n";
|
2006-02-24 10:13:54 +08:00
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Add this to the output node.
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
|
2006-12-17 05:14:48 +08:00
|
|
|
Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
|
2007-04-09 08:33:58 +08:00
|
|
|
IntPtrTy));
|
2006-02-24 10:13:54 +08:00
|
|
|
Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
|
|
|
|
i += 2;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Add the flag input back if present.
|
|
|
|
if (e != InOps.size())
|
|
|
|
Ops.push_back(InOps.back());
|
|
|
|
}
|
2007-05-02 05:15:47 +08:00
|
|
|
|
2007-05-03 09:11:54 +08:00
|
|
|
char SelectionDAGISel::ID = 0;
|