maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/MC/Disassembler/Mips/mips32r3/valid-fp64.txt

Ignoring revisions in .git-blame-ignore-revs. Click here to bypass and see the normal blame view.

30 lines
1.3 KiB
Plaintext
Raw Normal View History

[mips] Properly select abs and sqrt instructions - Alter abs for micromips to have both AFGR64 and FGR64 variants, same as sqrt - Remove sqrt and abs from MicroMips32r6InstrInfo.td, use micromips FGR64 variants - Restrict non-micromips abs/sqrt with NotInMicroMips predicate Differential revision: https://reviews.llvm.org/D41439 llvm-svn: 323184
2018-01-23 18:09:39 +08:00
# RUN: llvm-mc --disassemble -arch=mips -mcpu=mips32r3 -mattr=+fp64 %s | \
# RUN: FileCheck %s
0x46 0x00 0x60 0x04 # CHECK: sqrt.s $f0, $f12
0x46 0x00 0x60 0x05 # CHECK: abs.s $f0, $f12
0x46 0x20 0x60 0x04 # CHECK: sqrt.d $f0, $f12
0x46 0x20 0x60 0x05 # CHECK: abs.d $f0, $f12
[mips] Define certain instructions in microMIPS32r3 Instructions affected: mthc1, mfhc1, add.d, sub.d, mul.d, div.d, mov.d, neg.d, cvt.w.d, cvt.d.s, cvt.d.w, cvt.s.d These instructions are now defined for microMIPS32r3 + microMIPS32r6 in MicroMipsInstrFPU.td since they shared their encoding with those already defined in microMIPS32r6InstrInfo.td and have been therefore removed from the latter file. Some instructions present in MicroMipsInstrFPU.td which did not have both AFGR64 and FGR64 variants defined have been altered to do so. Differential revision: https://reviews.llvm.org/D42738 llvm-svn: 324584
2018-02-08 17:25:17 +08:00
0x46 0x24 0x10 0x00 # CHECK: add.d $f0, $f2, $f4
0x46 0x24 0x10 0x01 # CHECK: sub.d $f0, $f2, $f4
0x46 0x24 0x10 0x02 # CHECK: mul.d $f0, $f2, $f4
0x46 0x24 0x10 0x03 # CHECK: div.d $f0, $f2, $f4
0x46 0x20 0x10 0x06 # CHECK: mov.d $f0, $f2
0x46 0x20 0x10 0x07 # CHECK: neg.d $f0, $f2
0x46 0x20 0x10 0x24 # CHECK: cvt.w.d $f0, $f2
0x46 0x00 0x10 0x21 # CHECK: cvt.d.s $f0, $f2
0x46 0x80 0x10 0x21 # CHECK: cvt.d.w $f0, $f2
0x46 0x20 0x10 0x20 # CHECK: cvt.s.d $f0, $f2
[mips] Add missing instructions Add pll.ps, plu.ps, cvt.s.pu, cvt.s.pl, cvt.ps instructions for FP64. Differential Revision: https://reviews.llvm.org/D50437 llvm-svn: 340920
2018-08-29 19:35:03 +08:00
0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16
0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30
0x46 0xc0 0xd3 0xa0 # CHECK: cvt.s.pu $f14, $f26
0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20
0x46 0xc0 0x17 0xa8 # CHECK: cvt.s.pl $f30, $f2
0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28
[mips] Define certain instructions in microMIPS32r3 Instructions affected: mthc1, mfhc1, add.d, sub.d, mul.d, div.d, mov.d, neg.d, cvt.w.d, cvt.d.s, cvt.d.w, cvt.s.d These instructions are now defined for microMIPS32r3 + microMIPS32r6 in MicroMipsInstrFPU.td since they shared their encoding with those already defined in microMIPS32r6InstrInfo.td and have been therefore removed from the latter file. Some instructions present in MicroMipsInstrFPU.td which did not have both AFGR64 and FGR64 variants defined have been altered to do so. Differential revision: https://reviews.llvm.org/D42738 llvm-svn: 324584
2018-02-08 17:25:17 +08:00
0x44 0xe4 0x00 0x00 # CHECK: mthc1 $4, $f0
0x44 0x64 0x00 0x00 # CHECK: mfhc1 $4, $f0
[mips] Add tests to check disassembling of add.ps/mul.ps/sub.ps instructions
2020-11-05 21:30:45 +08:00
0x46 0xda 0x71 0x00 # CHECK: add.ps $f4, $f14, $f26
0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
0x46 0xda 0x71 0x02 # CHECK: mul.ps $f4, $f14, $f26