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llvm-project/llvm/test/MC/Disassembler/AMDGPU/smrd_vi.txt

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[AMDGPU] add VI disassembler tests. NFC. Autogenerated from the corresponding assembler tests with a few FIXME added (will fix soon). Differential Revision: http://reviews.llvm.org/D18249 llvm-svn: 263729
2016-03-18 01:56:33 +08:00
# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
# VI: s_load_dword s1, s[2:3], 0xfc ; encoding: [0x41,0x00,0x02,0xc0,0xfc,0x00,0x00,0x00]
0x41 0x00 0x02 0xc0 0xfc 0x00 0x00 0x00
# VI: s_load_dword s1, s[2:3], 0xff ; encoding: [0x41,0x00,0x02,0xc0,0xff,0x00,0x00,0x00]
0x41 0x00 0x02 0xc0 0xff 0x00 0x00 0x00
[AMDGPU] Fix SMEM instructions encoding/operand namings Differential Revision: http://reviews.llvm.org/D17651 llvm-svn: 263108
2016-03-10 21:06:08 +08:00
# VI: s_load_dword s1, s[2:3], 0x1 ; encoding: [0x41,0x00,0x02,0xc0,0x01,0x00,0x00,0x00]
0x41 0x00 0x02 0xc0 0x01 0x00 0x00 0x00
[AMDGPU][MC][gfx8] Support 20-bit immediate offset in SMEM instructions. Fixes Bug 30808. Note that passing subtarget information to predicates seems too complicated, so gfx8-specific def smrd_offset_20 introduced. Old gfx6/7-specific def renamed to smrd_offset_8 for clarity. Lit tests updated. Differential Revision: https://reviews.llvm.org/D26085 llvm-svn: 285590
2016-11-01 00:07:39 +08:00
# VI: s_load_dword s1, s[2:3], 0xfffff ; encoding: [0x41,0x00,0x02,0xc0,0xff,0xff,0x0f,0x00]
0x41,0x00,0x02,0xc0,0xff,0xff,0x0f,0x00
[AMDGPU] Fix SMEM instructions encoding/operand namings Differential Revision: http://reviews.llvm.org/D17651 llvm-svn: 263108
2016-03-10 21:06:08 +08:00
# VI: s_load_dword s1, s[2:3], s4 ; encoding: [0x41,0x00,0x00,0xc0,0x04,0x00,0x00,0x00]
0x41 0x00 0x00 0xc0 0x04 0x00 0x00 0x00
# VI: s_load_dwordx2 s[2:3], s[2:3], 0x1 ; encoding: [0x81,0x00,0x06,0xc0,0x01,0x00,0x00,0x00]
0x81 0x00 0x06 0xc0 0x01 0x00 0x00 0x00
# VI: s_load_dwordx2 s[2:3], s[2:3], s4 ; encoding: [0x81,0x00,0x04,0xc0,0x04,0x00,0x00,0x00]
0x81 0x00 0x04 0xc0 0x04 0x00 0x00 0x00
# VI: s_load_dwordx4 s[4:7], s[2:3], 0x1 ; encoding: [0x01,0x01,0x0a,0xc0,0x01,0x00,0x00,0x00]
0x01 0x01 0x0a 0xc0 0x01 0x00 0x00 0x00
# VI: s_load_dwordx4 s[4:7], s[2:3], s4 ; encoding: [0x01,0x01,0x08,0xc0,0x04,0x00,0x00,0x00]
0x01 0x01 0x08 0xc0 0x04 0x00 0x00 0x00
# VI: s_load_dwordx8 s[8:15], s[2:3], 0x1 ; encoding: [0x01,0x02,0x0e,0xc0,0x01,0x00,0x00,0x00]
0x01 0x02 0x0e 0xc0 0x01 0x00 0x00 0x00
# VI: s_load_dwordx8 s[8:15], s[2:3], s4 ; encoding: [0x01,0x02,0x0c,0xc0,0x04,0x00,0x00,0x00]
0x01 0x02 0x0c 0xc0 0x04 0x00 0x00 0x00
# VI: s_load_dwordx16 s[16:31], s[2:3], 0x1 ; encoding: [0x01,0x04,0x12,0xc0,0x01,0x00,0x00,0x00]
0x01 0x04 0x12 0xc0 0x01 0x00 0x00 0x00
# VI: s_load_dwordx16 s[16:31], s[2:3], s4 ; encoding: [0x01,0x04,0x10,0xc0,0x04,0x00,0x00,0x00]
0x01 0x04 0x10 0xc0 0x04 0x00 0x00 0x00
[AMDGPU] add VI disassembler tests. NFC. Autogenerated from the corresponding assembler tests with a few FIXME added (will fix soon). Differential Revision: http://reviews.llvm.org/D18249 llvm-svn: 263729
2016-03-18 01:56:33 +08:00
# VI: s_buffer_load_dword s1, s[4:7], 0x1 ; encoding: [0x42,0x00,0x22,0xc0,0x01,0x00,0x00,0x00]
0x42 0x00 0x22 0xc0 0x01 0x00 0x00 0x00
# VI: s_buffer_load_dword s1, s[4:7], s4 ; encoding: [0x42,0x00,0x20,0xc0,0x04,0x00,0x00,0x00]
0x42 0x00 0x20 0xc0 0x04 0x00 0x00 0x00
# VI: s_buffer_load_dwordx2 s[8:9], s[4:7], 0x1 ; encoding: [0x02,0x02,0x26,0xc0,0x01,0x00,0x00,0x00]
0x02 0x02 0x26 0xc0 0x01 0x00 0x00 0x00
# VI: s_buffer_load_dwordx2 s[8:9], s[4:7], s4 ; encoding: [0x02,0x02,0x24,0xc0,0x04,0x00,0x00,0x00]
0x02 0x02 0x24 0xc0 0x04 0x00 0x00 0x00
# VI: s_buffer_load_dwordx4 s[8:11], s[4:7], 0x1 ; encoding: [0x02,0x02,0x2a,0xc0,0x01,0x00,0x00,0x00]
0x02 0x02 0x2a 0xc0 0x01 0x00 0x00 0x00
# VI: s_buffer_load_dwordx4 s[8:11], s[4:7], s4 ; encoding: [0x02,0x02,0x28,0xc0,0x04,0x00,0x00,0x00]
0x02 0x02 0x28 0xc0 0x04 0x00 0x00 0x00
# VI: s_buffer_load_dwordx8 s[8:15], s[4:7], 0x1 ; encoding: [0x02,0x02,0x2e,0xc0,0x01,0x00,0x00,0x00]
0x02 0x02 0x2e 0xc0 0x01 0x00 0x00 0x00
# VI: s_buffer_load_dwordx8 s[8:15], s[4:7], s4 ; encoding: [0x02,0x02,0x2c,0xc0,0x04,0x00,0x00,0x00]
0x02 0x02 0x2c 0xc0 0x04 0x00 0x00 0x00
# VI: s_buffer_load_dwordx16 s[16:31], s[4:7], 0x1 ; encoding: [0x02,0x04,0x32,0xc0,0x01,0x00,0x00,0x00]
0x02 0x04 0x32 0xc0 0x01 0x00 0x00 0x00
# VI: s_buffer_load_dwordx16 s[16:31], s[4:7], s4 ; encoding: [0x02,0x04,0x30,0xc0,0x04,0x00,0x00,0x00]
0x02 0x04 0x30 0xc0 0x04 0x00 0x00 0x00
[AMDGPU] Fix SMEM instructions encoding/operand namings Differential Revision: http://reviews.llvm.org/D17651 llvm-svn: 263108
2016-03-10 21:06:08 +08:00
# VI: s_dcache_inv ; encoding: [0x00,0x00,0x80,0xc0,0x00,0x00,0x00,0x00]
0x00 0x00 0x80 0xc0 0x00 0x00 0x00 0x00
# VI: s_dcache_inv_vol ; encoding: [0x00,0x00,0x88,0xc0,0x00,0x00,0x00,0x00]
0x00 0x00 0x88 0xc0 0x00 0x00 0x00 0x00
[AMDGPU] add VI disassembler tests. NFC. Autogenerated from the corresponding assembler tests with a few FIXME added (will fix soon). Differential Revision: http://reviews.llvm.org/D18249 llvm-svn: 263729
2016-03-18 01:56:33 +08:00
# VI: s_memtime s[4:5] ; encoding: [0x00,0x01,0x90,0xc0,0x00,0x00,0x00,0x00]
0x00 0x01 0x90 0xc0 0x00 0x00 0x00 0x00