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llvm-project/llvm/test/MC/Disassembler/AMDGPU/gfx10_mimg.txt

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[AMDGPU] gfx1010 MIMG implementation Differential Revision: https://reviews.llvm.org/D61339 llvm-svn: 359698
2019-05-02 00:32:58 +08:00
# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX10 %s
# GFX10: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm ; encoding: [0x00,0x1f,0x00,0xf0,0x00,0x00,0x00,0x00]
0x00,0x1f,0x00,0xf0,0x00,0x00,0x00,0x00
# GFX10: image_load v[0:3], v[1:2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm ; encoding: [0x08,0x1f,0x00,0xf0,0x01,0x00,0x00,0x00]
0x08,0x1f,0x00,0xf0,0x01,0x00,0x00,0x00
# GFX10: image_load v[252:255], v[2:4], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm ; encoding: [0x10,0x1f,0x00,0xf0,0x02,0xfc,0x00,0x00]
0x10,0x1f,0x00,0xf0,0x02,0xfc,0x00,0x00
# GFX10: image_load v[252:255], v[3:5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE unorm ; encoding: [0x18,0x1f,0x00,0xf0,0x03,0xfc,0x00,0x00]
0x18,0x1f,0x00,0xf0,0x03,0xfc,0x00,0x00
# GFX10: image_load v[253:255], v[4:5], s[0:7] dmask:0xb dim:SQ_RSRC_IMG_1D_ARRAY unorm ; encoding: [0x20,0x1b,0x00,0xf0,0x04,0xfd,0x00,0x00]
0x20,0x1b,0x00,0xf0,0x04,0xfd,0x00,0x00
# GFX10: image_load v[254:255], v[5:7], s[0:7] dmask:0x9 dim:SQ_RSRC_IMG_2D_ARRAY unorm ; encoding: [0x28,0x19,0x00,0xf0,0x05,0xfe,0x00,0x00]
0x28,0x19,0x00,0xf0,0x05,0xfe,0x00,0x00
# GFX10: image_load v255, v[6:8], s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_2D_MSAA unorm ; encoding: [0x30,0x18,0x00,0xf0,0x06,0xff,0x00,0x00]
0x30,0x18,0x00,0xf0,0x06,0xff,0x00,0x00
# GFX10: image_load v65, v[7:10], s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm ; encoding: [0x38,0x18,0x00,0xf0,0x07,0x41,0x00,0x00]
0x38,0x18,0x00,0xf0,0x07,0x41,0x00,0x00
# GFX10: image_load_mip v[16:19], v[8:9], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_1D unorm ; encoding: [0x00,0x1f,0x04,0xf0,0x08,0x10,0x01,0x00]
0x00,0x1f,0x04,0xf0,0x08,0x10,0x01,0x00
# GFX10: image_load_pck v[16:19], v[8:9], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D unorm ; encoding: [0x08,0x1f,0x08,0xf0,0x08,0x10,0x01,0x00]
0x08,0x1f,0x08,0xf0,0x08,0x10,0x01,0x00
# GFX10: image_load_pck_sgn v[16:19], v[8:9], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D unorm glc ; encoding: [0x08,0x3f,0x0c,0xf0,0x08,0x10,0x01,0x00]
0x08,0x3f,0x0c,0xf0,0x08,0x10,0x01,0x00
# GFX10: image_load_mip_pck v[16:19], v[8:10], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D unorm slc ; encoding: [0x08,0x1f,0x10,0xf2,0x08,0x10,0x01,0x00]
0x08,0x1f,0x10,0xf2,0x08,0x10,0x01,0x00
# GFX10: image_load_mip_pck_sgn v[16:19], v[8:10], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D unorm dlc ; encoding: [0x88,0x1f,0x14,0xf0,0x08,0x10,0x01,0x00]
0x88,0x1f,0x14,0xf0,0x08,0x10,0x01,0x00
# TODO: This is incorrect: r128 should use a 128-bit register for srsrc
# GFX10: image_load_mip_pck_sgn v[16:19], v[8:10], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D unorm r128 ; encoding: [0x08,0x9f,0x14,0xf0,0x08,0x10,0x01,0x00]
0x08,0x9f,0x14,0xf0,0x08,0x10,0x01,0x00
[AMDGPU][MC] Add tfe disassembler support MIMG opcodes With tfe on there can be a vgpr write to vdata+1. Add tablegen support for 5 register vdata store. This is required for 4 register vdata store with tfe. Differential Revision: https://reviews.llvm.org/D94960
2021-01-20 17:09:59 +08:00
# GFX10: image_load v16, v[8:9], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x01,0x00,0xf0,0x08,0x10,0x18,0x00]
0x08,0x01,0x00,0xf0,0x08,0x10,0x18,0x00
# GFX10: image_load v[16:17], v[8:9], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x03,0x00,0xf0,0x08,0x10,0x18,0x00]
0x08,0x03,0x00,0xf0,0x08,0x10,0x18,0x00
# GFX10: image_load v[16:18], v[8:9], s[96:103] dmask:0x7 dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x07,0x00,0xf0,0x08,0x10,0x18,0x00]
0x08,0x07,0x00,0xf0,0x08,0x10,0x18,0x00
# GFX10: image_load v[16:19], v[8:9], s[96:103] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x0f,0x00,0xf0,0x08,0x10,0x18,0x00]
0x08,0x0f,0x00,0xf0,0x08,0x10,0x18,0x00
# GFX10: image_load v[16:17], v[8:9], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_2D tfe ; encoding: [0x08,0x01,0x01,0xf0,0x08,0x10,0x18,0x00]
0x08,0x01,0x01,0xf0,0x08,0x10,0x18,0x00
# GFX10: image_load v[16:18], v[8:9], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D tfe ; encoding: [0x08,0x03,0x01,0xf0,0x08,0x10,0x18,0x00]
0x08,0x03,0x01,0xf0,0x08,0x10,0x18,0x00
# GFX10: image_load v[16:19], v[8:9], s[96:103] dmask:0x7 dim:SQ_RSRC_IMG_2D tfe ; encoding: [0x08,0x07,0x01,0xf0,0x08,0x10,0x18,0x00]
0x08,0x07,0x01,0xf0,0x08,0x10,0x18,0x00
# GFX10: image_load v[16:20], v[8:9], s[96:103] dmask:0xf dim:SQ_RSRC_IMG_2D tfe ; encoding: [0x08,0x0f,0x01,0xf0,0x08,0x10,0x18,0x00]
0x08,0x0f,0x01,0xf0,0x08,0x10,0x18,0x00
# GFX10: image_load v16, v[8:9], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_2D d16 ; encoding: [0x08,0x01,0x00,0xf0,0x08,0x10,0x18,0x80]
0x08,0x01,0x00,0xf0,0x08,0x10,0x18,0x80
# GFX10: image_load v16, v[8:9], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D d16 ; encoding: [0x08,0x03,0x00,0xf0,0x08,0x10,0x18,0x80]
0x08,0x03,0x00,0xf0,0x08,0x10,0x18,0x80
# GFX10: image_load v[16:17], v[8:9], s[96:103] dmask:0x7 dim:SQ_RSRC_IMG_2D d16 ; encoding: [0x08,0x07,0x00,0xf0,0x08,0x10,0x18,0x80]
0x08,0x07,0x00,0xf0,0x08,0x10,0x18,0x80
# GFX10: image_load v[16:17], v[8:9], s[96:103] dmask:0xf dim:SQ_RSRC_IMG_2D d16 ; encoding: [0x08,0x0f,0x00,0xf0,0x08,0x10,0x18,0x80]
0x08,0x0f,0x00,0xf0,0x08,0x10,0x18,0x80
# GFX10: image_load v[16:17], v[8:9], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_2D tfe d16 ; encoding: [0x08,0x01,0x01,0xf0,0x08,0x10,0x18,0x80]
0x08,0x01,0x01,0xf0,0x08,0x10,0x18,0x80
# GFX10: image_load v[16:17], v[8:9], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D tfe d16 ; encoding: [0x08,0x03,0x01,0xf0,0x08,0x10,0x18,0x80]
0x08,0x03,0x01,0xf0,0x08,0x10,0x18,0x80
# GFX10: image_load v[16:18], v[8:9], s[96:103] dmask:0x7 dim:SQ_RSRC_IMG_2D tfe d16 ; encoding: [0x08,0x07,0x01,0xf0,0x08,0x10,0x18,0x80]
0x08,0x07,0x01,0xf0,0x08,0x10,0x18,0x80
# GFX10: image_load v[16:18], v[8:9], s[96:103] dmask:0xf dim:SQ_RSRC_IMG_2D tfe d16 ; encoding: [0x08,0x0f,0x01,0xf0,0x08,0x10,0x18,0x80]
0x08,0x0f,0x01,0xf0,0x08,0x10,0x18,0x80
[AMDGPU] gfx1010 MIMG implementation Differential Revision: https://reviews.llvm.org/D61339 llvm-svn: 359698
2019-05-02 00:32:58 +08:00
# GFX10: image_store v16, v[8:9], s[96:103] dmask:0x4 dim:SQ_RSRC_IMG_2D unorm ; encoding: [0x08,0x14,0x20,0xf0,0x08,0x10,0x18,0x00]
0x08,0x14,0x20,0xf0,0x08,0x10,0x18,0x00
# GFX10: image_store v[16:17], v[8:10], s[96:103] dmask:0x5 dim:SQ_RSRC_IMG_3D unorm ; encoding: [0x10,0x15,0x20,0xf0,0x08,0x10,0x18,0x00]
0x10,0x15,0x20,0xf0,0x08,0x10,0x18,0x00
# GFX10: image_store v[16:18], v[8:10], s[96:103] dmask:0xd dim:SQ_RSRC_IMG_CUBE unorm ; encoding: [0x18,0x1d,0x20,0xf0,0x08,0x10,0x18,0x00]
0x18,0x1d,0x20,0xf0,0x08,0x10,0x18,0x00
# GFX10: image_store v[16:19], v[8:10], s[96:103] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY unorm ; encoding: [0x28,0x1f,0x20,0xf0,0x08,0x10,0x18,0x00]
0x28,0x1f,0x20,0xf0,0x08,0x10,0x18,0x00
# GFX10: image_store_mip v[16:19], v[8:10], s[96:103] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY unorm ; encoding: [0x20,0x1f,0x24,0xf0,0x08,0x10,0x18,0x00]
0x20,0x1f,0x24,0xf0,0x08,0x10,0x18,0x00
# GFX10: image_store_pck v[16:19], v[8:10], s[96:103] dmask:0xf dim:SQ_RSRC_IMG_3D unorm ; encoding: [0x10,0x1f,0x28,0xf0,0x08,0x10,0x18,0x00]
0x10,0x1f,0x28,0xf0,0x08,0x10,0x18,0x00
# GFX10: image_store_mip_pck v[16:19], v[8:11], s[96:103] dmask:0xf dim:SQ_RSRC_IMG_3D unorm ; encoding: [0x10,0x1f,0x2c,0xf0,0x08,0x10,0x18,0x00]
0x10,0x1f,0x2c,0xf0,0x08,0x10,0x18,0x00
[AMDGPU][MC] Add tfe disassembler support MIMG opcodes With tfe on there can be a vgpr write to vdata+1. Add tablegen support for 5 register vdata store. This is required for 4 register vdata store with tfe. Differential Revision: https://reviews.llvm.org/D94960
2021-01-20 17:09:59 +08:00
# GFX10: image_store v16, v[8:9], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x01,0x20,0xf0,0x08,0x10,0x18,0x00]
0x08,0x01,0x20,0xf0,0x08,0x10,0x18,0x00
# GFX10: image_store v[16:17], v[8:9], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x03,0x20,0xf0,0x08,0x10,0x18,0x00]
0x08,0x03,0x20,0xf0,0x08,0x10,0x18,0x00
# GFX10: image_store v[16:18], v[8:9], s[96:103] dmask:0x7 dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x07,0x20,0xf0,0x08,0x10,0x18,0x00]
0x08,0x07,0x20,0xf0,0x08,0x10,0x18,0x00
# GFX10: image_store v[16:19], v[8:9], s[96:103] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x0f,0x20,0xf0,0x08,0x10,0x18,0x00]
0x08,0x0f,0x20,0xf0,0x08,0x10,0x18,0x00
# GFX10: image_store v[16:17], v[8:9], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_2D tfe ; encoding: [0x08,0x01,0x21,0xf0,0x08,0x10,0x18,0x00]
0x08,0x01,0x21,0xf0,0x08,0x10,0x18,0x00
# GFX10: image_store v[16:18], v[8:9], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D tfe ; encoding: [0x08,0x03,0x21,0xf0,0x08,0x10,0x18,0x00]
0x08,0x03,0x21,0xf0,0x08,0x10,0x18,0x00
# GFX10: image_store v[16:19], v[8:9], s[96:103] dmask:0x7 dim:SQ_RSRC_IMG_2D tfe ; encoding: [0x08,0x07,0x21,0xf0,0x08,0x10,0x18,0x00]
0x08,0x07,0x21,0xf0,0x08,0x10,0x18,0x00
# GFX10: image_store v[16:20], v[8:9], s[96:103] dmask:0xf dim:SQ_RSRC_IMG_2D tfe ; encoding: [0x08,0x0f,0x21,0xf0,0x08,0x10,0x18,0x00]
0x08,0x0f,0x21,0xf0,0x08,0x10,0x18,0x00
# GFX10: image_store v16, v[8:9], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_2D d16 ; encoding: [0x08,0x01,0x20,0xf0,0x08,0x10,0x18,0x80]
0x08,0x01,0x20,0xf0,0x08,0x10,0x18,0x80
# GFX10: image_store v16, v[8:9], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D d16 ; encoding: [0x08,0x03,0x20,0xf0,0x08,0x10,0x18,0x80]
0x08,0x03,0x20,0xf0,0x08,0x10,0x18,0x80
# GFX10: image_store v[16:17], v[8:9], s[96:103] dmask:0x7 dim:SQ_RSRC_IMG_2D d16 ; encoding: [0x08,0x07,0x20,0xf0,0x08,0x10,0x18,0x80]
0x08,0x07,0x20,0xf0,0x08,0x10,0x18,0x80
# GFX10: image_store v[16:17], v[8:9], s[96:103] dmask:0xf dim:SQ_RSRC_IMG_2D d16 ; encoding: [0x08,0x0f,0x20,0xf0,0x08,0x10,0x18,0x80]
0x08,0x0f,0x20,0xf0,0x08,0x10,0x18,0x80
# GFX10: image_store v[16:17], v[8:9], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_2D tfe d16 ; encoding: [0x08,0x01,0x21,0xf0,0x08,0x10,0x18,0x80]
0x08,0x01,0x21,0xf0,0x08,0x10,0x18,0x80
# GFX10: image_store v[16:17], v[8:9], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D tfe d16 ; encoding: [0x08,0x03,0x21,0xf0,0x08,0x10,0x18,0x80]
0x08,0x03,0x21,0xf0,0x08,0x10,0x18,0x80
# GFX10: image_store v[16:18], v[8:9], s[96:103] dmask:0x7 dim:SQ_RSRC_IMG_2D tfe d16 ; encoding: [0x08,0x07,0x21,0xf0,0x08,0x10,0x18,0x80]
0x08,0x07,0x21,0xf0,0x08,0x10,0x18,0x80
# GFX10: image_store v[16:18], v[8:9], s[96:103] dmask:0xf dim:SQ_RSRC_IMG_2D tfe d16 ; encoding: [0x08,0x0f,0x21,0xf0,0x08,0x10,0x18,0x80]
0x08,0x0f,0x21,0xf0,0x08,0x10,0x18,0x80
[AMDGPU] gfx1010 MIMG implementation Differential Revision: https://reviews.llvm.org/D61339 llvm-svn: 359698
2019-05-02 00:32:58 +08:00
# GFX10: image_get_resinfo v[16:19], v8, s[96:103] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY unorm ; encoding: [0x28,0x1f,0x38,0xf0,0x08,0x10,0x18,0x00]
0x28,0x1f,0x38,0xf0,0x08,0x10,0x18,0x00
# GFX10: image_atomic_swap v16, v8, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm ; encoding: [0x00,0x11,0x3c,0xf0,0x08,0x10,0x18,0x00]
0x00,0x11,0x3c,0xf0,0x08,0x10,0x18,0x00
# NOTE: Contents of unused NSA bytes are NOT preserved.
# GFX10: image_atomic_cmpswap v[16:17], [v8, v9], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D unorm glc ; encoding: [0x0a,0x33,0x40,0xf0,0x08,0x10,0x18,0x00,0x09,0x00,0x00,0x00]
0x0a,0x33,0x40,0xf0,0x08,0x10,0x18,0x00,0x09,0x0a,0x0b,0x0c
# GFX10: image_atomic_add v16, [v8, v9, v10], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_3D unorm glc ; encoding: [0x12,0x31,0x44,0xf0,0x08,0x10,0x18,0x00,0x09,0x0a,0x00,0x00]
0x12,0x31,0x44,0xf0,0x08,0x10,0x18,0x00,0x09,0x0a,0x0b,0x0c
# GFX10: image_atomic_sub v16, [v8, v9, v10], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_CUBE unorm glc ; encoding: [0x1a,0x31,0x48,0xf0,0x08,0x10,0x18,0x00,0x09,0x0a,0x00,0x00]
0x1a,0x31,0x48,0xf0,0x08,0x10,0x18,0x00,0x09,0x0a,0x0b,0x0c
# GFX10: image_atomic_smin v16, [v8, v9], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY unorm glc ; encoding: [0x22,0x31,0x50,0xf0,0x08,0x10,0x18,0x00,0x09,0x00,0x00,0x00]
0x22,0x31,0x50,0xf0,0x08,0x10,0x18,0x00,0x09,0x0a,0x0b,0x0c
# GFX10: image_atomic_umin v16, [v8, v9, v10], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY unorm glc ; encoding: [0x2a,0x31,0x54,0xf0,0x08,0x10,0x18,0x00,0x09,0x0a,0x00,0x00]
0x2a,0x31,0x54,0xf0,0x08,0x10,0x18,0x00,0x09,0x0a,0x0b,0x0c
# GFX10: image_atomic_smax v16, [v8, v9, v10], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm glc ; encoding: [0x32,0x31,0x58,0xf0,0x08,0x10,0x18,0x00,0x09,0x0a,0x00,0x00]
0x32,0x31,0x58,0xf0,0x08,0x10,0x18,0x00,0x09,0x0a,0x0b,0x0c
# GFX10: image_atomic_umax v16, [v8, v9, v10, v11], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm glc ; encoding: [0x3a,0x31,0x5c,0xf0,0x08,0x10,0x18,0x00,0x09,0x0a,0x0b,0x00]
0x3a,0x31,0x5c,0xf0,0x08,0x10,0x18,0x00,0x09,0x0a,0x0b,0x0c
# GFX10: image_atomic_and v16, v8, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc ; encoding: [0x00,0x31,0x60,0xf0,0x08,0x10,0x18,0x00]
0x00,0x31,0x60,0xf0,0x08,0x10,0x18,0x00
# GFX10: image_atomic_or v16, v8, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc ; encoding: [0x00,0x31,0x64,0xf0,0x08,0x10,0x18,0x00]
0x00,0x31,0x64,0xf0,0x08,0x10,0x18,0x00
# GFX10: image_atomic_xor v16, v8, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc ; encoding: [0x00,0x31,0x68,0xf0,0x08,0x10,0x18,0x00]
0x00,0x31,0x68,0xf0,0x08,0x10,0x18,0x00
# GFX10: image_atomic_inc v16, v8, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc ; encoding: [0x00,0x31,0x6c,0xf0,0x08,0x10,0x18,0x00]
0x00,0x31,0x6c,0xf0,0x08,0x10,0x18,0x00
# GFX10: image_atomic_dec v16, v8, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc ; encoding: [0x00,0x31,0x70,0xf0,0x08,0x10,0x18,0x00]
0x00,0x31,0x70,0xf0,0x08,0x10,0x18,0x00
[AMDGPU] Refactor MIMG tables to better handle hardware variants Add mimgopc object to represent the opcode allowing different opcodes for different hardware variants. This enables image_atomic_fcmpswap, image_atomic_fmin, and image_atomic_fmax on GFX10 Reviewed By: foad, rampitec Differential Revision: https://reviews.llvm.org/D96309
2021-02-11 10:18:44 +08:00
# GFX10: image_atomic_fcmpswap v[4:5], v32, s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_1D glc ; encoding: [0x00,0x23,0x74,0xf0,0x20,0x04,0x18,0x00]
0x00,0x23,0x74,0xf0,0x20,0x04,0x18,0x00
# GFX10: image_atomic_fmin v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D glc ; encoding: [0x00,0x21,0x78,0xf0,0x20,0x04,0x18,0x00]
0x00,0x21,0x78,0xf0,0x20,0x04,0x18,0x00
# GFX10: image_atomic_fmax v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D glc ; encoding: [0x00,0x21,0x7c,0xf0,0x20,0x04,0x18,0x00]
0x00,0x21,0x7c,0xf0,0x20,0x04,0x18,0x00
[AMDGPU] gfx1010 MIMG implementation Differential Revision: https://reviews.llvm.org/D61339 llvm-svn: 359698
2019-05-02 00:32:58 +08:00
# GFX10: image_sample v[16:19], v8, s[96:103], s[0:3] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x0f,0x80,0xf0,0x08,0x10,0x18,0x00]
0x00,0x0f,0x80,0xf0,0x08,0x10,0x18,0x00
# GFX10: image_sample_cl v[16:17], [v8, v9, v10], s[96:103], s[0:3] dmask:0xf dim:SQ_RSRC_IMG_2D d16 ; encoding: [0x0a,0x0f,0x84,0xf0,0x08,0x10,0x18,0x80,0x09,0x0a,0x00,0x00]
0x0a,0x0f,0x84,0xf0,0x08,0x10,0x18,0x80,0x09,0x0a,0x0b,0x0c
# GFX10: image_sample_d v[16:19], [v8, v9, v10], s[96:103], s[0:3] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x02,0x0f,0x88,0xf0,0x08,0x10,0x18,0x00,0x09,0x0a,0x00,0x00]
0x02,0x0f,0x88,0xf0,0x08,0x10,0x18,0x00,0x09,0x0a,0x0b,0x0c
# GFX10: image_sample_d_cl v[16:19], [v8, v9, v10, v11, v12, v13, v14], s[20:27], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x0c,0x0f,0x8c,0xf0,0x08,0x10,0x25,0x00,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x00,0x00]
0x0c,0x0f,0x8c,0xf0,0x08,0x10,0x25,0x00,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10
# GFX10: image_sample_l v[16:19], [v8, v9, v10, v11], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_3D ; encoding: [0x12,0x0f,0x90,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x00]
0x12,0x0f,0x90,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_sample_b v[16:19], [v8, v9, v10, v11], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_CUBE ; encoding: [0x1a,0x0f,0x94,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x00]
0x1a,0x0f,0x94,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_sample_b_cl v[16:19], [v8, v9, v10, v11], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x22,0x0f,0x98,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x00]
0x22,0x0f,0x98,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_sample_lz v[16:19], [v8, v9, v10], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x2a,0x0f,0x9c,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x00,0x00]
0x2a,0x0f,0x9c,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_sample_c v[16:19], [v8, v9, v10], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x0a,0x0f,0xa0,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x00,0x00]
0x0a,0x0f,0xa0,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_sample_c_cl v[16:19], [v8, v9, v10, v11, v12], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_3D ; encoding: [0x12,0x0f,0xa4,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c]
0x12,0x0f,0xa4,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_sample_c_d v[16:19], [v8, v9, v10, v11, v12, v13, v14, v15, v16, v17], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_3D ; encoding: [0x16,0x0f,0xa8,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x00,0x00,0x00]
0x16,0x0f,0xa8,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13,0x14
# GFX10: image_sample_c_d_cl v[16:19], [v8, v9, v10, v11, v12, v13, v14, v15, v16], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_CUBE ; encoding: [0x1c,0x0f,0xac,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10]
0x1c,0x0f,0xac,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10
# GFX10: image_sample_c_l v[16:19], [v8, v9, v10, v11, v12], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_CUBE ; encoding: [0x1a,0x0f,0xb0,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c]
0x1a,0x0f,0xb0,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_sample_c_b v[16:19], v[8:15], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_CUBE ; encoding: [0x18,0x0f,0xb4,0xf0,0x08,0x10,0x25,0x03]
0x18,0x0f,0xb4,0xf0,0x08,0x10,0x25,0x03
# TODO: address of this instruction is v[250:255], but this register class does
# not exist, and the next-larger size goes beyond the last register, so
# the disassembly is not adjusted properly
# GFX10: image_sample_c_b_cl v16, v[250:252], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_CUBE ; encoding: [0x18,0x0f,0xb8,0xf0,0xfa,0x10,0x25,0x03]
0x18,0x0f,0xb8,0xf0,0xfa,0x10,0x25,0x03
# GFX10: image_sample_c_lz v[16:19], v[253:255], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x0f,0xbc,0xf0,0xfd,0x10,0x25,0x03]
0x08,0x0f,0xbc,0xf0,0xfd,0x10,0x25,0x03
# GFX10: image_sample_o v[16:19], v[252:255], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x28,0x0f,0xc0,0xf0,0xfc,0x10,0x25,0x03]
0x28,0x0f,0xc0,0xf0,0xfc,0x10,0x25,0x03
# GFX10: image_sample_cl_o v[16:19], [v8, v9, v10], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x02,0x0f,0xc4,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x00,0x00]
0x02,0x0f,0xc4,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_sample_d_o v[16:19], [v8, v9, v10, v11, v12, v13, v14], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x0c,0x0f,0xc8,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x00,0x00]
0x0c,0x0f,0xc8,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10
# GFX10: image_sample_d_cl_o v[16:19], [v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_3D ; encoding: [0x16,0x0f,0xcc,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x00,0x00]
0x16,0x0f,0xcc,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13,0x14
# GFX10: image_sample_l_o v[16:19], [v8, v9, v10, v11, v12], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_CUBE ; encoding: [0x1a,0x0f,0xd0,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c]
0x1a,0x0f,0xd0,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_sample_b_o v[16:19], [v8, v9, v10, v11], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x22,0x0f,0xd4,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x00]
0x22,0x0f,0xd4,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_sample_b_cl_o v[16:19], [v8, v9, v10, v11, v12, v13], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x2c,0x0f,0xd8,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x00,0x00,0x00]
0x2c,0x0f,0xd8,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10
# GFX10: image_sample_lz_o v[16:19], [v8, v9], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x02,0x0f,0xdc,0xf0,0x08,0x10,0x25,0x03,0x09,0x00,0x00,0x00]
0x02,0x0f,0xdc,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_sample_c_o v[16:19], [v8, v9, v10, v11], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x0a,0x0f,0xe0,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x00]
0x0a,0x0f,0xe0,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_sample_c_cl_o v[16:19], [v8, v9, v10, v11, v12, v13], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_3D ; encoding: [0x14,0x0f,0xe4,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x00,0x00,0x00]
0x14,0x0f,0xe4,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10
# GFX10: image_sample_c_d_o v[16:19], [v8, v9, v10, v11, v12, v13, v14, v15, v16], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_CUBE ; encoding: [0x1c,0x0f,0xe8,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10]
0x1c,0x0f,0xe8,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10
# GFX10: image_sample_c_d_cl_o v[16:19], [v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_3D ; encoding: [0x16,0x0f,0xec,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13,0x00]
0x16,0x0f,0xec,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13,0x14
# GFX10: image_sample_c_l_o v[16:19], [v8, v9, v10, v11, v12], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x22,0x0f,0xf0,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c]
0x22,0x0f,0xf0,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_sample_c_b_o v[16:19], [v8, v9, v10, v11, v12, v13], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x2c,0x0f,0xf4,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x00,0x00,0x00]
0x2c,0x0f,0xf4,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10
# GFX10: image_sample_c_b_cl_o v[16:19], [v8, v9, v10, v11, v12], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x02,0x0f,0xf8,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c]
0x02,0x0f,0xf8,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_sample_c_lz_o v[16:19], [v8, v9, v10, v11], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x0a,0x0f,0xfc,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x00]
0x0a,0x0f,0xfc,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_gather4 v[16:19], [v8, v9, v10], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_3D ; encoding: [0x12,0x0f,0x00,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x00,0x00]
0x12,0x0f,0x00,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_gather4_cl v[16:19], [v8, v9, v10, v11], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_CUBE ; encoding: [0x1a,0x0f,0x04,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x00]
0x1a,0x0f,0x04,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_gather4_l v[16:19], [v8, v9, v10], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x22,0x0f,0x10,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x00,0x00]
0x22,0x0f,0x10,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_gather4_b v[16:19], [v8, v9, v10, v11], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x2a,0x0f,0x14,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x00]
0x2a,0x0f,0x14,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_gather4_b_cl v[16:19], [v8, v9, v10], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x02,0x0f,0x18,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x00,0x00]
0x02,0x0f,0x18,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_gather4_lz v[16:19], [v8, v9], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x0a,0x0f,0x1c,0xf1,0x08,0x10,0x25,0x03,0x09,0x00,0x00,0x00]
0x0a,0x0f,0x1c,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_gather4_c v[16:19], [v8, v9, v10, v11], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_3D ; encoding: [0x12,0x0f,0x20,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x00]
0x12,0x0f,0x20,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_gather4_c_cl v[16:19], [v8, v9, v10, v11, v12], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_CUBE ; encoding: [0x1a,0x0f,0x24,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c]
0x1a,0x0f,0x24,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_gather4_c_l v[16:19], [v8, v9, v10, v11], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x22,0x0f,0x30,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x00]
0x22,0x0f,0x30,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_gather4_c_b v[16:19], [v8, v9, v10, v11, v12], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x2a,0x0f,0x34,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c]
0x2a,0x0f,0x34,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_gather4_c_b_cl v[16:19], [v8, v9, v10, v11], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x02,0x0f,0x38,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x00]
0x02,0x0f,0x38,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_gather4_c_lz v[16:19], [v8, v9, v10], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x0a,0x0f,0x3c,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x00,0x00]
0x0a,0x0f,0x3c,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_gather4_o v[16:19], [v8, v9, v10, v11], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_3D ; encoding: [0x12,0x0f,0x40,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x00]
0x12,0x0f,0x40,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_gather4_cl_o v[16:19], [v8, v9, v10, v11, v12], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_CUBE ; encoding: [0x1a,0x0f,0x44,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c]
0x1a,0x0f,0x44,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_gather4_l_o v[16:19], [v8, v9, v10, v11], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x22,0x0f,0x50,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x00]
0x22,0x0f,0x50,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_gather4_b_o v[16:19], [v8, v9, v10, v11, v12], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x2a,0x0f,0x54,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c]
0x2a,0x0f,0x54,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_gather4_b_cl_o v[16:19], [v8, v9, v10, v11], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x02,0x0f,0x58,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x00]
0x02,0x0f,0x58,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_gather4_lz_o v[16:19], [v8, v9, v10], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x0a,0x0f,0x5c,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x00,0x00]
0x0a,0x0f,0x5c,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_gather4_c_o v[16:19], [v8, v9, v10, v11, v12], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_3D ; encoding: [0x12,0x0f,0x60,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c]
0x12,0x0f,0x60,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_gather4_c_cl_o v[16:19], [v8, v9, v10, v11, v12, v13], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_CUBE ; encoding: [0x1c,0x0f,0x64,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x00,0x00,0x00]
0x1c,0x0f,0x64,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10
# GFX10: image_gather4_c_l_o v[16:19], [v8, v9, v10, v11, v12], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x22,0x0f,0x70,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c]
0x22,0x0f,0x70,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_gather4_c_b_o v[16:19], [v8, v9, v10, v11, v12, v13], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x2c,0x0f,0x74,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x00,0x00,0x00]
0x2c,0x0f,0x74,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10
# GFX10: image_gather4_c_b_cl_o v[16:19], [v8, v9, v10, v11, v12], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x02,0x0f,0x78,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c]
0x02,0x0f,0x78,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_gather4_c_lz_o v[16:19], [v8, v9, v10, v11], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x0a,0x0f,0x7c,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x00]
0x0a,0x0f,0x7c,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_get_lod v[16:19], [v8, v9, v10], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_3D ; encoding: [0x12,0x0f,0x80,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x00,0x00]
0x12,0x0f,0x80,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_sample_cd v[16:19], [v8, v9, v10, v11, v12, v13, v14], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_CUBE ; encoding: [0x1c,0x0f,0xa0,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x00,0x00]
0x1c,0x0f,0xa0,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10
# GFX10: image_sample_cd_cl v[16:19], [v8, v9, v10, v11, v12], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x22,0x0f,0xa4,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c]
0x22,0x0f,0xa4,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_sample_c_cd v[16:19], [v8, v9, v10, v11, v12, v13, v14, v15], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x2c,0x0f,0xa8,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x00]
0x2c,0x0f,0xa8,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10
# GFX10: image_sample_c_cd_cl v[16:19], [v8, v9, v10, v11, v12], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x02,0x0f,0xac,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c]
0x02,0x0f,0xac,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
# GFX10: image_sample_cd_o v[16:19], [v8, v9, v10, v11, v12, v13, v14], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x0c,0x0f,0xb0,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x00,0x00]
0x0c,0x0f,0xb0,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10
# GFX10: image_sample_cd_cl_o v[16:19], [v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_3D ; encoding: [0x16,0x0f,0xb4,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x00,0x00]
0x16,0x0f,0xb4,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13,0x14
# GFX10: image_sample_c_cd_o v[16:19], [v8, v9, v10, v11, v12, v13, v14, v15, v16], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_CUBE ; encoding: [0x1c,0x0f,0xb8,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10]
0x1c,0x0f,0xb8,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10
# GFX10: image_sample_c_cd_cl_o v[16:19], [v8, v9, v10, v11, v12, v13, v14], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x24,0x0f,0xbc,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x00,0x00]
0x24,0x0f,0xbc,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10