maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/MC/AVR/inst-sbic.s

Ignoring revisions in .git-blame-ignore-revs. Click here to bypass and see the normal blame view.

37 lines
1.0 KiB
ArmAsm
Raw Normal View History

[AVR] Add all of the machine code test suite Summary: This adds all of the AVR machine code tests. Reviewers: arsenm, kparzysz Subscribers: wdng, japaric Differential Revision: https://reviews.llvm.org/D26387 llvm-svn: 286417
2016-11-10 07:46:25 +08:00
; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
[AVR] Implement disassembly support for I/O instructions The in, out, and sbi/cbi family of instructions seem to require a custom decoder. I'm not exactly sure why and would prefer to convince TableGen to provide the correct decoders for these, but I can't seem to convince it to do so. They simply disassemble without any operands. Differential Revision: https://reviews.llvm.org/D74049
2020-02-05 22:04:47 +08:00
; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
[AVR] Add all of the machine code test suite Summary: This adds all of the AVR machine code tests. Reviewers: arsenm, kparzysz Subscribers: wdng, japaric Differential Revision: https://reviews.llvm.org/D26387 llvm-svn: 286417
2016-11-10 07:46:25 +08:00
foo:
sbic 4, 3
sbic 6, 2
sbic 16, 5
sbic 0, 0
[AVR] Implement disassembly support for I/O instructions The in, out, and sbi/cbi family of instructions seem to require a custom decoder. I'm not exactly sure why and would prefer to convince TableGen to provide the correct decoders for these, but I can't seem to convince it to do so. They simply disassemble without any operands. Differential Revision: https://reviews.llvm.org/D74049
2020-02-05 22:04:47 +08:00
sbic 31, 0
sbic 0, 7
sbic 31, 7
[AVR] Add all of the machine code test suite Summary: This adds all of the AVR machine code tests. Reviewers: arsenm, kparzysz Subscribers: wdng, japaric Differential Revision: https://reviews.llvm.org/D26387 llvm-svn: 286417
2016-11-10 07:46:25 +08:00
sbic foo+1, 1
; CHECK: sbic 4, 3 ; encoding: [0x23,0x99]
; CHECK: sbic 6, 2 ; encoding: [0x32,0x99]
; CHECK: sbic 16, 5 ; encoding: [0x85,0x99]
; CHECK: sbic 0, 0 ; encoding: [0x00,0x99]
[AVR] Implement disassembly support for I/O instructions The in, out, and sbi/cbi family of instructions seem to require a custom decoder. I'm not exactly sure why and would prefer to convince TableGen to provide the correct decoders for these, but I can't seem to convince it to do so. They simply disassemble without any operands. Differential Revision: https://reviews.llvm.org/D74049
2020-02-05 22:04:47 +08:00
; CHECK: sbic 31, 0 ; encoding: [0xf8,0x99]
; CHECK: sbic 0, 7 ; encoding: [0x07,0x99]
; CHECK: sbic 31, 7 ; encoding: [0xff,0x99]
[AVR] Add all of the machine code test suite Summary: This adds all of the AVR machine code tests. Reviewers: arsenm, kparzysz Subscribers: wdng, japaric Differential Revision: https://reviews.llvm.org/D26387 llvm-svn: 286417
2016-11-10 07:46:25 +08:00
; CHECK: sbic foo+1, 1 ; encoding: [0bAAAAA001,0x99]
; CHECK: ; fixup A - offset: 0, value: foo+1, kind: fixup_port5
[AVR] Implement disassembly support for I/O instructions The in, out, and sbi/cbi family of instructions seem to require a custom decoder. I'm not exactly sure why and would prefer to convince TableGen to provide the correct decoders for these, but I can't seem to convince it to do so. They simply disassemble without any operands. Differential Revision: https://reviews.llvm.org/D74049
2020-02-05 22:04:47 +08:00
; CHECK-INST: sbic 4, 3
; CHECK-INST: sbic 6, 2
; CHECK-INST: sbic 16, 5
; CHECK-INST: sbic 0, 0
; CHECK-INST: sbic 31, 0
; CHECK-INST: sbic 0, 7
; CHECK-INST: sbic 31, 7
; CHECK-INST: sbic 0, 1