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llvm-project/llvm/test/MC/AVR/inst-lsr.s

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[AVR] Add all of the machine code test suite Summary: This adds all of the AVR machine code tests. Reviewers: arsenm, kparzysz Subscribers: wdng, japaric Differential Revision: https://reviews.llvm.org/D26387 llvm-svn: 286417
2016-11-10 07:46:25 +08:00
; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
[AVR] Decode single register instructions This is a set of instructions that take just a single register as an operand, with no immediates. Because all instructions share the same format, I haven't added exhaustive bit testing to all instructions but just to the inc instruction. Differential Revision: https://reviews.llvm.org/D81968
2020-06-17 04:50:29 +08:00
; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
[AVR] Add all of the machine code test suite Summary: This adds all of the AVR machine code tests. Reviewers: arsenm, kparzysz Subscribers: wdng, japaric Differential Revision: https://reviews.llvm.org/D26387 llvm-svn: 286417
2016-11-10 07:46:25 +08:00
foo:
lsr r31
lsr r25
lsr r5
lsr r0
; CHECK: lsr r31 ; encoding: [0xf6,0x95]
; CHECK: lsr r25 ; encoding: [0x96,0x95]
; CHECK: lsr r5 ; encoding: [0x56,0x94]
; CHECK: lsr r0 ; encoding: [0x06,0x94]
[AVR] Decode single register instructions This is a set of instructions that take just a single register as an operand, with no immediates. Because all instructions share the same format, I haven't added exhaustive bit testing to all instructions but just to the inc instruction. Differential Revision: https://reviews.llvm.org/D81968
2020-06-17 04:50:29 +08:00
; CHECK-INST: lsr r31
; CHECK-INST: lsr r25
; CHECK-INST: lsr r5
; CHECK-INST: lsr r0