maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/Mips/unalignedload.ll

86 lines
3.5 KiB
LLVM
Raw Normal View History

[mips] Make Static a default relocation model for MIPS codegen This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 llvm-svn: 265949
2016-04-11 23:24:23 +08:00
; RUN: llc < %s -march=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefix=ALL -check-prefix=ALL-EL -check-prefix=MIPS32-EL
; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefix=ALL -check-prefix=ALL-EB -check-prefix=MIPS32-EB
; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefix=ALL -check-prefix=ALL-EL -check-prefix=MIPS32-EL
; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefix=ALL -check-prefix=ALL-EB -check-prefix=MIPS32-EB
; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefix=ALL -check-prefix=ALL-EL -check-prefix=MIPS32R6-EL
; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefix=ALL -check-prefix=ALL-EB -check-prefix=MIPS32R6-EB
Define unaligned load and store. llvm-svn: 137515
2011-08-13 05:30:06 +08:00
%struct.S2 = type { %struct.S1, %struct.S1 }
%struct.S1 = type { i8, i8 }
Use subword loads instead of a 4-byte load when the size of a structure (or a piece of it) that is being passed by value is smaller than a word. llvm-svn: 138007
2011-08-19 07:39:37 +08:00
%struct.S4 = type { [7 x i8] }
Define unaligned load and store. llvm-svn: 137515
2011-08-13 05:30:06 +08:00
@s2 = common global %struct.S2 zeroinitializer, align 1
Use subword loads instead of a 4-byte load when the size of a structure (or a piece of it) that is being passed by value is smaller than a word. llvm-svn: 138007
2011-08-19 07:39:37 +08:00
@s4 = common global %struct.S4 zeroinitializer, align 1
Define unaligned load and store. llvm-svn: 137515
2011-08-13 05:30:06 +08:00
[mips] Make unalignedload.ll test stricter and easier to modify for MIPS32r6/MIPS64r6 Summary: * Split into two functions, one to test each struct. * R0 and R2 must be defined by an lw with a %got reference to the correct symbol. * Test for $4 (first argument) where appropriate instead of accepting any register. * Test that the two lbu's are correctly combined into $4 Depends on D3844 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3845 llvm-svn: 209424
2014-05-22 19:55:04 +08:00
define void @bar1() nounwind {
Define unaligned load and store. llvm-svn: 137515
2011-08-13 05:30:06 +08:00
entry:
[mips] Make unalignedload.ll test stricter and easier to modify for MIPS32r6/MIPS64r6 Summary: * Split into two functions, one to test each struct. * R0 and R2 must be defined by an lw with a %got reference to the correct symbol. * Test for $4 (first argument) where appropriate instead of accepting any register. * Test that the two lbu's are correctly combined into $4 Depends on D3844 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3845 llvm-svn: 209424
2014-05-22 19:55:04 +08:00
; ALL-LABEL: bar1:
[mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6 Summary: Instead the system is required to provide some means of handling unaligned load/store without special instructions. Options include full hardware support, full trap-and-emulate, and hybrids such as hardware support within a cache line and trap-and-emulate for multi-line accesses. MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to assume that unaligned accesses are 'fast' on the basis that I expect few hardware implementations will opt for pure-software handling of unaligned accesses. The ones that do handle it purely in software can override this. mips64-load-store-left-right.ll has been merged into load-store-left-right.ll The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has been fixed and the variables renamed to clarify the units they hold. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3872 llvm-svn: 209512
2014-05-23 21:18:02 +08:00
; ALL-DAG: lw $[[R0:[0-9]+]], %got(s2)(
[mips] Make unalignedload.ll test stricter and easier to modify for MIPS32r6/MIPS64r6 Summary: * Split into two functions, one to test each struct. * R0 and R2 must be defined by an lw with a %got reference to the correct symbol. * Test for $4 (first argument) where appropriate instead of accepting any register. * Test that the two lbu's are correctly combined into $4 Depends on D3844 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3845 llvm-svn: 209424
2014-05-22 19:55:04 +08:00
[mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6 Summary: Instead the system is required to provide some means of handling unaligned load/store without special instructions. Options include full hardware support, full trap-and-emulate, and hybrids such as hardware support within a cache line and trap-and-emulate for multi-line accesses. MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to assume that unaligned accesses are 'fast' on the basis that I expect few hardware implementations will opt for pure-software handling of unaligned accesses. The ones that do handle it purely in software can override this. mips64-load-store-left-right.ll has been merged into load-store-left-right.ll The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has been fixed and the variables renamed to clarify the units they hold. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3872 llvm-svn: 209512
2014-05-23 21:18:02 +08:00
; MIPS32-EL-DAG: lbu $[[PART1:[0-9]+]], 2($[[R0]])
; MIPS32-EL-DAG: lbu $[[PART2:[0-9]+]], 3($[[R0]])
; MIPS32-EL-DAG: sll $[[T0:[0-9]+]], $[[PART2]], 8
; MIPS32-EL-DAG: or $4, $[[T0]], $[[PART1]]
[mips] Make unalignedload.ll test stricter and easier to modify for MIPS32r6/MIPS64r6 Summary: * Split into two functions, one to test each struct. * R0 and R2 must be defined by an lw with a %got reference to the correct symbol. * Test for $4 (first argument) where appropriate instead of accepting any register. * Test that the two lbu's are correctly combined into $4 Depends on D3844 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3845 llvm-svn: 209424
2014-05-22 19:55:04 +08:00
[mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6 Summary: Instead the system is required to provide some means of handling unaligned load/store without special instructions. Options include full hardware support, full trap-and-emulate, and hybrids such as hardware support within a cache line and trap-and-emulate for multi-line accesses. MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to assume that unaligned accesses are 'fast' on the basis that I expect few hardware implementations will opt for pure-software handling of unaligned accesses. The ones that do handle it purely in software can override this. mips64-load-store-left-right.ll has been merged into load-store-left-right.ll The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has been fixed and the variables renamed to clarify the units they hold. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3872 llvm-svn: 209512
2014-05-23 21:18:02 +08:00
; MIPS32-EB-DAG: lbu $[[PART1:[0-9]+]], 2($[[R0]])
; MIPS32-EB-DAG: lbu $[[PART2:[0-9]+]], 3($[[R0]])
; MIPS32-EB-DAG: sll $[[T0:[0-9]+]], $[[PART1]], 8
; MIPS32-EB-DAG: or $[[T1:[0-9]+]], $[[T0]], $[[PART2]]
; MIPS32-EB-DAG: sll $4, $[[T1]], 16
[mips] Make unalignedload.ll test stricter and easier to modify for MIPS32r6/MIPS64r6 Summary: * Split into two functions, one to test each struct. * R0 and R2 must be defined by an lw with a %got reference to the correct symbol. * Test for $4 (first argument) where appropriate instead of accepting any register. * Test that the two lbu's are correctly combined into $4 Depends on D3844 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3845 llvm-svn: 209424
2014-05-22 19:55:04 +08:00
[mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6 Summary: Instead the system is required to provide some means of handling unaligned load/store without special instructions. Options include full hardware support, full trap-and-emulate, and hybrids such as hardware support within a cache line and trap-and-emulate for multi-line accesses. MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to assume that unaligned accesses are 'fast' on the basis that I expect few hardware implementations will opt for pure-software handling of unaligned accesses. The ones that do handle it purely in software can override this. mips64-load-store-left-right.ll has been merged into load-store-left-right.ll The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has been fixed and the variables renamed to clarify the units they hold. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3872 llvm-svn: 209512
2014-05-23 21:18:02 +08:00
; MIPS32R6-DAG: lhu $[[PART1:[0-9]+]], 2($[[R0]])
[mips] Make unalignedload.ll test stricter and easier to modify for MIPS32r6/MIPS64r6 Summary: * Split into two functions, one to test each struct. * R0 and R2 must be defined by an lw with a %got reference to the correct symbol. * Test for $4 (first argument) where appropriate instead of accepting any register. * Test that the two lbu's are correctly combined into $4 Depends on D3844 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3845 llvm-svn: 209424
2014-05-22 19:55:04 +08:00
[opaque pointer type] Add textual IR support for explicit type parameter to gep operator Similar to gep (r230786) and load (r230794) changes. Similar migration script can be used to update test cases, which successfully migrated all of LLVM and Polly, but about 4 test cases needed manually changes in Clang. (this script will read the contents of stdin and massage it into stdout - wrap it in the 'apply.sh' script shown in previous commits + xargs to apply it over a large set of test cases) import fileinput import sys import re rep = re.compile(r"(getelementptr(?:\s+inbounds)?\s*\()((<\d*\s+x\s+)?([^@]*?)(|\s*addrspace\(\d+\))\s*\*(?(3)>)\s*)(?=$|%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|zeroinitializer|<|\[\[[a-zA-Z]|\{\{)", re.MULTILINE | re.DOTALL) def conv(match): line = match.group(1) line += match.group(4) line += ", " line += match.group(2) return line line = sys.stdin.read() off = 0 for match in re.finditer(rep, line): sys.stdout.write(line[off:match.start()]) sys.stdout.write(conv(match)) off = match.end() sys.stdout.write(line[off:]) llvm-svn: 232184
2015-03-14 02:20:45 +08:00
tail call void @foo2(%struct.S1* byval getelementptr inbounds (%struct.S2, %struct.S2* @s2, i32 0, i32 1)) nounwind
[mips] Make unalignedload.ll test stricter and easier to modify for MIPS32r6/MIPS64r6 Summary: * Split into two functions, one to test each struct. * R0 and R2 must be defined by an lw with a %got reference to the correct symbol. * Test for $4 (first argument) where appropriate instead of accepting any register. * Test that the two lbu's are correctly combined into $4 Depends on D3844 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3845 llvm-svn: 209424
2014-05-22 19:55:04 +08:00
ret void
}
define void @bar2() nounwind {
entry:
; ALL-LABEL: bar2:
[mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6 Summary: Instead the system is required to provide some means of handling unaligned load/store without special instructions. Options include full hardware support, full trap-and-emulate, and hybrids such as hardware support within a cache line and trap-and-emulate for multi-line accesses. MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to assume that unaligned accesses are 'fast' on the basis that I expect few hardware implementations will opt for pure-software handling of unaligned accesses. The ones that do handle it purely in software can override this. mips64-load-store-left-right.ll has been merged into load-store-left-right.ll The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has been fixed and the variables renamed to clarify the units they hold. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3872 llvm-svn: 209512
2014-05-23 21:18:02 +08:00
; ALL-DAG: lw $[[R2:[0-9]+]], %got(s4)(
[mips] Make unalignedload.ll test stricter and easier to modify for MIPS32r6/MIPS64r6 Summary: * Split into two functions, one to test each struct. * R0 and R2 must be defined by an lw with a %got reference to the correct symbol. * Test for $4 (first argument) where appropriate instead of accepting any register. * Test that the two lbu's are correctly combined into $4 Depends on D3844 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3845 llvm-svn: 209424
2014-05-22 19:55:04 +08:00
[mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6 Summary: Instead the system is required to provide some means of handling unaligned load/store without special instructions. Options include full hardware support, full trap-and-emulate, and hybrids such as hardware support within a cache line and trap-and-emulate for multi-line accesses. MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to assume that unaligned accesses are 'fast' on the basis that I expect few hardware implementations will opt for pure-software handling of unaligned accesses. The ones that do handle it purely in software can override this. mips64-load-store-left-right.ll has been merged into load-store-left-right.ll The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has been fixed and the variables renamed to clarify the units they hold. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3872 llvm-svn: 209512
2014-05-23 21:18:02 +08:00
; MIPS32-EL-DAG: lwl $[[R1:4]], 3($[[R2]])
; MIPS32-EL-DAG: lwr $[[R1]], 0($[[R2]])
; MIPS32-EL-DAG: lbu $[[T0:[0-9]+]], 4($[[R2]])
; MIPS32-EL-DAG: lbu $[[T1:[0-9]+]], 5($[[R2]])
; MIPS32-EL-DAG: lbu $[[T2:[0-9]+]], 6($[[R2]])
; MIPS32-EL-DAG: sll $[[T3:[0-9]+]], $[[T1]], 8
; MIPS32-EL-DAG: or $[[T4:[0-9]+]], $[[T3]], $[[T0]]
; MIPS32-EL-DAG: sll $[[T5:[0-9]+]], $[[T2]], 16
; MIPS32-EL-DAG: or $5, $[[T4]], $[[T5]]
Use subword loads instead of a 4-byte load when the size of a structure (or a piece of it) that is being passed by value is smaller than a word. llvm-svn: 138007
2011-08-19 07:39:37 +08:00
[mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6 Summary: Instead the system is required to provide some means of handling unaligned load/store without special instructions. Options include full hardware support, full trap-and-emulate, and hybrids such as hardware support within a cache line and trap-and-emulate for multi-line accesses. MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to assume that unaligned accesses are 'fast' on the basis that I expect few hardware implementations will opt for pure-software handling of unaligned accesses. The ones that do handle it purely in software can override this. mips64-load-store-left-right.ll has been merged into load-store-left-right.ll The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has been fixed and the variables renamed to clarify the units they hold. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3872 llvm-svn: 209512
2014-05-23 21:18:02 +08:00
; MIPS32-EB-DAG: lwl $[[R1:4]], 0($[[R2]])
; MIPS32-EB-DAG: lwr $[[R1]], 3($[[R2]])
; MIPS32-EB-DAG: lbu $[[T0:[0-9]+]], 4($[[R2]])
; MIPS32-EB-DAG: lbu $[[T1:[0-9]+]], 5($[[R2]])
; MIPS32-EB-DAG: lbu $[[T2:[0-9]+]], 6($[[R2]])
; MIPS32-EB-DAG: sll $[[T3:[0-9]+]], $[[T0]], 8
; MIPS32-EB-DAG: or $[[T4:[0-9]+]], $[[T3]], $[[T1]]
; MIPS32-EB-DAG: sll $[[T5:[0-9]+]], $[[T4]], 16
; MIPS32-EB-DAG: sll $[[T6:[0-9]+]], $[[T2]], 8
; MIPS32-EB-DAG: or $5, $[[T5]], $[[T6]]
; FIXME: We should be able to do better than this using lhu
; MIPS32R6-EL-DAG: lw $4, 0($[[R2]])
; MIPS32R6-EL-DAG: lhu $[[T0:[0-9]+]], 4($[[R2]])
; MIPS32R6-EL-DAG: lbu $[[T1:[0-9]+]], 6($[[R2]])
; MIPS32R6-EL-DAG: sll $[[T2:[0-9]+]], $[[T1]], 16
; MIPS32R6-EL-DAG: or $5, $[[T0]], $[[T2]]
; FIXME: We should be able to do better than this using lhu
; MIPS32R6-EB-DAG: lw $4, 0($[[R2]])
; MIPS32R6-EB-DAG: lhu $[[T0:[0-9]+]], 4($[[R2]])
; MIPS32R6-EB-DAG: lbu $[[T1:[0-9]+]], 6($[[R2]])
; MIPS32R6-EB-DAG: sll $[[T2:[0-9]+]], $[[T0]], 16
; MIPS32R6-EB-DAG: sll $[[T3:[0-9]+]], $[[T1]], 8
; MIPS32R6-EB-DAG: or $5, $[[T2]], $[[T3]]
Define unaligned load and store. llvm-svn: 137515
2011-08-13 05:30:06 +08:00
Use subword loads instead of a 4-byte load when the size of a structure (or a piece of it) that is being passed by value is smaller than a word. llvm-svn: 138007
2011-08-19 07:39:37 +08:00
tail call void @foo4(%struct.S4* byval @s4) nounwind
Define unaligned load and store. llvm-svn: 137515
2011-08-13 05:30:06 +08:00
ret void
}
declare void @foo2(%struct.S1* byval)
Use subword loads instead of a 4-byte load when the size of a structure (or a piece of it) that is being passed by value is smaller than a word. llvm-svn: 138007
2011-08-19 07:39:37 +08:00
declare void @foo4(%struct.S4* byval)