maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/Mips/octeon.ll

158 lines
3.7 KiB
LLVM
Raw Normal View History

[mips] Add registers and ALL check prefix to octeon test case. No functional change. Reviewed by D. Sanders llvm-svn: 226574
2015-01-21 00:14:02 +08:00
; RUN: llc -O1 < %s -march=mips64 -mcpu=octeon | FileCheck %s -check-prefix=ALL -check-prefix=OCTEON
; RUN: llc -O1 < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64
[MIPS] Add cpu octeon and some instructions The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337
2014-03-20 19:51:58 +08:00
[mips] Add more Octeon cnMips instructions Adds the instructions ext/ext32/cins/cins32. It also changes pop/dpop to accept the two operand version and adds a simple pattern to generate baddu. Tests for the two operand versions (including baddu/dmul/dpop/pop) and the code generation pattern for baddu are included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205449
2014-04-03 02:40:43 +08:00
define i64 @addi64(i64 %a, i64 %b) nounwind {
entry:
[mips] Add registers and ALL check prefix to octeon test case. No functional change. Reviewed by D. Sanders llvm-svn: 226574
2015-01-21 00:14:02 +08:00
; ALL-LABEL: addi64:
[mips] Add more Octeon cnMips instructions Adds the instructions ext/ext32/cins/cins32. It also changes pop/dpop to accept the two operand version and adds a simple pattern to generate baddu. Tests for the two operand versions (including baddu/dmul/dpop/pop) and the code generation pattern for baddu are included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205449
2014-04-03 02:40:43 +08:00
; OCTEON: jr $ra
; OCTEON: baddu $2, $4, $5
[mips] Add registers and ALL check prefix to octeon test case. No functional change. Reviewed by D. Sanders llvm-svn: 226574
2015-01-21 00:14:02 +08:00
; MIPS64: daddu $[[T0:[0-9]+]], $4, $5
; MIPS64: jr $ra
; MIPS64: andi $2, $[[T0]], 255
[mips] Add more Octeon cnMips instructions Adds the instructions ext/ext32/cins/cins32. It also changes pop/dpop to accept the two operand version and adds a simple pattern to generate baddu. Tests for the two operand versions (including baddu/dmul/dpop/pop) and the code generation pattern for baddu are included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205449
2014-04-03 02:40:43 +08:00
%add = add i64 %a, %b
%and = and i64 %add, 255
ret i64 %and
}
[MIPS] Add cpu octeon and some instructions The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337
2014-03-20 19:51:58 +08:00
define i64 @mul(i64 %a, i64 %b) nounwind {
entry:
[mips] Add registers and ALL check prefix to octeon test case. No functional change. Reviewed by D. Sanders llvm-svn: 226574
2015-01-21 00:14:02 +08:00
; ALL-LABEL: mul:
[MIPS] Add cpu octeon and some instructions The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337
2014-03-20 19:51:58 +08:00
; OCTEON: jr $ra
; OCTEON: dmul $2, $4, $5
[mips] Add registers and ALL check prefix to octeon test case. No functional change. Reviewed by D. Sanders llvm-svn: 226574
2015-01-21 00:14:02 +08:00
; MIPS64: dmult $4, $5
; MIPS64: jr $ra
; MIPS64: mflo $2
[MIPS] Add cpu octeon and some instructions The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337
2014-03-20 19:51:58 +08:00
%res = mul i64 %a, %b
ret i64 %res
}
[mips] Refine octeon instructions seq/seqi/sne/snei This commit refines the pattern for the octeon seq/seqi/sne/snei instructions. The target register is set to 0 or 1 according to the result of the comparison. In C, this is something like rd = (unsigned long)(rs == rt) This commit adds a zext to bring the result to i64. With this change the instruction is selected for this type of code. (gcc produces the same code for the above C code.) llvm-svn: 225968
2015-01-14 18:19:09 +08:00
define i64 @cmpeq(i64 %a, i64 %b) nounwind {
entry:
[mips] Add registers and ALL check prefix to octeon test case. No functional change. Reviewed by D. Sanders llvm-svn: 226574
2015-01-21 00:14:02 +08:00
; ALL-LABEL: cmpeq:
[mips] Refine octeon instructions seq/seqi/sne/snei This commit refines the pattern for the octeon seq/seqi/sne/snei instructions. The target register is set to 0 or 1 according to the result of the comparison. In C, this is something like rd = (unsigned long)(rs == rt) This commit adds a zext to bring the result to i64. With this change the instruction is selected for this type of code. (gcc produces the same code for the above C code.) llvm-svn: 225968
2015-01-14 18:19:09 +08:00
; OCTEON: jr $ra
; OCTEON: seq $2, $4, $5
[mips] Add registers and ALL check prefix to octeon test case. No functional change. Reviewed by D. Sanders llvm-svn: 226574
2015-01-21 00:14:02 +08:00
; MIPS64: xor $[[T0:[0-9]+]], $4, $5
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
; MIPS64: sltiu $[[T1:[0-9]+]], $[[T0]], 1
; MIPS64: dsll $[[T2:[0-9]+]], $[[T1]], 32
[mips] Refine octeon instructions seq/seqi/sne/snei This commit refines the pattern for the octeon seq/seqi/sne/snei instructions. The target register is set to 0 or 1 according to the result of the comparison. In C, this is something like rd = (unsigned long)(rs == rt) This commit adds a zext to bring the result to i64. With this change the instruction is selected for this type of code. (gcc produces the same code for the above C code.) llvm-svn: 225968
2015-01-14 18:19:09 +08:00
; MIPS64: jr $ra
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
; MIPS64: dsrl $2, $[[T2]], 32
[mips] Refine octeon instructions seq/seqi/sne/snei This commit refines the pattern for the octeon seq/seqi/sne/snei instructions. The target register is set to 0 or 1 according to the result of the comparison. In C, this is something like rd = (unsigned long)(rs == rt) This commit adds a zext to bring the result to i64. With this change the instruction is selected for this type of code. (gcc produces the same code for the above C code.) llvm-svn: 225968
2015-01-14 18:19:09 +08:00
%res = icmp eq i64 %a, %b
%res2 = zext i1 %res to i64
ret i64 %res2
}
define i64 @cmpeqi(i64 %a) nounwind {
entry:
[mips] Add registers and ALL check prefix to octeon test case. No functional change. Reviewed by D. Sanders llvm-svn: 226574
2015-01-21 00:14:02 +08:00
; ALL-LABEL: cmpeqi:
[mips] Refine octeon instructions seq/seqi/sne/snei This commit refines the pattern for the octeon seq/seqi/sne/snei instructions. The target register is set to 0 or 1 according to the result of the comparison. In C, this is something like rd = (unsigned long)(rs == rt) This commit adds a zext to bring the result to i64. With this change the instruction is selected for this type of code. (gcc produces the same code for the above C code.) llvm-svn: 225968
2015-01-14 18:19:09 +08:00
; OCTEON: jr $ra
; OCTEON: seqi $2, $4, 42
[mips] Add registers and ALL check prefix to octeon test case. No functional change. Reviewed by D. Sanders llvm-svn: 226574
2015-01-21 00:14:02 +08:00
; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 42
; MIPS64: xor $[[T1:[0-9]+]], $4, $[[T0]]
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
; MIPS64: sltiu $[[T2:[0-9]+]], $[[T1]], 1
; MIPS64: dsll $[[T3:[0-9]+]], $[[T2]], 32
[mips] Refine octeon instructions seq/seqi/sne/snei This commit refines the pattern for the octeon seq/seqi/sne/snei instructions. The target register is set to 0 or 1 according to the result of the comparison. In C, this is something like rd = (unsigned long)(rs == rt) This commit adds a zext to bring the result to i64. With this change the instruction is selected for this type of code. (gcc produces the same code for the above C code.) llvm-svn: 225968
2015-01-14 18:19:09 +08:00
; MIPS64: jr $ra
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
; MIPS64: dsrl $2, $[[T3]], 32
[mips] Refine octeon instructions seq/seqi/sne/snei This commit refines the pattern for the octeon seq/seqi/sne/snei instructions. The target register is set to 0 or 1 according to the result of the comparison. In C, this is something like rd = (unsigned long)(rs == rt) This commit adds a zext to bring the result to i64. With this change the instruction is selected for this type of code. (gcc produces the same code for the above C code.) llvm-svn: 225968
2015-01-14 18:19:09 +08:00
%res = icmp eq i64 %a, 42
%res2 = zext i1 %res to i64
ret i64 %res2
}
define i64 @cmpne(i64 %a, i64 %b) nounwind {
entry:
[mips] Add registers and ALL check prefix to octeon test case. No functional change. Reviewed by D. Sanders llvm-svn: 226574
2015-01-21 00:14:02 +08:00
; ALL-LABEL: cmpne:
[mips] Refine octeon instructions seq/seqi/sne/snei This commit refines the pattern for the octeon seq/seqi/sne/snei instructions. The target register is set to 0 or 1 according to the result of the comparison. In C, this is something like rd = (unsigned long)(rs == rt) This commit adds a zext to bring the result to i64. With this change the instruction is selected for this type of code. (gcc produces the same code for the above C code.) llvm-svn: 225968
2015-01-14 18:19:09 +08:00
; OCTEON: jr $ra
; OCTEON: sne $2, $4, $5
[mips] Add registers and ALL check prefix to octeon test case. No functional change. Reviewed by D. Sanders llvm-svn: 226574
2015-01-21 00:14:02 +08:00
; MIPS64: xor $[[T0:[0-9]+]], $4, $5
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
; MIPS64: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
; MIPS64: dsll $[[T2:[0-9]+]], $[[T1]], 32
[mips] Refine octeon instructions seq/seqi/sne/snei This commit refines the pattern for the octeon seq/seqi/sne/snei instructions. The target register is set to 0 or 1 according to the result of the comparison. In C, this is something like rd = (unsigned long)(rs == rt) This commit adds a zext to bring the result to i64. With this change the instruction is selected for this type of code. (gcc produces the same code for the above C code.) llvm-svn: 225968
2015-01-14 18:19:09 +08:00
; MIPS64: jr $ra
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
; MIPS64: dsrl $2, $[[T2]], 32
[mips] Refine octeon instructions seq/seqi/sne/snei This commit refines the pattern for the octeon seq/seqi/sne/snei instructions. The target register is set to 0 or 1 according to the result of the comparison. In C, this is something like rd = (unsigned long)(rs == rt) This commit adds a zext to bring the result to i64. With this change the instruction is selected for this type of code. (gcc produces the same code for the above C code.) llvm-svn: 225968
2015-01-14 18:19:09 +08:00
%res = icmp ne i64 %a, %b
%res2 = zext i1 %res to i64
ret i64 %res2
}
define i64 @cmpnei(i64 %a) nounwind {
entry:
[mips] Add registers and ALL check prefix to octeon test case. No functional change. Reviewed by D. Sanders llvm-svn: 226574
2015-01-21 00:14:02 +08:00
; ALL-LABEL: cmpnei:
[mips] Refine octeon instructions seq/seqi/sne/snei This commit refines the pattern for the octeon seq/seqi/sne/snei instructions. The target register is set to 0 or 1 according to the result of the comparison. In C, this is something like rd = (unsigned long)(rs == rt) This commit adds a zext to bring the result to i64. With this change the instruction is selected for this type of code. (gcc produces the same code for the above C code.) llvm-svn: 225968
2015-01-14 18:19:09 +08:00
; OCTEON: jr $ra
; OCTEON: snei $2, $4, 42
[mips] Add registers and ALL check prefix to octeon test case. No functional change. Reviewed by D. Sanders llvm-svn: 226574
2015-01-21 00:14:02 +08:00
; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 42
; MIPS64: xor $[[T1:[0-9]+]], $4, $[[T0]]
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
; MIPS64: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
; MIPS64: dsll $[[T3:[0-9]+]], $[[T2]], 32
[mips] Refine octeon instructions seq/seqi/sne/snei This commit refines the pattern for the octeon seq/seqi/sne/snei instructions. The target register is set to 0 or 1 according to the result of the comparison. In C, this is something like rd = (unsigned long)(rs == rt) This commit adds a zext to bring the result to i64. With this change the instruction is selected for this type of code. (gcc produces the same code for the above C code.) llvm-svn: 225968
2015-01-14 18:19:09 +08:00
; MIPS64: jr $ra
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
; MIPS64: dsrl $2, $[[T3]], 32
[mips] Refine octeon instructions seq/seqi/sne/snei This commit refines the pattern for the octeon seq/seqi/sne/snei instructions. The target register is set to 0 or 1 according to the result of the comparison. In C, this is something like rd = (unsigned long)(rs == rt) This commit adds a zext to bring the result to i64. With this change the instruction is selected for this type of code. (gcc produces the same code for the above C code.) llvm-svn: 225968
2015-01-14 18:19:09 +08:00
%res = icmp ne i64 %a, 42
%res2 = zext i1 %res to i64
ret i64 %res2
}
[mips] Add octeon branch instructions bbit0/bbit032/bbit1/bbit132 This commits adds the octeon branch instructions bbit0/bbit032/bbit1/bbit132. It also includes patterns for instruction selection and test cases. Reviewed by D. Sanders llvm-svn: 226573
2015-01-21 00:10:51 +08:00
define i64 @bbit0(i64 %a) nounwind {
entry:
[mips] Add registers and ALL check prefix to octeon test case. No functional change. Reviewed by D. Sanders llvm-svn: 226574
2015-01-21 00:14:02 +08:00
; ALL-LABEL: bbit0:
Revert r237789 - [mips] The naming convention for private labels is ABI dependant. It works, but I've noticed that I missed several callers of createMCAsmInfo() and many don't have a TargetMachine to provide. llvm-svn: 237792
2015-05-20 22:18:59 +08:00
; OCTEON: bbit0 $4, 3, $[[BB0:BB[0-9_]+]]
[mips] Add octeon branch instructions bbit0/bbit032/bbit1/bbit132 This commits adds the octeon branch instructions bbit0/bbit032/bbit1/bbit132. It also includes patterns for instruction selection and test cases. Reviewed by D. Sanders llvm-svn: 226573
2015-01-21 00:10:51 +08:00
; MIPS64: andi $[[T0:[0-9]+]], $4, 8
Revert r237789 - [mips] The naming convention for private labels is ABI dependant. It works, but I've noticed that I missed several callers of createMCAsmInfo() and many don't have a TargetMachine to provide. llvm-svn: 237792
2015-05-20 22:18:59 +08:00
; MIPS64: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
[mips] Add octeon branch instructions bbit0/bbit032/bbit1/bbit132 This commits adds the octeon branch instructions bbit0/bbit032/bbit1/bbit132. It also includes patterns for instruction selection and test cases. Reviewed by D. Sanders llvm-svn: 226573
2015-01-21 00:10:51 +08:00
%bit = and i64 %a, 8
%res = icmp eq i64 %bit, 0
br i1 %res, label %endif, label %if
if:
ret i64 48
endif:
ret i64 12
}
define i64 @bbit032(i64 %a) nounwind {
entry:
[mips] Add registers and ALL check prefix to octeon test case. No functional change. Reviewed by D. Sanders llvm-svn: 226574
2015-01-21 00:14:02 +08:00
; ALL-LABEL: bbit032:
Revert r237789 - [mips] The naming convention for private labels is ABI dependant. It works, but I've noticed that I missed several callers of createMCAsmInfo() and many don't have a TargetMachine to provide. llvm-svn: 237792
2015-05-20 22:18:59 +08:00
; OCTEON: bbit032 $4, 3, $[[BB0:BB[0-9_]+]]
[mips] Add octeon branch instructions bbit0/bbit032/bbit1/bbit132 This commits adds the octeon branch instructions bbit0/bbit032/bbit1/bbit132. It also includes patterns for instruction selection and test cases. Reviewed by D. Sanders llvm-svn: 226573
2015-01-21 00:10:51 +08:00
; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 1
; MIPS64: dsll $[[T1:[0-9]+]], $[[T0]], 35
; MIPS64: and $[[T2:[0-9]+]], $4, $[[T1]]
Revert r237789 - [mips] The naming convention for private labels is ABI dependant. It works, but I've noticed that I missed several callers of createMCAsmInfo() and many don't have a TargetMachine to provide. llvm-svn: 237792
2015-05-20 22:18:59 +08:00
; MIPS64: bnez $[[T2]], $[[BB0:BB[0-9_]+]]
[mips] Add octeon branch instructions bbit0/bbit032/bbit1/bbit132 This commits adds the octeon branch instructions bbit0/bbit032/bbit1/bbit132. It also includes patterns for instruction selection and test cases. Reviewed by D. Sanders llvm-svn: 226573
2015-01-21 00:10:51 +08:00
%bit = and i64 %a, 34359738368
%res = icmp eq i64 %bit, 0
br i1 %res, label %endif, label %if
if:
ret i64 48
endif:
ret i64 12
}
define i64 @bbit1(i64 %a) nounwind {
entry:
[mips] Add registers and ALL check prefix to octeon test case. No functional change. Reviewed by D. Sanders llvm-svn: 226574
2015-01-21 00:14:02 +08:00
; ALL-LABEL: bbit1:
Revert r237789 - [mips] The naming convention for private labels is ABI dependant. It works, but I've noticed that I missed several callers of createMCAsmInfo() and many don't have a TargetMachine to provide. llvm-svn: 237792
2015-05-20 22:18:59 +08:00
; OCTEON: bbit1 $4, 3, $[[BB0:BB[0-9_]+]]
[mips] Add octeon branch instructions bbit0/bbit032/bbit1/bbit132 This commits adds the octeon branch instructions bbit0/bbit032/bbit1/bbit132. It also includes patterns for instruction selection and test cases. Reviewed by D. Sanders llvm-svn: 226573
2015-01-21 00:10:51 +08:00
; MIPS64: andi $[[T0:[0-9]+]], $4, 8
Revert r237789 - [mips] The naming convention for private labels is ABI dependant. It works, but I've noticed that I missed several callers of createMCAsmInfo() and many don't have a TargetMachine to provide. llvm-svn: 237792
2015-05-20 22:18:59 +08:00
; MIPS64: beqz $[[T0]], $[[BB0:BB[0-9_]+]]
[mips] Add octeon branch instructions bbit0/bbit032/bbit1/bbit132 This commits adds the octeon branch instructions bbit0/bbit032/bbit1/bbit132. It also includes patterns for instruction selection and test cases. Reviewed by D. Sanders llvm-svn: 226573
2015-01-21 00:10:51 +08:00
%bit = and i64 %a, 8
%res = icmp ne i64 %bit, 0
br i1 %res, label %endif, label %if
if:
ret i64 48
endif:
ret i64 12
}
define i64 @bbit132(i64 %a) nounwind {
entry:
[mips] Add registers and ALL check prefix to octeon test case. No functional change. Reviewed by D. Sanders llvm-svn: 226574
2015-01-21 00:14:02 +08:00
; ALL-LABEL: bbit132:
Revert r237789 - [mips] The naming convention for private labels is ABI dependant. It works, but I've noticed that I missed several callers of createMCAsmInfo() and many don't have a TargetMachine to provide. llvm-svn: 237792
2015-05-20 22:18:59 +08:00
; OCTEON: bbit132 $4, 3, $[[BB0:BB[0-9_]+]]
[mips] Add octeon branch instructions bbit0/bbit032/bbit1/bbit132 This commits adds the octeon branch instructions bbit0/bbit032/bbit1/bbit132. It also includes patterns for instruction selection and test cases. Reviewed by D. Sanders llvm-svn: 226573
2015-01-21 00:10:51 +08:00
; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 1
; MIPS64: dsll $[[T1:[0-9]+]], $[[T0]], 35
; MIPS64: and $[[T2:[0-9]+]], $4, $[[T1]]
Revert r237789 - [mips] The naming convention for private labels is ABI dependant. It works, but I've noticed that I missed several callers of createMCAsmInfo() and many don't have a TargetMachine to provide. llvm-svn: 237792
2015-05-20 22:18:59 +08:00
; MIPS64: beqz $[[T2]], $[[BB0:BB[0-9_]+]]
[mips] Add octeon branch instructions bbit0/bbit032/bbit1/bbit132 This commits adds the octeon branch instructions bbit0/bbit032/bbit1/bbit132. It also includes patterns for instruction selection and test cases. Reviewed by D. Sanders llvm-svn: 226573
2015-01-21 00:10:51 +08:00
%bit = and i64 %a, 34359738368
%res = icmp ne i64 %bit, 0
br i1 %res, label %endif, label %if
if:
ret i64 48
endif:
ret i64 12
}