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llvm-project/llvm/test/CodeGen/Mips/no-odd-spreg-msa.ll

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[mips][ias] Explicitly disable IAS on tests that depend on not assembling. Summary: no-odd-spreg-msa.ll: This test deliberately uses an odd-numbered register in inline assembly and expects the compiler to insert a move to an even-numbered register. inlineasm-operand-code.ll and inlineasm_constraint.ll: Checks for IAS's output will be added once a matcher bug is resolved. This bug causes the canonical output emitted by IAS to be incorrect for uimm16 constants with the MSB set. We will still need the non-IAS checks at this point since these tests primarily test formatting of operands. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D14705 llvm-svn: 254148
2015-11-26 19:23:03 +08:00
; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+fp64,+msa,-nooddspreg \
[mips] Make Static a default relocation model for MIPS codegen This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 llvm-svn: 265949
2016-04-11 23:24:23 +08:00
; RUN: -no-integrated-as -relocation-model=pic < %s | FileCheck %s -check-prefix=ALL \
[mips][ias] Explicitly disable IAS on tests that depend on not assembling. Summary: no-odd-spreg-msa.ll: This test deliberately uses an odd-numbered register in inline assembly and expects the compiler to insert a move to an even-numbered register. inlineasm-operand-code.ll and inlineasm_constraint.ll: Checks for IAS's output will be added once a matcher bug is resolved. This bug causes the canonical output emitted by IAS to be incorrect for uimm16 constants with the MSB set. We will still need the non-IAS checks at this point since these tests primarily test formatting of operands. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D14705 llvm-svn: 254148
2015-11-26 19:23:03 +08:00
; RUN: -check-prefix=ODDSPREG
; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+fp64,+msa,+nooddspreg \
[mips] Make Static a default relocation model for MIPS codegen This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 llvm-svn: 265949
2016-04-11 23:24:23 +08:00
; RUN: -no-integrated-as -relocation-model=pic < %s | FileCheck %s -check-prefix=ALL \
[mips][ias] Explicitly disable IAS on tests that depend on not assembling. Summary: no-odd-spreg-msa.ll: This test deliberately uses an odd-numbered register in inline assembly and expects the compiler to insert a move to an even-numbered register. inlineasm-operand-code.ll and inlineasm_constraint.ll: Checks for IAS's output will be added once a matcher bug is resolved. This bug causes the canonical output emitted by IAS to be incorrect for uimm16 constants with the MSB set. We will still need the non-IAS checks at this point since these tests primarily test formatting of operands. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D14705 llvm-svn: 254148
2015-11-26 19:23:03 +08:00
; RUN: -check-prefix=NOODDSPREG
[mips] Honour -mno-odd-spreg for vector insert/extract when MSA is enabled. Summary: -mno-odd-spreg prohibits the use of odd-numbered single-precision floating point registers. However, vector insert/extract was still using them when manipulating the subregisters of an MSA register. Fixed this by ensuring that insertion/extraction is only performed on even-numbered vector registers when -mno-odd-spreg is given. Reviewers: vmedic, sstankovic Reviewed By: sstankovic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7672 llvm-svn: 230235
2015-02-24 01:22:16 +08:00
@v4f32 = global <4 x float> zeroinitializer
define void @msa_insert_0(float %a) {
entry:
; Force the float into an odd-numbered register using named registers and
; load the vector.
%b = call float asm sideeffect "mov.s $0, $1", "={$f13},{$f12}" (float %a)
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load volatile <4 x float>, <4 x float>* @v4f32
[mips] Honour -mno-odd-spreg for vector insert/extract when MSA is enabled. Summary: -mno-odd-spreg prohibits the use of odd-numbered single-precision floating point registers. However, vector insert/extract was still using them when manipulating the subregisters of an MSA register. Fixed this by ensuring that insertion/extraction is only performed on even-numbered vector registers when -mno-odd-spreg is given. Reviewers: vmedic, sstankovic Reviewed By: sstankovic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7672 llvm-svn: 230235
2015-02-24 01:22:16 +08:00
; Clobber all except $f12/$w12 and $f13
;
; The intention is that if odd single precision registers are permitted, the
; allocator will choose $f12/$w12 for the vector and $f13 for the float to
; avoid the spill/reload.
;
; On the other hand, if odd single precision registers are not permitted, it
; must copy $f13 to an even-numbered register before inserting into the
; vector.
[mips][ias] Replace anchor comments with anchor instructions in tests. Summary: This is because IAS will delete the comments. NFC at the moment but it will prevent a failure once IAS is the default. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14704 llvm-svn: 254147
2015-11-26 18:26:18 +08:00
call void asm sideeffect "teqi $$zero, 1", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
[mips] Honour -mno-odd-spreg for vector insert/extract when MSA is enabled. Summary: -mno-odd-spreg prohibits the use of odd-numbered single-precision floating point registers. However, vector insert/extract was still using them when manipulating the subregisters of an MSA register. Fixed this by ensuring that insertion/extraction is only performed on even-numbered vector registers when -mno-odd-spreg is given. Reviewers: vmedic, sstankovic Reviewed By: sstankovic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7672 llvm-svn: 230235
2015-02-24 01:22:16 +08:00
%1 = insertelement <4 x float> %0, float %b, i32 0
store <4 x float> %1, <4 x float>* @v4f32
ret void
}
; ALL-LABEL: msa_insert_0:
; ALL: mov.s $f13, $f12
; ALL: lw $[[R0:[0-9]+]], %got(v4f32)(
; ALL: ld.w $w[[W0:[0-9]+]], 0($[[R0]])
; NOODDSPREG: mov.s $f[[F0:[0-9]+]], $f13
; NOODDSPREG: insve.w $w[[W0]][0], $w[[F0]][0]
; ODDSPREG: insve.w $w[[W0]][0], $w13[0]
[mips][ias] Replace anchor comments with anchor instructions in tests. Summary: This is because IAS will delete the comments. NFC at the moment but it will prevent a failure once IAS is the default. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14704 llvm-svn: 254147
2015-11-26 18:26:18 +08:00
; ALL: teqi $zero, 1
[mips] Honour -mno-odd-spreg for vector insert/extract when MSA is enabled. Summary: -mno-odd-spreg prohibits the use of odd-numbered single-precision floating point registers. However, vector insert/extract was still using them when manipulating the subregisters of an MSA register. Fixed this by ensuring that insertion/extraction is only performed on even-numbered vector registers when -mno-odd-spreg is given. Reviewers: vmedic, sstankovic Reviewed By: sstankovic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7672 llvm-svn: 230235
2015-02-24 01:22:16 +08:00
; ALL-NOT: sdc1
; ALL-NOT: ldc1
; ALL: st.w $w[[W0]], 0($[[R0]])
define void @msa_insert_1(float %a) {
entry:
; Force the float into an odd-numbered register using named registers and
; load the vector.
%b = call float asm sideeffect "mov.s $0, $1", "={$f13},{$f12}" (float %a)
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load volatile <4 x float>, <4 x float>* @v4f32
[mips] Honour -mno-odd-spreg for vector insert/extract when MSA is enabled. Summary: -mno-odd-spreg prohibits the use of odd-numbered single-precision floating point registers. However, vector insert/extract was still using them when manipulating the subregisters of an MSA register. Fixed this by ensuring that insertion/extraction is only performed on even-numbered vector registers when -mno-odd-spreg is given. Reviewers: vmedic, sstankovic Reviewed By: sstankovic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7672 llvm-svn: 230235
2015-02-24 01:22:16 +08:00
; Clobber all except $f12/$w12 and $f13
;
; The intention is that if odd single precision registers are permitted, the
; allocator will choose $f12/$w12 for the vector and $f13 for the float to
; avoid the spill/reload.
;
; On the other hand, if odd single precision registers are not permitted, it
; must copy $f13 to an even-numbered register before inserting into the
; vector.
[mips][ias] Replace anchor comments with anchor instructions in tests. Summary: This is because IAS will delete the comments. NFC at the moment but it will prevent a failure once IAS is the default. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14704 llvm-svn: 254147
2015-11-26 18:26:18 +08:00
call void asm sideeffect "teqi $$zero, 1", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
[mips] Honour -mno-odd-spreg for vector insert/extract when MSA is enabled. Summary: -mno-odd-spreg prohibits the use of odd-numbered single-precision floating point registers. However, vector insert/extract was still using them when manipulating the subregisters of an MSA register. Fixed this by ensuring that insertion/extraction is only performed on even-numbered vector registers when -mno-odd-spreg is given. Reviewers: vmedic, sstankovic Reviewed By: sstankovic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7672 llvm-svn: 230235
2015-02-24 01:22:16 +08:00
%1 = insertelement <4 x float> %0, float %b, i32 1
store <4 x float> %1, <4 x float>* @v4f32
ret void
}
; ALL-LABEL: msa_insert_1:
; ALL: mov.s $f13, $f12
; ALL: lw $[[R0:[0-9]+]], %got(v4f32)(
; ALL: ld.w $w[[W0:[0-9]+]], 0($[[R0]])
; NOODDSPREG: mov.s $f[[F0:[0-9]+]], $f13
; NOODDSPREG: insve.w $w[[W0]][1], $w[[F0]][0]
; ODDSPREG: insve.w $w[[W0]][1], $w13[0]
[mips][ias] Replace anchor comments with anchor instructions in tests. Summary: This is because IAS will delete the comments. NFC at the moment but it will prevent a failure once IAS is the default. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14704 llvm-svn: 254147
2015-11-26 18:26:18 +08:00
; ALL: teqi $zero, 1
[mips] Honour -mno-odd-spreg for vector insert/extract when MSA is enabled. Summary: -mno-odd-spreg prohibits the use of odd-numbered single-precision floating point registers. However, vector insert/extract was still using them when manipulating the subregisters of an MSA register. Fixed this by ensuring that insertion/extraction is only performed on even-numbered vector registers when -mno-odd-spreg is given. Reviewers: vmedic, sstankovic Reviewed By: sstankovic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7672 llvm-svn: 230235
2015-02-24 01:22:16 +08:00
; ALL-NOT: sdc1
; ALL-NOT: ldc1
; ALL: st.w $w[[W0]], 0($[[R0]])
define float @msa_extract_0() {
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load volatile <4 x float>, <4 x float>* @v4f32
[mips] Honour -mno-odd-spreg for vector insert/extract when MSA is enabled. Summary: -mno-odd-spreg prohibits the use of odd-numbered single-precision floating point registers. However, vector insert/extract was still using them when manipulating the subregisters of an MSA register. Fixed this by ensuring that insertion/extraction is only performed on even-numbered vector registers when -mno-odd-spreg is given. Reviewers: vmedic, sstankovic Reviewed By: sstankovic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7672 llvm-svn: 230235
2015-02-24 01:22:16 +08:00
%1 = call <4 x float> asm sideeffect "move.v $0, $1", "={$w13},{$w12}" (<4 x float> %0)
; Clobber all except $f12, and $f13
;
; The intention is that if odd single precision registers are permitted, the
; allocator will choose $f13/$w13 for the vector since that saves on moves.
;
; On the other hand, if odd single precision registers are not permitted, it
; must move it to $f12/$w12.
[mips][ias] Replace anchor comments with anchor instructions in tests. Summary: This is because IAS will delete the comments. NFC at the moment but it will prevent a failure once IAS is the default. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14704 llvm-svn: 254147
2015-11-26 18:26:18 +08:00
call void asm sideeffect "teqi $$zero, 1", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
[mips] Honour -mno-odd-spreg for vector insert/extract when MSA is enabled. Summary: -mno-odd-spreg prohibits the use of odd-numbered single-precision floating point registers. However, vector insert/extract was still using them when manipulating the subregisters of an MSA register. Fixed this by ensuring that insertion/extraction is only performed on even-numbered vector registers when -mno-odd-spreg is given. Reviewers: vmedic, sstankovic Reviewed By: sstankovic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7672 llvm-svn: 230235
2015-02-24 01:22:16 +08:00
%2 = extractelement <4 x float> %1, i32 0
ret float %2
}
; ALL-LABEL: msa_extract_0:
; ALL: lw $[[R0:[0-9]+]], %got(v4f32)(
; ALL: ld.w $w12, 0($[[R0]])
; ALL: move.v $w[[W0:13]], $w12
; NOODDSPREG: move.v $w[[W0:12]], $w13
[mips][ias] Replace anchor comments with anchor instructions in tests. Summary: This is because IAS will delete the comments. NFC at the moment but it will prevent a failure once IAS is the default. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14704 llvm-svn: 254147
2015-11-26 18:26:18 +08:00
; ALL: teqi $zero, 1
[mips] Honour -mno-odd-spreg for vector insert/extract when MSA is enabled. Summary: -mno-odd-spreg prohibits the use of odd-numbered single-precision floating point registers. However, vector insert/extract was still using them when manipulating the subregisters of an MSA register. Fixed this by ensuring that insertion/extraction is only performed on even-numbered vector registers when -mno-odd-spreg is given. Reviewers: vmedic, sstankovic Reviewed By: sstankovic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7672 llvm-svn: 230235
2015-02-24 01:22:16 +08:00
; ALL-NOT: st.w
; ALL-NOT: ld.w
; ALL: mov.s $f0, $f[[W0]]
define float @msa_extract_1() {
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load volatile <4 x float>, <4 x float>* @v4f32
[mips] Honour -mno-odd-spreg for vector insert/extract when MSA is enabled. Summary: -mno-odd-spreg prohibits the use of odd-numbered single-precision floating point registers. However, vector insert/extract was still using them when manipulating the subregisters of an MSA register. Fixed this by ensuring that insertion/extraction is only performed on even-numbered vector registers when -mno-odd-spreg is given. Reviewers: vmedic, sstankovic Reviewed By: sstankovic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7672 llvm-svn: 230235
2015-02-24 01:22:16 +08:00
%1 = call <4 x float> asm sideeffect "move.v $0, $1", "={$w13},{$w12}" (<4 x float> %0)
; Clobber all except $f13
;
; The intention is that if odd single precision registers are permitted, the
; allocator will choose $f13/$w13 for the vector since that saves on moves.
;
; On the other hand, if odd single precision registers are not permitted, it
; must be spilled.
[mips][ias] Replace anchor comments with anchor instructions in tests. Summary: This is because IAS will delete the comments. NFC at the moment but it will prevent a failure once IAS is the default. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14704 llvm-svn: 254147
2015-11-26 18:26:18 +08:00
call void asm sideeffect "teqi $$zero, 1", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f12},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
[mips] Honour -mno-odd-spreg for vector insert/extract when MSA is enabled. Summary: -mno-odd-spreg prohibits the use of odd-numbered single-precision floating point registers. However, vector insert/extract was still using them when manipulating the subregisters of an MSA register. Fixed this by ensuring that insertion/extraction is only performed on even-numbered vector registers when -mno-odd-spreg is given. Reviewers: vmedic, sstankovic Reviewed By: sstankovic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7672 llvm-svn: 230235
2015-02-24 01:22:16 +08:00
%2 = extractelement <4 x float> %1, i32 1
ret float %2
}
; ALL-LABEL: msa_extract_1:
; ALL: lw $[[R0:[0-9]+]], %got(v4f32)(
; ALL: ld.w $w12, 0($[[R0]])
; ALL: splati.w $w[[W0:[0-9]+]], $w13[1]
; NOODDSPREG: st.w $w[[W0]], 0($sp)
; ODDSPREG-NOT: st.w
; ODDSPREG-NOT: ld.w
[mips][ias] Replace anchor comments with anchor instructions in tests. Summary: This is because IAS will delete the comments. NFC at the moment but it will prevent a failure once IAS is the default. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14704 llvm-svn: 254147
2015-11-26 18:26:18 +08:00
; ALL: teqi $zero, 1
[mips] Honour -mno-odd-spreg for vector insert/extract when MSA is enabled. Summary: -mno-odd-spreg prohibits the use of odd-numbered single-precision floating point registers. However, vector insert/extract was still using them when manipulating the subregisters of an MSA register. Fixed this by ensuring that insertion/extraction is only performed on even-numbered vector registers when -mno-odd-spreg is given. Reviewers: vmedic, sstankovic Reviewed By: sstankovic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7672 llvm-svn: 230235
2015-02-24 01:22:16 +08:00
; ODDSPREG-NOT: st.w
; ODDSPREG-NOT: ld.w
; NOODDSPREG: ld.w $w0, 0($sp)
; ODDSPREG: mov.s $f0, $f[[W0]]