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llvm-project/llvm/test/CodeGen/Mips/llvm-ir/srem.ll

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[mips] Make Static a default relocation model for MIPS codegen This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 llvm-svn: 265949
2016-04-11 23:24:23 +08:00
; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \
[mips] Remove duplicate tests and add missing prefixes for *-LABEL checks. NFC. Summary: The only difference between the removed tests and the pre-existing ones, is the materialization of the zero constant, which shouldn't matter for these cases. Reviewers: dsanders, sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D18693 llvm-svn: 266285
2016-04-14 17:13:13 +08:00
; RUN: -check-prefix=ALL -check-prefix=GP32 \
; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
[mips] Make Static a default relocation model for MIPS codegen This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 llvm-svn: 265949
2016-04-11 23:24:23 +08:00
; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \
[mips] Remove duplicate tests and add missing prefixes for *-LABEL checks. NFC. Summary: The only difference between the removed tests and the pre-existing ones, is the materialization of the zero constant, which shouldn't matter for these cases. Reviewers: dsanders, sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D18693 llvm-svn: 266285
2016-04-14 17:13:13 +08:00
; RUN: -check-prefix=ALL -check-prefix=GP32 \
; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP32 -check-prefix=R2-R5 \
; RUN: -check-prefix=R2-R6 -check-prefix=NOT-R6
; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP32 -check-prefix=R2-R5 \
; RUN: -check-prefix=R2-R6 -check-prefix=NOT-R6
; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP32 -check-prefix=R2-R5 \
; RUN: -check-prefix=R2-R6 -check-prefix=NOT-R6
[mips] Make Static a default relocation model for MIPS codegen This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 llvm-svn: 265949
2016-04-11 23:24:23 +08:00
; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \
[mips] Remove duplicate tests and add missing prefixes for *-LABEL checks. NFC. Summary: The only difference between the removed tests and the pre-existing ones, is the materialization of the zero constant, which shouldn't matter for these cases. Reviewers: dsanders, sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D18693 llvm-svn: 266285
2016-04-14 17:13:13 +08:00
; RUN: -check-prefix=ALL -check-prefix=GP32 \
; RUN: -check-prefix=R6 -check-prefix=R2-R6
[mips] Make Static a default relocation model for MIPS codegen This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 llvm-svn: 265949
2016-04-11 23:24:23 +08:00
; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \
[mips] Remove duplicate tests and add missing prefixes for *-LABEL checks. NFC. Summary: The only difference between the removed tests and the pre-existing ones, is the materialization of the zero constant, which shouldn't matter for these cases. Reviewers: dsanders, sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D18693 llvm-svn: 266285
2016-04-14 17:13:13 +08:00
; RUN: -check-prefix=ALL -check-prefix=GP64-NOT-R6 \
; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
[mips] Make Static a default relocation model for MIPS codegen This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 llvm-svn: 265949
2016-04-11 23:24:23 +08:00
; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | FileCheck %s \
[mips] Remove duplicate tests and add missing prefixes for *-LABEL checks. NFC. Summary: The only difference between the removed tests and the pre-existing ones, is the materialization of the zero constant, which shouldn't matter for these cases. Reviewers: dsanders, sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D18693 llvm-svn: 266285
2016-04-14 17:13:13 +08:00
; RUN: -check-prefix=ALL -check-prefix=GP64-NOT-R6 \
; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
[mips] Make Static a default relocation model for MIPS codegen This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 llvm-svn: 265949
2016-04-11 23:24:23 +08:00
; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \
[mips] Remove duplicate tests and add missing prefixes for *-LABEL checks. NFC. Summary: The only difference between the removed tests and the pre-existing ones, is the materialization of the zero constant, which shouldn't matter for these cases. Reviewers: dsanders, sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D18693 llvm-svn: 266285
2016-04-14 17:13:13 +08:00
; RUN: -check-prefix=ALL -check-prefix=GP64-NOT-R6 \
; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
[mips] Make Static a default relocation model for MIPS codegen This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 llvm-svn: 265949
2016-04-11 23:24:23 +08:00
; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \
[mips] Remove duplicate tests and add missing prefixes for *-LABEL checks. NFC. Summary: The only difference between the removed tests and the pre-existing ones, is the materialization of the zero constant, which shouldn't matter for these cases. Reviewers: dsanders, sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D18693 llvm-svn: 266285
2016-04-14 17:13:13 +08:00
; RUN: -check-prefix=ALL -check-prefix=R2-R5 -check-prefix=R2-R6 \
; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
[mips] Make Static a default relocation model for MIPS codegen This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 llvm-svn: 265949
2016-04-11 23:24:23 +08:00
; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \
[mips] Remove duplicate tests and add missing prefixes for *-LABEL checks. NFC. Summary: The only difference between the removed tests and the pre-existing ones, is the materialization of the zero constant, which shouldn't matter for these cases. Reviewers: dsanders, sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D18693 llvm-svn: 266285
2016-04-14 17:13:13 +08:00
; RUN: -check-prefix=ALL -check-prefix=R2-R5 -check-prefix=R2-R6 \
; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
[mips] Make Static a default relocation model for MIPS codegen This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 llvm-svn: 265949
2016-04-11 23:24:23 +08:00
; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \
[mips] Remove duplicate tests and add missing prefixes for *-LABEL checks. NFC. Summary: The only difference between the removed tests and the pre-existing ones, is the materialization of the zero constant, which shouldn't matter for these cases. Reviewers: dsanders, sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D18693 llvm-svn: 266285
2016-04-14 17:13:13 +08:00
; RUN: -check-prefix=ALL -check-prefix=R2-R5 -check-prefix=R2-R6 \
; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
[mips] Make Static a default relocation model for MIPS codegen This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 llvm-svn: 265949
2016-04-11 23:24:23 +08:00
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \
[mips] Remove duplicate tests and add missing prefixes for *-LABEL checks. NFC. Summary: The only difference between the removed tests and the pre-existing ones, is the materialization of the zero constant, which shouldn't matter for these cases. Reviewers: dsanders, sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D18693 llvm-svn: 266285
2016-04-14 17:13:13 +08:00
; RUN: -check-prefix=ALL -check-prefix=64R6 \
; RUN: -check-prefix=R6 -check-prefix=R2-R6
[mips][microMIPS] Add CodeGen support for DIV, MOD, DIVU, MODU, DDIV, DMOD, DDIVU and DMODU instructions Differential Revision: http://reviews.llvm.org/D17137 This patch was reverted after the revertion of dependant patch http://reviews.llvm.org/D17068. There was the problem with test-suite failure. The problem is hopefully solved with dependant patch so this patch is commited again. llvm-svn: 266179
2016-04-13 16:02:26 +08:00
; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \
[mips] Remove duplicate tests and add missing prefixes for *-LABEL checks. NFC. Summary: The only difference between the removed tests and the pre-existing ones, is the materialization of the zero constant, which shouldn't matter for these cases. Reviewers: dsanders, sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D18693 llvm-svn: 266285
2016-04-14 17:13:13 +08:00
; RUN: -check-prefix=ALL -check-prefix=MMR3 -check-prefix=MM32
[mips][microMIPS] Add CodeGen support for DIV, MOD, DIVU, MODU, DDIV, DMOD, DDIVU and DMODU instructions Differential Revision: http://reviews.llvm.org/D17137 This patch was reverted after the revertion of dependant patch http://reviews.llvm.org/D17068. There was the problem with test-suite failure. The problem is hopefully solved with dependant patch so this patch is commited again. llvm-svn: 266179
2016-04-13 16:02:26 +08:00
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
[mips] Remove duplicate tests and add missing prefixes for *-LABEL checks. NFC. Summary: The only difference between the removed tests and the pre-existing ones, is the materialization of the zero constant, which shouldn't matter for these cases. Reviewers: dsanders, sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D18693 llvm-svn: 266285
2016-04-14 17:13:13 +08:00
; RUN: -check-prefix=ALL -check-prefix=MMR6 -check-prefix=MM32
[mips] Don't derive the default ABI from the CPU in the backend. Summary: The backend has no reason to behave like a driver and should generally do as it's told (and error out if it can't) instead of trying to figure out what the API user meant. The default ABI is still derived from the arch component as a concession to backwards compatibility. API-users that previously passed an explicit CPU and a triple that was inconsistent with the CPU (e.g. mips-linux-gnu and mips64r2) may get a different ABI to what they got before. However, it's expected that there are no such users on the basis that CodeGen has been asserting that the triple is consistent with the selected ABI for several releases. API-users that were consistent or passed '' or 'generic' as the CPU will see no difference. Reviewers: sdardis, rafael Subscribers: rafael, dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21466 llvm-svn: 273557
2016-06-23 20:42:53 +08:00
; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s \
[mips] Remove duplicate tests and add missing prefixes for *-LABEL checks. NFC. Summary: The only difference between the removed tests and the pre-existing ones, is the materialization of the zero constant, which shouldn't matter for these cases. Reviewers: dsanders, sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D18693 llvm-svn: 266285
2016-04-14 17:13:13 +08:00
; RUN: -check-prefix=ALL -check-prefix=MMR6 -check-prefix=MM64
[mips] Add tests for bitwise binary and integer arithmetic operators. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
2015-01-26 20:04:40 +08:00
define signext i1 @srem_i1(i1 signext %a, i1 signext %b) {
entry:
; ALL-LABEL: srem_i1:
; NOT-R6: div $zero, $4, $5
; NOT-R6: teq $5, $zero, 7
; NOT-R6: mfhi $[[T0:[0-9]+]]
; NOT-R6: sll $[[T1:[0-9]+]], $[[T0]], 31
; NOT-R6: sra $2, $[[T1]], 31
; R6: mod $[[T0:[0-9]+]], $4, $5
; R6: teq $5, $zero, 7
; R6: sll $[[T3:[0-9]+]], $[[T0]], 31
; R6: sra $2, $[[T3]], 31
[mips][microMIPS] Add CodeGen support for DIV, MOD, DIVU, MODU, DDIV, DMOD, DDIVU and DMODU instructions Differential Revision: http://reviews.llvm.org/D17137 This patch was reverted after the revertion of dependant patch http://reviews.llvm.org/D17068. There was the problem with test-suite failure. The problem is hopefully solved with dependant patch so this patch is commited again. llvm-svn: 266179
2016-04-13 16:02:26 +08:00
; MMR3: div $zero, $4, $5
; MMR3: teq $5, $zero, 7
; MMR3: mfhi $[[T0:[0-9]+]]
; MMR3: sll $[[T1:[0-9]+]], $[[T0]], 31
; MMR3: sra $2, $[[T1]], 31
; MMR6: mod $[[T0:[0-9]+]], $4, $5
; MMR6: teq $5, $zero, 7
; MMR6: sll $[[T1:[0-9]+]], $[[T0]], 31
; MMR6: sra $2, $[[T1]], 31
[mips] Add tests for bitwise binary and integer arithmetic operators. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
2015-01-26 20:04:40 +08:00
%r = srem i1 %a, %b
ret i1 %r
}
define signext i8 @srem_i8(i8 signext %a, i8 signext %b) {
entry:
; ALL-LABEL: srem_i8:
; NOT-R2-R6: div $zero, $4, $5
; NOT-R2-R6: teq $5, $zero, 7
; NOT-R2-R6: mfhi $[[T0:[0-9]+]]
; NOT-R2-R6: sll $[[T1:[0-9]+]], $[[T0]], 24
; NOT-R2-R6: sra $2, $[[T1]], 24
[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
; R2-R5: div $zero, $4, $5
; R2-R5: teq $5, $zero, 7
; R2-R5: mfhi $[[T0:[0-9]+]]
; R2-R5: seb $2, $[[T0]]
[mips] Add tests for bitwise binary and integer arithmetic operators. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
2015-01-26 20:04:40 +08:00
; R6: mod $[[T0:[0-9]+]], $4, $5
; R6: teq $5, $zero, 7
; R6: seb $2, $[[T0]]
[mips][microMIPS] Add CodeGen support for DIV, MOD, DIVU, MODU, DDIV, DMOD, DDIVU and DMODU instructions Differential Revision: http://reviews.llvm.org/D17137 This patch was reverted after the revertion of dependant patch http://reviews.llvm.org/D17068. There was the problem with test-suite failure. The problem is hopefully solved with dependant patch so this patch is commited again. llvm-svn: 266179
2016-04-13 16:02:26 +08:00
; MMR3: div $zero, $4, $5
; MMR3: teq $5, $zero, 7
; MMR3: mfhi $[[T0:[0-9]+]]
; MMR3: seb $2, $[[T0]]
; MMR6: mod $[[T0:[0-9]+]], $4, $5
; MMR6: teq $5, $zero, 7
; MMR6: seb $2, $[[T0]]
[mips] Add tests for bitwise binary and integer arithmetic operators. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
2015-01-26 20:04:40 +08:00
%r = srem i8 %a, %b
ret i8 %r
}
define signext i16 @srem_i16(i16 signext %a, i16 signext %b) {
entry:
; ALL-LABEL: srem_i16:
; NOT-R2-R6: div $zero, $4, $5
; NOT-R2-R6: teq $5, $zero, 7
; NOT-R2-R6: mfhi $[[T0:[0-9]+]]
; NOT-R2-R6: sll $[[T1:[0-9]+]], $[[T0]], 16
; NOT-R2-R6: sra $2, $[[T1]], 16
[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
; R2-R5: div $zero, $4, $5
; R2-R5: teq $5, $zero, 7
; R2-R5: mfhi $[[T0:[0-9]+]]
[mips][microMIPS] Add CodeGen support for DIV, MOD, DIVU, MODU, DDIV, DMOD, DDIVU and DMODU instructions Differential Revision: http://reviews.llvm.org/D17137 This patch was reverted after the revertion of dependant patch http://reviews.llvm.org/D17068. There was the problem with test-suite failure. The problem is hopefully solved with dependant patch so this patch is commited again. llvm-svn: 266179
2016-04-13 16:02:26 +08:00
; R2-R5: seh $2, $[[T0]]
[mips] Add tests for bitwise binary and integer arithmetic operators. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
2015-01-26 20:04:40 +08:00
; R6: mod $[[T0:[0-9]+]], $4, $5
; R6: teq $5, $zero, 7
; R6: seh $2, $[[T0]]
[mips][microMIPS] Add CodeGen support for DIV, MOD, DIVU, MODU, DDIV, DMOD, DDIVU and DMODU instructions Differential Revision: http://reviews.llvm.org/D17137 This patch was reverted after the revertion of dependant patch http://reviews.llvm.org/D17068. There was the problem with test-suite failure. The problem is hopefully solved with dependant patch so this patch is commited again. llvm-svn: 266179
2016-04-13 16:02:26 +08:00
; MMR3: div $zero, $4, $5
; MMR3: teq $5, $zero, 7
; MMR3: mfhi $[[T0:[0-9]+]]
; MMR3: seh $2, $[[T0]]
; MMR6: mod $[[T0:[0-9]+]], $4, $5
; MMR6: teq $5, $zero, 7
; MMR6: seh $2, $[[T0]]
[mips] Add tests for bitwise binary and integer arithmetic operators. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
2015-01-26 20:04:40 +08:00
%r = srem i16 %a, %b
ret i16 %r
}
define signext i32 @srem_i32(i32 signext %a, i32 signext %b) {
entry:
; ALL-LABEL: srem_i32:
; NOT-R6: div $zero, $4, $5
; NOT-R6: teq $5, $zero, 7
; NOT-R6: mfhi $2
; R6: mod $2, $4, $5
; R6: teq $5, $zero, 7
[mips][microMIPS] Add CodeGen support for DIV, MOD, DIVU, MODU, DDIV, DMOD, DDIVU and DMODU instructions Differential Revision: http://reviews.llvm.org/D17137 This patch was reverted after the revertion of dependant patch http://reviews.llvm.org/D17068. There was the problem with test-suite failure. The problem is hopefully solved with dependant patch so this patch is commited again. llvm-svn: 266179
2016-04-13 16:02:26 +08:00
; MMR3: div $zero, $4, $5
; MMR3: teq $5, $zero, 7
; MMR3: mfhi $2
; MMR6: mod $2, $4, $5
; MMR6: teq $5, $zero, 7
[mips] Add tests for bitwise binary and integer arithmetic operators. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
2015-01-26 20:04:40 +08:00
%r = srem i32 %a, %b
ret i32 %r
}
define signext i64 @srem_i64(i64 signext %a, i64 signext %b) {
entry:
; ALL-LABEL: srem_i64:
; GP32: lw $25, %call16(__moddi3)($gp)
; GP64-NOT-R6: ddiv $zero, $4, $5
; GP64-NOT-R6: teq $5, $zero, 7
; GP64-NOT-R6: mfhi $2
; 64R6: dmod $2, $4, $5
; 64R6: teq $5, $zero, 7
[mips][microMIPS] Add CodeGen support for DIV, MOD, DIVU, MODU, DDIV, DMOD, DDIVU and DMODU instructions Differential Revision: http://reviews.llvm.org/D17137 This patch was reverted after the revertion of dependant patch http://reviews.llvm.org/D17068. There was the problem with test-suite failure. The problem is hopefully solved with dependant patch so this patch is commited again. llvm-svn: 266179
2016-04-13 16:02:26 +08:00
; MM32: lw $25, %call16(__moddi3)($2)
; MM64: dmod $2, $4, $5
; MM64: teq $5, $zero, 7
[mips] Add tests for bitwise binary and integer arithmetic operators. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
2015-01-26 20:04:40 +08:00
%r = srem i64 %a, %b
ret i64 %r
}
[mips] Enable arithmetic and binary operations for the i128 data type. Summary: This patch adds support for some operations that were missing from 128-bit integer types (add/sub/mul/sdiv/udiv... etc.). With these changes we can support the __int128_t and __uint128_t data types from C/C++. Depends on D7125 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7143 llvm-svn: 227089
2015-01-26 20:33:22 +08:00
define signext i128 @srem_i128(i128 signext %a, i128 signext %b) {
entry:
; ALL-LABEL: srem_i128:
; GP32: lw $25, %call16(__modti3)($gp)
[mips][microMIPS] Add CodeGen support for DIV, MOD, DIVU, MODU, DDIV, DMOD, DDIVU and DMODU instructions Differential Revision: http://reviews.llvm.org/D17137 This patch was reverted after the revertion of dependant patch http://reviews.llvm.org/D17068. There was the problem with test-suite failure. The problem is hopefully solved with dependant patch so this patch is commited again. llvm-svn: 266179
2016-04-13 16:02:26 +08:00
; GP64-NOT-R6: ld $25, %call16(__modti3)($gp)
; 64R6: ld $25, %call16(__modti3)($gp)
; MM32: lw $25, %call16(__modti3)($2)
; MM64: ld $25, %call16(__modti3)($2)
[mips] Remove duplicate tests and add missing prefixes for *-LABEL checks. NFC. Summary: The only difference between the removed tests and the pre-existing ones, is the materialization of the zero constant, which shouldn't matter for these cases. Reviewers: dsanders, sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D18693 llvm-svn: 266285
2016-04-14 17:13:13 +08:00
%r = srem i128 %a, %b
[mips][microMIPS] Add CodeGen support for DIV, MOD, DIVU, MODU, DDIV, DMOD, DDIVU and DMODU instructions Differential Revision: http://reviews.llvm.org/D17137 This patch was reverted after the revertion of dependant patch http://reviews.llvm.org/D17068. There was the problem with test-suite failure. The problem is hopefully solved with dependant patch so this patch is commited again. llvm-svn: 266179
2016-04-13 16:02:26 +08:00
ret i128 %r
}