2017-09-09 01:33:54 +08:00
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=i386-unknown-linux-gnu -mattr=-slow-incdec < %s | FileCheck -check-prefix=CHECK -check-prefix=INCDEC %s
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; RUN: llc -mtriple=i386-unknown-linux-gnu -mattr=+slow-incdec < %s | FileCheck -check-prefix=CHECK -check-prefix=ADD %s
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2014-11-18 00:17:51 +08:00
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2017-09-09 01:33:54 +08:00
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define i32 @inc(i32 %x) {
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; INCDEC-LABEL: inc:
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2017-12-05 01:18:51 +08:00
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; INCDEC: # %bb.0:
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2017-09-09 01:33:54 +08:00
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; INCDEC-NEXT: movl {{[0-9]+}}(%esp), %eax
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; INCDEC-NEXT: incl %eax
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; INCDEC-NEXT: retl
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2014-11-18 00:17:51 +08:00
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;
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2017-09-09 01:33:54 +08:00
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; ADD-LABEL: inc:
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2017-12-05 01:18:51 +08:00
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; ADD: # %bb.0:
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2017-09-09 01:33:54 +08:00
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; ADD-NEXT: movl {{[0-9]+}}(%esp), %eax
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; ADD-NEXT: addl $1, %eax
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; ADD-NEXT: retl
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%r = add i32 %x, 1
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ret i32 %r
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2014-11-18 00:17:51 +08:00
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}
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2017-09-09 01:33:54 +08:00
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define i32 @dec(i32 %x) {
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; INCDEC-LABEL: dec:
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2017-12-05 01:18:51 +08:00
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; INCDEC: # %bb.0:
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2017-09-09 01:33:54 +08:00
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; INCDEC-NEXT: movl {{[0-9]+}}(%esp), %eax
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; INCDEC-NEXT: decl %eax
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; INCDEC-NEXT: retl
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;
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; ADD-LABEL: dec:
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2017-12-05 01:18:51 +08:00
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; ADD: # %bb.0:
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2017-09-09 01:33:54 +08:00
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; ADD-NEXT: movl {{[0-9]+}}(%esp), %eax
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; ADD-NEXT: addl $-1, %eax
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; ADD-NEXT: retl
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%r = add i32 %x, -1
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ret i32 %r
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}
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2014-11-18 00:17:51 +08:00
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2017-09-09 01:33:54 +08:00
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define i32 @inc_size(i32 %x) optsize {
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2017-09-10 01:11:59 +08:00
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; CHECK-LABEL: inc_size:
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2017-12-05 01:18:51 +08:00
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; CHECK: # %bb.0:
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2017-09-10 01:11:59 +08:00
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: incl %eax
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; CHECK-NEXT: retl
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2017-09-09 01:33:54 +08:00
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%r = add i32 %x, 1
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ret i32 %r
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2014-11-18 00:17:51 +08:00
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}
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2017-09-09 01:33:54 +08:00
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define i32 @dec_size(i32 %x) optsize {
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2017-09-10 01:11:59 +08:00
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; CHECK-LABEL: dec_size:
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2017-12-05 01:18:51 +08:00
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; CHECK: # %bb.0:
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2017-09-10 01:11:59 +08:00
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: decl %eax
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; CHECK-NEXT: retl
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2017-09-09 01:33:54 +08:00
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%r = add i32 %x, -1
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ret i32 %r
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}
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