2018-03-01 06:57:23 +08:00
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown- -mcpu=core2 | FileCheck %s --check-prefixes=CHECK
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2011-08-27 05:21:21 +08:00
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; Basic 128-bit cmpxchg
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define void @t1(i128* nocapture %p) nounwind ssp {
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2018-03-01 06:57:23 +08:00
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; CHECK-LABEL: t1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushq %rbx
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Bias physical register immediate assignments
The machine scheduler currently biases register copies to/from
physical registers to be closer to their point of use / def to
minimize their live ranges. This change extends this to also physical
register assignments from immediate values.
This causes a reduction in reduction in overall register pressure and
minor reduction in spills and indirectly fixes an out-of-registers
assertion (PR39391).
Most test changes are from minor instruction reorderings and register
name selection changes and direct consequences of that.
Reviewers: MatzeB, qcolombet, myatsina, pcc
Subscribers: nemanjai, jvesely, nhaehnle, eraman, hiraditya,
javed.absar, arphaman, jfb, jsji, llvm-commits
Differential Revision: https://reviews.llvm.org/D54218
llvm-svn: 346894
2018-11-15 05:11:53 +08:00
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; CHECK-NEXT: movl $1, %ebx
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2018-03-01 06:57:23 +08:00
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: xorl %edx, %edx
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; CHECK-NEXT: xorl %ecx, %ecx
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; CHECK-NEXT: lock cmpxchg16b (%rdi)
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: retq
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2011-08-27 05:21:21 +08:00
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entry:
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2014-03-11 18:48:52 +08:00
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%r = cmpxchg i128* %p, i128 0, i128 1 seq_cst seq_cst
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2011-08-27 05:21:21 +08:00
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ret void
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}
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; FIXME: Handle 128-bit atomicrmw/load atomic/store atomic
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