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llvm-project/llvm/test/CodeGen/Mips/llvm-ir/sub.ll

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[mips] Add tests for bitwise binary and integer arithmetic operators. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
2015-01-26 20:04:40 +08:00
; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32
; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32
; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
[mips] Add tests for bitwise binary and integer arithmetic operators. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
2015-01-26 20:04:40 +08:00
; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
[mips] Add tests for bitwise binary and integer arithmetic operators. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
2015-01-26 20:04:40 +08:00
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
define signext i1 @sub_i1(i1 signext %a, i1 signext %b) {
entry:
; ALL-LABEL: sub_i1:
; ALL: subu $[[T0:[0-9]+]], $4, $5
; ALL: sll $[[T0]], $[[T0]], 31
; ALL: sra $2, $[[T0]], 31
%r = sub i1 %a, %b
ret i1 %r
}
define signext i8 @sub_i8(i8 signext %a, i8 signext %b) {
entry:
; ALL-LABEL: sub_i8:
; NOT-R2-R6: subu $[[T0:[0-9]+]], $4, $5
; NOT-R2-R6: sll $[[T0]], $[[T0]], 24
; NOT-R2-R6: sra $2, $[[T0]], 24
; R2-R6: subu $[[T0:[0-9]+]], $4, $5
; R2-R6: seb $2, $[[T0:[0-9]+]]
%r = sub i8 %a, %b
ret i8 %r
}
define signext i16 @sub_i16(i16 signext %a, i16 signext %b) {
entry:
; ALL-LABEL: sub_i16:
; NOT-R2-R6: subu $[[T0:[0-9]+]], $4, $5
; NOT-R2-R6: sll $[[T0]], $[[T0]], 16
; NOT-R2-R6: sra $2, $[[T0]], 16
; R2-R6: subu $[[T0:[0-9]+]], $4, $5
; R2-R6: seh $2, $[[T0:[0-9]+]]
%r = sub i16 %a, %b
ret i16 %r
}
define signext i32 @sub_i32(i32 signext %a, i32 signext %b) {
entry:
; ALL-LABEL: sub_i32:
; ALL: subu $2, $4, $5
%r = sub i32 %a, %b
ret i32 %r
}
define signext i64 @sub_i64(i64 signext %a, i64 signext %b) {
entry:
; ALL-LABEL: sub_i64:
; GP32: subu $3, $5, $7
; GP32: sltu $[[T0:[0-9]+]], $5, $7
; GP32: addu $[[T1:[0-9]+]], $[[T0]], $6
; GP32: subu $2, $4, $[[T1]]
; GP64: dsubu $2, $4, $5
%r = sub i64 %a, %b
ret i64 %r
}
[mips] Enable arithmetic and binary operations for the i128 data type. Summary: This patch adds support for some operations that were missing from 128-bit integer types (add/sub/mul/sdiv/udiv... etc.). With these changes we can support the __int128_t and __uint128_t data types from C/C++. Depends on D7125 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7143 llvm-svn: 227089
2015-01-26 20:33:22 +08:00
define signext i128 @sub_i128(i128 signext %a, i128 signext %b) {
entry:
; ALL-LABEL: sub_i128:
; GP32: lw $[[T0:[0-9]+]], 20($sp)
; GP32: sltu $[[T1:[0-9]+]], $5, $[[T0]]
; GP32: lw $[[T2:[0-9]+]], 16($sp)
; GP32: addu $[[T3:[0-9]+]], $[[T1]], $[[T2]]
; GP32: lw $[[T4:[0-9]+]], 24($sp)
; GP32: lw $[[T5:[0-9]+]], 28($sp)
; GP32: subu $[[T6:[0-9]+]], $7, $[[T5]]
; GP32: subu $2, $4, $[[T3]]
; GP32: sltu $[[T8:[0-9]+]], $6, $[[T4]]
; GP32: addu $[[T9:[0-9]+]], $[[T8]], $[[T0]]
; GP32: subu $3, $5, $[[T9]]
; GP32: sltu $[[T10:[0-9]+]], $7, $[[T5]]
; GP32: addu $[[T11:[0-9]+]], $[[T10]], $[[T4]]
; GP32: subu $4, $6, $[[T11]]
; GP32: move $5, $[[T6]]
; GP64: dsubu $3, $5, $7
; GP64: sltu $[[T0:[0-9]+]], $5, $7
; GP64: daddu $[[T1:[0-9]+]], $[[T0]], $6
; GP64: dsubu $2, $4, $[[T1]]
%r = sub i128 %a, %b
ret i128 %r
}