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llvm-project/llvm/test/CodeGen/Mips/inlineasm64.ll

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Replace obsolete -mattr=n64 command line option with -target-abi=n64. No functional changes. llvm-svn: 230628
2015-02-26 20:29:48 +08:00
; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 < %s | FileCheck %s
Have getRegForInlineAsmConstraint return the correct register class when target is Mips64. llvm-svn: 147516
2012-01-04 10:45:01 +08:00
@gl2 = external global i64
@gl1 = external global i64
@gl0 = external global i64
define void @foo1() nounwind {
entry:
; CHECK: foo1
; CHECK: daddu
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load i64, i64* @gl1, align 8
%1 = load i64, i64* @gl0, align 8
Have getRegForInlineAsmConstraint return the correct register class when target is Mips64. llvm-svn: 147516
2012-01-04 10:45:01 +08:00
%2 = tail call i64 asm "daddu $0, $1, $2", "=r,r,r"(i64 %0, i64 %1) nounwind
store i64 %2, i64* @gl2, align 8
ret void
}