maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/lib/Target/Mips/MipsSEISelLowering.h

97 lines
3.8 KiB
C
Raw Normal View History

[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
2013-03-13 08:54:29 +08:00
//===-- MipsSEISelLowering.h - MipsSE DAG Lowering Interface ----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// Subclass of MipsTargetLowering specialized for mips32/64.
//
//===----------------------------------------------------------------------===//
#ifndef MipsSEISELLOWERING_H
#define MipsSEISELLOWERING_H
#include "MipsISelLowering.h"
[mips] Implement getRepRegClassFor in MipsSETargetLowering. This function is called in several places in ScheduleDAGRRList.cpp. llvm-svn: 178393
2013-03-30 09:12:05 +08:00
#include "MipsRegisterInfo.h"
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
2013-03-13 08:54:29 +08:00
namespace llvm {
class MipsSETargetLowering : public MipsTargetLowering {
public:
explicit MipsSETargetLowering(MipsTargetMachine &TM);
[mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD) Note: There's a later patch on my branch that re-implements this to select build_vector without the custom SelectionDAG nodes. The future patch avoids the constant-folding problems stemming from the custom node (i.e. it doesn't need to re-implement all the DAG combines related to BUILD_VECTOR). Changes to MIPS specific SelectionDAG nodes: * Added VSPLAT This is a special case of BUILD_VECTOR that covers the case the BUILD_VECTOR is a splat operation. * Added VSPLATD This is a special case of VSPLAT that handles the cases when v2i64 is legal llvm-svn: 191191
2013-09-23 20:02:46 +08:00
/// \brief Enable MSA support for the given integer type and Register
/// class.
[mips][msa] Separate the configuration of int/float vector types since they will diverge soon No functional change llvm-svn: 190506
2013-09-11 18:15:48 +08:00
void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC);
[mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD) Note: There's a later patch on my branch that re-implements this to select build_vector without the custom SelectionDAG nodes. The future patch avoids the constant-folding problems stemming from the custom node (i.e. it doesn't need to re-implement all the DAG combines related to BUILD_VECTOR). Changes to MIPS specific SelectionDAG nodes: * Added VSPLAT This is a special case of BUILD_VECTOR that covers the case the BUILD_VECTOR is a splat operation. * Added VSPLATD This is a special case of VSPLAT that handles the cases when v2i64 is legal llvm-svn: 191191
2013-09-23 20:02:46 +08:00
/// \brief Enable MSA support for the given floating-point type and
/// Register class.
[mips][msa] Separate the configuration of int/float vector types since they will diverge soon No functional change llvm-svn: 190506
2013-09-11 18:15:48 +08:00
void addMSAFloatType(MVT::SimpleValueType Ty,
const TargetRegisterClass *RC);
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
2013-03-13 08:54:29 +08:00
virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const;
[mips] Fix definitions of multiply, multiply-add/sub and divide instructions. The new instructions have explicit register output operands and use table-gen patterns instead of C++ code to do instruction selection. Mips16's instructions are unaffected by this change. llvm-svn: 178403
2013-03-30 09:36:35 +08:00
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
[mips] Move the code which does dag-combine for multiply-add/sub nodes to derived class MipsSETargetLowering. We shouldn't be generating madd/msub nodes if target is Mips16, since Mips16 doesn't have support for multipy-add/sub instructions. llvm-svn: 178404
2013-03-30 09:42:24 +08:00
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
2013-03-13 08:54:29 +08:00
virtual MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
[mips] Override TargetLoweringBase::isShuffleMaskLegal. llvm-svn: 179433
2013-04-13 08:45:02 +08:00
virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
EVT VT) const {
return false;
}
[mips] Implement getRepRegClassFor in MipsSETargetLowering. This function is called in several places in ScheduleDAGRRList.cpp. llvm-svn: 178393
2013-03-30 09:12:05 +08:00
virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
if (VT == MVT::Untyped)
[mips] Rename accumulator register classes and FP register operands. llvm-svn: 188020
2013-08-09 05:54:26 +08:00
return Subtarget->hasDSP() ? &Mips::ACC64DSPRegClass :
&Mips::ACC64RegClass;
[mips] Implement getRepRegClassFor in MipsSETargetLowering. This function is called in several places in ScheduleDAGRRList.cpp. llvm-svn: 178393
2013-03-30 09:12:05 +08:00
return TargetLowering::getRepRegClassFor(VT);
}
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
2013-03-13 08:54:29 +08:00
private:
virtual bool
isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
unsigned NextStackOffset,
const MipsFunctionInfo& FI) const;
virtual void
getOpndList(SmallVectorImpl<SDValue> &Ops,
std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
[mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double precision loads and stores as well as reg+imm double precision loads and stores. Previously, expansion of loads and stores was done after register allocation, but now it takes place during legalization. As a result, users will see double precision stores and loads being emitted to spill and restore 64-bit FP registers. llvm-svn: 190235
2013-09-07 08:52:30 +08:00
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
[mips] Fix definitions of multiply, multiply-add/sub and divide instructions. The new instructions have explicit register output operands and use table-gen patterns instead of C++ code to do instruction selection. Mips16's instructions are unaffected by this change. llvm-svn: 178403
2013-03-30 09:36:35 +08:00
SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
SelectionDAG &DAG) const;
[mips] Move MipsTargetLowering::lowerINTRINSIC_W_CHAIN and lowerINTRINSIC_WO_CHAIN into MipsSETargetLowering. No functionality changes. llvm-svn: 179444
2013-04-13 10:13:30 +08:00
SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
[mips][msa] Added load/store intrinsics. llvm-svn: 189476
2013-08-28 20:04:29 +08:00
SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
[mips][msa] Added support for matching insert and copy from normal IR (i.e. not intrinsics) Changes to MIPS SelectionDAG: * Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a single operation and implemented the DAG combines necessary to fold sign/zero extends into the extract. llvm-svn: 191199
2013-09-23 22:03:12 +08:00
SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
[mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD) Note: There's a later patch on my branch that re-implements this to select build_vector without the custom SelectionDAG nodes. The future patch avoids the constant-folding problems stemming from the custom node (i.e. it doesn't need to re-implement all the DAG combines related to BUILD_VECTOR). Changes to MIPS specific SelectionDAG nodes: * Added VSPLAT This is a special case of BUILD_VECTOR that covers the case the BUILD_VECTOR is a splat operation. * Added VSPLATD This is a special case of VSPLAT that handles the cases when v2i64 is legal llvm-svn: 191191
2013-09-23 20:02:46 +08:00
SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
[mips][msa] Added support for matching vshf from normal IR (i.e. not intrinsics) llvm-svn: 191301
2013-09-24 22:02:15 +08:00
/// \brief Lower VECTOR_SHUFFLE into one of a number of instructions
/// depending on the indices in the shuffle.
SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
[mips] Move MipsTargetLowering::lowerINTRINSIC_W_CHAIN and lowerINTRINSIC_WO_CHAIN into MipsSETargetLowering. No functionality changes. llvm-svn: 179444
2013-04-13 10:13:30 +08:00
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
2013-03-13 08:54:29 +08:00
MachineBasicBlock *emitBPOSGE32(MachineInstr *MI,
MachineBasicBlock *BB) const;
[mips][msa] Added bnz.df, bnz.v, bz.df, and bz.v These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes, are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as a branch/mov sequence to evaluate to 0 or 1. Note: The resulting code is sub-optimal since it doesnt seem to be possible to feed the result of an intrinsic directly into a brcond. At the moment it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily evaluates the boolean twice. llvm-svn: 189478
2013-08-28 20:14:50 +08:00
MachineBasicBlock *emitMSACBranchPseudo(MachineInstr *MI,
MachineBasicBlock *BB,
unsigned BranchOp) const;
[mips][msa] Implemented extract_vector_elt for v4f32 or v2f64 For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may be expanded to subregister copies and/or instructions as appropriate. llvm-svn: 191514
2013-09-27 20:17:32 +08:00
/// \brief Emit the COPY_FW pseudo instruction
MachineBasicBlock *emitCOPY_FW(MachineInstr *MI,
MachineBasicBlock *BB) const;
/// \brief Emit the COPY_FD pseudo instruction
MachineBasicBlock *emitCOPY_FD(MachineInstr *MI,
MachineBasicBlock *BB) const;
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
2013-03-13 08:54:29 +08:00
};
}
#endif // MipsSEISELLOWERING_H