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llvm-project/llvm/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll

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[mips] Disable code generation through FastISel for MIPS32R6. Reviewers: dsanders Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14708 llvm-svn: 253225
2015-11-17 01:05:01 +08:00
; RUN: llc -march=mips -mcpu=mips2 -O0 -relocation-model=pic \
; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s
; RUN: llc -march=mips -mcpu=mips3 -O0 -relocation-model=pic \
; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s
; RUN: llc -march=mips -mcpu=mips4 -O0 -relocation-model=pic \
; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s
; RUN: llc -march=mips -mcpu=mips32r6 -O0 -relocation-model=pic \
; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s
; RUN: llc -march=mips -mcpu=mips64 -O0 -relocation-model=pic \
; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s
; RUN: llc -march=mips -mcpu=mips64r2 -O0 -relocation-model=pic \
; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s
; RUN: llc -march=mips -mcpu=mips64r3 -O0 -relocation-model=pic \
; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s
; RUN: llc -march=mips -mcpu=mips64r5 -O0 -relocation-model=pic \
; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s
; RUN: llc -march=mips -mcpu=mips32r6 -O0 -relocation-model=pic \
; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s
; CHECK: FastISel missed terminator: ret i32 0
define i32 @foo() {
entry:
ret i32 0
}