forked from OSchip/llvm-project
75 lines
2.0 KiB
LLVM
75 lines
2.0 KiB
LLVM
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; RUN: opt < %s -instcombine -S | FileCheck %s
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; With left shift, the comparison should not be modified.
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; CHECK-LABEL: @test_shift_and_cmp_not_changed1(
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; CHECK: icmp slt i8 %andp, 32
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define i1 @test_shift_and_cmp_not_changed1(i8 %p) #0 {
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entry:
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%shlp = shl i8 %p, 5
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%andp = and i8 %shlp, -64
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%cmp = icmp slt i8 %andp, 32
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ret i1 %cmp
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}
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; With arithmetic right shift, the comparison should not be modified.
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; CHECK-LABEL: @test_shift_and_cmp_not_changed2(
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; CHECK: icmp slt i8 %andp, 32
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define i1 @test_shift_and_cmp_not_changed2(i8 %p) #0 {
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entry:
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%shlp = ashr i8 %p, 5
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%andp = and i8 %shlp, -64
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%cmp = icmp slt i8 %andp, 32
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ret i1 %cmp
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}
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; This should simplify functionally to the left shift case.
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; The extra input parameter should be optimized away.
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; CHECK-LABEL: @test_shift_and_cmp_changed1(
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; CHECK: %andp = shl i8 %p, 5
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; CHECK-NEXT: %shl = and i8 %andp, -64
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; CHECK-NEXT: %cmp = icmp slt i8 %shl, 32
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define i1 @test_shift_and_cmp_changed1(i8 %p, i8 %q) #0 {
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entry:
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%andp = and i8 %p, 6
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%andq = and i8 %q, 8
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%or = or i8 %andq, %andp
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%shl = shl i8 %or, 5
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%ashr = ashr i8 %shl, 5
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%cmp = icmp slt i8 %ashr, 1
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ret i1 %cmp
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}
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; Unsigned compare allows a transformation to compare against 0.
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; CHECK-LABEL: @test_shift_and_cmp_changed2(
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; CHECK: icmp eq i8 %andp, 0
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define i1 @test_shift_and_cmp_changed2(i8 %p) #0 {
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entry:
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%shlp = shl i8 %p, 5
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%andp = and i8 %shlp, -64
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%cmp = icmp ult i8 %andp, 32
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ret i1 %cmp
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}
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; nsw on the shift should not affect the comparison.
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; CHECK-LABEL: @test_shift_and_cmp_changed3(
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; CHECK: icmp slt i8 %andp, 32
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define i1 @test_shift_and_cmp_changed3(i8 %p) #0 {
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entry:
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%shlp = shl nsw i8 %p, 5
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%andp = and i8 %shlp, -64
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%cmp = icmp slt i8 %andp, 32
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ret i1 %cmp
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}
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; Logical shift right allows a return true because the 'and' guarantees no bits are set.
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; CHECK-LABEL: @test_shift_and_cmp_changed4(
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; CHECK: ret i1 true
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define i1 @test_shift_and_cmp_changed4(i8 %p) #0 {
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entry:
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%shlp = lshr i8 %p, 5
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%andp = and i8 %shlp, -64
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%cmp = icmp slt i8 %andp, 32
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ret i1 %cmp
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}
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