forked from OSchip/llvm-project
71 lines
2.0 KiB
C++
71 lines
2.0 KiB
C++
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//===-- checksum.cpp --------------------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "checksum.h"
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#include "atomic_helpers.h"
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#if defined(__x86_64__) || defined(__i386__)
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#include <cpuid.h>
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#elif defined(__arm__) || defined(__aarch64__)
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#if SCUDO_FUCHSIA
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#include <zircon/features.h>
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#include <zircon/syscalls.h>
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#else
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#include <sys/auxv.h>
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#endif
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#endif
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namespace scudo {
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Checksum HashAlgorithm = {Checksum::BSD};
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#if defined(__x86_64__) || defined(__i386__)
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// i386 and x86_64 specific code to detect CRC32 hardware support via CPUID.
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// CRC32 requires the SSE 4.2 instruction set.
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#ifndef bit_SSE4_2
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#define bit_SSE4_2 bit_SSE42 // clang and gcc have different defines.
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#endif
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bool hasHardwareCRC32() {
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u32 Eax, Ebx = 0, Ecx = 0, Edx = 0;
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__get_cpuid(0, &Eax, &Ebx, &Ecx, &Edx);
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const bool IsIntel = (Ebx == signature_INTEL_ebx) &&
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(Edx == signature_INTEL_edx) &&
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(Ecx == signature_INTEL_ecx);
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const bool IsAMD = (Ebx == signature_AMD_ebx) && (Edx == signature_AMD_edx) &&
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(Ecx == signature_AMD_ecx);
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if (!IsIntel && !IsAMD)
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return false;
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__get_cpuid(1, &Eax, &Ebx, &Ecx, &Edx);
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return !!(Ecx & bit_SSE4_2);
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}
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#elif defined(__arm__) || defined(__aarch64__)
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#ifndef AT_HWCAP
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#define AT_HWCAP 16
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#endif
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#ifndef HWCAP_CRC32
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#define HWCAP_CRC32 (1U << 7) // HWCAP_CRC32 is missing on older platforms.
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#endif
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bool hasHardwareCRC32() {
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#if SCUDO_FUCHSIA
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u32 HWCap;
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const zx_status_t Status =
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zx_system_get_features(ZX_FEATURE_KIND_CPU, &HWCap);
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if (Status != ZX_OK)
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return false;
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return !!(HWCap & ZX_ARM64_FEATURE_ISA_CRC32);
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#else
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return !!(getauxval(AT_HWCAP) & HWCAP_CRC32);
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#endif // SCUDO_FUCHSIA
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}
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#endif // defined(__x86_64__) || defined(__i386__)
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} // namespace scudo
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