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llvm-project/llvm/test/CodeGen/XCore/unaligned_load.ll

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Eliminate more uses of llvm-as and llvm-dis. llvm-svn: 81293
2009-09-09 08:09:15 +08:00
; RUN: llc < %s -march=xcore > %t1.s
Custom lower unaligned 32 bit stores and loads into libcalls. This is a big code size win since before they were expanding to upto 16 instructions. llvm-svn: 75901
2009-07-16 18:21:18 +08:00
; RUN: grep "bl __misaligned_load" %t1.s | count 1
Expand unaligned 32 bit loads from an address which is a constant offset from a 32 bit aligned base as follows: ldw low, base[offset >> 2] ldw high, base[(offset >> 2) + 1] shr low_shifted, low, (offset & 0x3) * 8 shl high_shifted, high, 32 - (offset & 0x3) * 8 or result, low_shifted, high_shifted Expand 32 bit loads / stores with 16 bit alignment into two 16 bit loads / stores. llvm-svn: 75902
2009-07-16 18:42:35 +08:00
; RUN: grep ld16s %t1.s | count 2
; RUN: grep ldw %t1.s | count 2
; RUN: grep shl %t1.s | count 2
; RUN: grep shr %t1.s | count 1
; RUN: grep zext %t1.s | count 1
; RUN: grep "or " %t1.s | count 2
Custom lower unaligned 32 bit stores and loads into libcalls. This is a big code size win since before they were expanding to upto 16 instructions. llvm-svn: 75901
2009-07-16 18:21:18 +08:00
; Byte aligned load. Expands to call to __misaligned_load.
define i32 @align1(i32* %p) nounwind {
entry:
%0 = load i32* %p, align 1 ; <i32> [#uses=1]
ret i32 %0
}
Expand unaligned 32 bit loads from an address which is a constant offset from a 32 bit aligned base as follows: ldw low, base[offset >> 2] ldw high, base[(offset >> 2) + 1] shr low_shifted, low, (offset & 0x3) * 8 shl high_shifted, high, 32 - (offset & 0x3) * 8 or result, low_shifted, high_shifted Expand 32 bit loads / stores with 16 bit alignment into two 16 bit loads / stores. llvm-svn: 75902
2009-07-16 18:42:35 +08:00
; Half word aligned load. Expands to two 16bit loads.
define i32 @align2(i32* %p) nounwind {
entry:
%0 = load i32* %p, align 2 ; <i32> [#uses=1]
ret i32 %0
}
@a = global [5 x i8] zeroinitializer, align 4
; Constant offset from word aligned base. Expands to two 32bit loads.
define i32 @align3() nounwind {
entry:
%0 = load i32* bitcast (i8* getelementptr ([5 x i8]* @a, i32 0, i32 1) to i32*), align 1
ret i32 %0
}