maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/AMDGPU/sdiv64.ll

Ignoring revisions in .git-blame-ignore-revs. Click here to bypass and see the normal blame view.

1165 lines
47 KiB
LLVM
Raw Normal View History

AMDGPU: Cleanup and generate 64-bit div tests Split out r600 tests, and try to be more consistent with coverage. Cover a few more cases for 24-bit optimization and constants.
2020-01-19 05:51:43 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
define amdgpu_kernel void @s_test_sdiv(i64 addrspace(1)* %out, i64 %x, i64 %y) {
; GCN-LABEL: s_test_sdiv:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd
; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_ashr_i32 s0, s3, 31
; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: s_mov_b32 s4, s8
; GCN-NEXT: s_mov_b32 s5, s9
; GCN-NEXT: s_mov_b32 s1, s0
; GCN-NEXT: s_add_u32 s2, s2, s0
; GCN-NEXT: s_addc_u32 s3, s3, s0
; GCN-NEXT: s_xor_b64 s[2:3], s[2:3], s[0:1]
; GCN-NEXT: v_cvt_f32_u32_e32 v2, s2
; GCN-NEXT: v_cvt_f32_u32_e32 v3, s3
; GCN-NEXT: s_sub_u32 s14, 0, s2
; GCN-NEXT: v_mov_b32_e32 v4, s3
; GCN-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
; GCN-NEXT: s_subb_u32 s15, 0, s3
; GCN-NEXT: s_ashr_i32 s8, s11, 31
; GCN-NEXT: v_rcp_f32_e32 v2, v2
; GCN-NEXT: s_mov_b32 s9, s8
; GCN-NEXT: s_add_u32 s10, s10, s8
; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
; GCN-NEXT: s_addc_u32 s11, s11, s8
; GCN-NEXT: s_xor_b64 s[12:13], s[8:9], s[0:1]
; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
; GCN-NEXT: s_xor_b64 s[8:9], s[10:11], s[8:9]
; GCN-NEXT: v_mov_b32_e32 v5, s13
; GCN-NEXT: v_trunc_f32_e32 v3, v3
; GCN-NEXT: v_mov_b32_e32 v6, s9
; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3
; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
; GCN-NEXT: v_mul_lo_u32 v7, s14, v3
; GCN-NEXT: v_mul_lo_u32 v8, s15, v2
; GCN-NEXT: v_mul_hi_u32 v9, s14, v2
; GCN-NEXT: v_mul_lo_u32 v10, s14, v2
; GCN-NEXT: v_add_i32_e32 v7, vcc, v9, v7
; GCN-NEXT: v_mul_hi_u32 v9, v2, v10
; GCN-NEXT: v_mul_hi_u32 v11, v3, v10
; GCN-NEXT: v_mul_lo_u32 v10, v3, v10
; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GCN-NEXT: v_mul_hi_u32 v8, v2, v7
; GCN-NEXT: v_mul_lo_u32 v12, v2, v7
; GCN-NEXT: v_mul_hi_u32 v13, v3, v7
; GCN-NEXT: v_mul_lo_u32 v7, v3, v7
; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; GCN-NEXT: v_addc_u32_e32 v8, vcc, v1, v8, vcc
; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GCN-NEXT: v_addc_u32_e32 v8, vcc, v8, v11, vcc
; GCN-NEXT: v_addc_u32_e32 v9, vcc, v13, v0, vcc
; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; GCN-NEXT: v_addc_u32_e32 v8, vcc, v1, v9, vcc
; GCN-NEXT: v_add_i32_e64 v2, s[0:1], v2, v7
; GCN-NEXT: v_addc_u32_e64 v7, vcc, v3, v8, s[0:1]
; GCN-NEXT: v_mul_hi_u32 v9, s14, v2
; GCN-NEXT: v_mul_lo_u32 v10, s15, v2
; GCN-NEXT: v_mul_lo_u32 v11, s14, v2
; GCN-NEXT: v_mul_lo_u32 v12, s14, v7
; GCN-NEXT: v_mul_hi_u32 v13, v7, v11
; GCN-NEXT: v_mul_lo_u32 v14, v7, v11
; GCN-NEXT: v_mul_hi_u32 v11, v2, v11
; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GCN-NEXT: v_mul_hi_u32 v10, v7, v9
; GCN-NEXT: v_mul_hi_u32 v12, v2, v9
; GCN-NEXT: v_mul_lo_u32 v15, v2, v9
; GCN-NEXT: v_mul_lo_u32 v7, v7, v9
; GCN-NEXT: v_add_i32_e32 v9, vcc, v11, v15
; GCN-NEXT: v_addc_u32_e32 v11, vcc, v1, v12, vcc
; GCN-NEXT: v_add_i32_e32 v9, vcc, v14, v9
; GCN-NEXT: v_addc_u32_e32 v9, vcc, v11, v13, vcc
; GCN-NEXT: v_addc_u32_e32 v10, vcc, v10, v0, vcc
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v8
; GCN-NEXT: v_add_i32_e32 v7, vcc, v9, v7
; GCN-NEXT: v_addc_u32_e32 v8, vcc, v1, v10, vcc
; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v8, s[0:1]
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v7
; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; GCN-NEXT: v_mul_hi_u32 v7, s8, v2
; GCN-NEXT: v_mul_hi_u32 v8, s9, v2
; GCN-NEXT: v_mul_lo_u32 v2, s9, v2
; GCN-NEXT: v_mul_hi_u32 v9, s8, v3
; GCN-NEXT: v_mul_lo_u32 v10, s8, v3
; GCN-NEXT: v_mul_hi_u32 v11, s9, v3
; GCN-NEXT: v_mul_lo_u32 v3, s9, v3
; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; GCN-NEXT: v_addc_u32_e32 v9, vcc, v1, v9, vcc
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v7
; GCN-NEXT: v_addc_u32_e32 v2, vcc, v9, v8, vcc
; GCN-NEXT: v_addc_u32_e32 v0, vcc, v11, v0, vcc
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; GCN-NEXT: v_addc_u32_e32 v0, vcc, v1, v0, vcc
; GCN-NEXT: v_mul_hi_u32 v1, s2, v2
; GCN-NEXT: v_mul_lo_u32 v3, s3, v2
; GCN-NEXT: v_mul_lo_u32 v7, s2, v2
; GCN-NEXT: v_mul_lo_u32 v8, s2, v0
; GCN-NEXT: v_add_i32_e32 v9, vcc, 2, v2
; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v0, vcc
; GCN-NEXT: v_add_i32_e32 v11, vcc, 1, v2
; GCN-NEXT: v_addc_u32_e32 v12, vcc, 0, v0, vcc
; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v8
; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GCN-NEXT: v_sub_i32_e32 v3, vcc, s9, v1
; GCN-NEXT: v_sub_i32_e32 v7, vcc, s8, v7
; GCN-NEXT: v_subb_u32_e64 v3, s[0:1], v3, v4, vcc
; GCN-NEXT: v_subrev_i32_e64 v4, s[0:1], s2, v7
; GCN-NEXT: v_subb_u32_e32 v1, vcc, v6, v1, vcc
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v7
; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
; GCN-NEXT: v_subbrev_u32_e64 v3, vcc, 0, v3, s[0:1]
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v4
; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s3, v3
; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v1
; GCN-NEXT: v_cndmask_b32_e32 v1, v7, v6, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v3
; GCN-NEXT: v_cndmask_b32_e32 v3, v8, v4, vcc
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GCN-NEXT: v_cndmask_b32_e32 v3, v12, v10, vcc
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v1
; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1]
; GCN-NEXT: v_cndmask_b32_e32 v1, v11, v9, vcc
; GCN-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[0:1]
; GCN-NEXT: v_xor_b32_e32 v2, s13, v0
; GCN-NEXT: v_xor_b32_e32 v0, s12, v1
; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s12, v0
; GCN-NEXT: v_subb_u32_e32 v1, vcc, v2, v5, vcc
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-NEXT: s_endpgm
%result = sdiv i64 %x, %y
store i64 %result, i64 addrspace(1)* %out
ret void
}
define i64 @v_test_sdiv(i64 %x, i64 %y) {
; GCN-LABEL: v_test_sdiv:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_ashrrev_i32_e32 v4, 31, v3
; GCN-NEXT: v_mov_b32_e32 v5, 0
; GCN-NEXT: v_mov_b32_e32 v6, 0
; GCN-NEXT: v_ashrrev_i32_e32 v7, 31, v1
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v7
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v7, vcc
; GCN-NEXT: v_xor_b32_e32 v8, v7, v4
; GCN-NEXT: v_xor_b32_e32 v3, v3, v4
; GCN-NEXT: v_xor_b32_e32 v2, v2, v4
; GCN-NEXT: v_xor_b32_e32 v1, v1, v7
; GCN-NEXT: v_xor_b32_e32 v0, v0, v7
; GCN-NEXT: v_cvt_f32_u32_e32 v4, v2
; GCN-NEXT: v_cvt_f32_u32_e32 v7, v3
; GCN-NEXT: v_sub_i32_e32 v9, vcc, 0, v2
; GCN-NEXT: v_subb_u32_e32 v10, vcc, 0, v3, vcc
; GCN-NEXT: v_mac_f32_e32 v4, 0x4f800000, v7
; GCN-NEXT: v_rcp_f32_e32 v4, v4
; GCN-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
; GCN-NEXT: v_mul_f32_e32 v7, 0x2f800000, v4
; GCN-NEXT: v_trunc_f32_e32 v7, v7
; GCN-NEXT: v_mac_f32_e32 v4, 0xcf800000, v7
; GCN-NEXT: v_cvt_u32_f32_e32 v7, v7
; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4
; GCN-NEXT: v_mul_lo_u32 v11, v9, v7
; GCN-NEXT: v_mul_lo_u32 v12, v10, v4
; GCN-NEXT: v_mul_hi_u32 v13, v9, v4
; GCN-NEXT: v_mul_lo_u32 v14, v9, v4
; GCN-NEXT: v_add_i32_e32 v11, vcc, v13, v11
; GCN-NEXT: v_mul_hi_u32 v13, v4, v14
; GCN-NEXT: v_mul_hi_u32 v15, v7, v14
; GCN-NEXT: v_mul_lo_u32 v14, v7, v14
; GCN-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; GCN-NEXT: v_mul_hi_u32 v12, v4, v11
; GCN-NEXT: v_mul_lo_u32 v16, v4, v11
; GCN-NEXT: v_mul_hi_u32 v17, v7, v11
; GCN-NEXT: v_mul_lo_u32 v11, v7, v11
; GCN-NEXT: v_add_i32_e32 v13, vcc, v13, v16
; GCN-NEXT: v_addc_u32_e32 v12, vcc, v6, v12, vcc
; GCN-NEXT: v_add_i32_e32 v13, vcc, v14, v13
; GCN-NEXT: v_addc_u32_e32 v12, vcc, v12, v15, vcc
; GCN-NEXT: v_addc_u32_e32 v13, vcc, v17, v5, vcc
; GCN-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; GCN-NEXT: v_addc_u32_e32 v12, vcc, v6, v13, vcc
; GCN-NEXT: v_add_i32_e64 v4, s[4:5], v4, v11
; GCN-NEXT: v_addc_u32_e64 v11, vcc, v7, v12, s[4:5]
; GCN-NEXT: v_mul_hi_u32 v13, v9, v4
; GCN-NEXT: v_mul_lo_u32 v10, v10, v4
; GCN-NEXT: v_mul_lo_u32 v14, v9, v4
; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v12
; GCN-NEXT: v_mul_lo_u32 v9, v9, v11
; GCN-NEXT: v_mul_hi_u32 v12, v11, v14
; GCN-NEXT: v_mul_lo_u32 v15, v11, v14
; GCN-NEXT: v_mul_hi_u32 v14, v4, v14
; GCN-NEXT: v_add_i32_e32 v9, vcc, v13, v9
; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; GCN-NEXT: v_mul_hi_u32 v10, v11, v9
; GCN-NEXT: v_mul_hi_u32 v13, v4, v9
; GCN-NEXT: v_mul_lo_u32 v16, v4, v9
; GCN-NEXT: v_mul_lo_u32 v9, v11, v9
; GCN-NEXT: v_add_i32_e32 v11, vcc, v14, v16
; GCN-NEXT: v_addc_u32_e32 v13, vcc, v6, v13, vcc
; GCN-NEXT: v_add_i32_e32 v11, vcc, v15, v11
; GCN-NEXT: v_addc_u32_e32 v11, vcc, v13, v12, vcc
; GCN-NEXT: v_addc_u32_e32 v10, vcc, v10, v5, vcc
; GCN-NEXT: v_add_i32_e32 v9, vcc, v11, v9
; GCN-NEXT: v_addc_u32_e32 v10, vcc, v6, v10, vcc
; GCN-NEXT: v_addc_u32_e64 v7, vcc, v7, v10, s[4:5]
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v9
; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
; GCN-NEXT: v_mul_hi_u32 v9, v0, v4
; GCN-NEXT: v_mul_hi_u32 v10, v1, v4
; GCN-NEXT: v_mul_lo_u32 v4, v1, v4
; GCN-NEXT: v_mul_hi_u32 v11, v0, v7
; GCN-NEXT: v_mul_lo_u32 v12, v0, v7
; GCN-NEXT: v_mul_hi_u32 v13, v1, v7
; GCN-NEXT: v_mul_lo_u32 v7, v1, v7
; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; GCN-NEXT: v_addc_u32_e32 v11, vcc, v6, v11, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v9
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v11, v10, vcc
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v13, v5, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc
; GCN-NEXT: v_mul_hi_u32 v6, v2, v4
; GCN-NEXT: v_mul_lo_u32 v7, v3, v4
; GCN-NEXT: v_mul_lo_u32 v9, v2, v4
; GCN-NEXT: v_mul_lo_u32 v10, v2, v5
; GCN-NEXT: v_add_i32_e32 v11, vcc, 2, v4
; GCN-NEXT: v_addc_u32_e32 v12, vcc, 0, v5, vcc
; GCN-NEXT: v_add_i32_e32 v13, vcc, 1, v4
; GCN-NEXT: v_addc_u32_e32 v14, vcc, 0, v5, vcc
; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v10
; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7
; GCN-NEXT: v_sub_i32_e32 v7, vcc, v1, v6
; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v9
; GCN-NEXT: v_subb_u32_e64 v7, s[4:5], v7, v3, vcc
; GCN-NEXT: v_sub_i32_e64 v9, s[4:5], v0, v2
; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v6, vcc
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
; GCN-NEXT: v_subbrev_u32_e64 v6, vcc, 0, v7, s[4:5]
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v9, v2
; GCN-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v6, v3
; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
; GCN-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v6, v3
; GCN-NEXT: v_cndmask_b32_e32 v1, v9, v2, vcc
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
; GCN-NEXT: v_cndmask_b32_e32 v1, v14, v12, vcc
; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v0
; GCN-NEXT: v_cndmask_b32_e64 v0, v5, v1, s[4:5]
; GCN-NEXT: v_cndmask_b32_e32 v1, v13, v11, vcc
; GCN-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5]
; GCN-NEXT: v_xor_b32_e32 v2, v0, v8
; GCN-NEXT: v_xor_b32_e32 v0, v1, v8
; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v8
; GCN-NEXT: v_subb_u32_e32 v1, vcc, v2, v8, vcc
; GCN-NEXT: s_setpc_b64 s[30:31]
%result = sdiv i64 %x, %y
ret i64 %result
}
define amdgpu_kernel void @s_test_sdiv24_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
; GCN-LABEL: s_test_sdiv24_64:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-NEXT: s_load_dword s9, s[0:1], 0xe
; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s0, s4
; GCN-NEXT: s_mov_b32 s1, s5
; GCN-NEXT: s_ashr_i64 s[4:5], s[6:7], 40
; GCN-NEXT: s_ashr_i64 s[6:7], s[8:9], 40
; GCN-NEXT: s_xor_b32 s5, s4, s6
; GCN-NEXT: v_cvt_f32_i32_e32 v0, s6
; GCN-NEXT: v_cvt_f32_i32_e32 v1, s4
; GCN-NEXT: s_ashr_i32 s4, s5, 30
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
; GCN-NEXT: s_or_b32 s4, s4, 1
; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
; GCN-NEXT: v_trunc_f32_e32 v2, v2
; GCN-NEXT: v_mov_b32_e32 v3, s4
; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; GCN-NEXT: v_cvt_i32_f32_e32 v1, v2
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24
; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GCN-NEXT: s_endpgm
%1 = ashr i64 %x, 40
%2 = ashr i64 %y, 40
%result = sdiv i64 %1, %2
store i64 %result, i64 addrspace(1)* %out
ret void
}
define i64 @v_test_sdiv24_64(i64 %x, i64 %y) {
; GCN-LABEL: v_test_sdiv24_64:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_lshrrev_b32_e32 v0, 8, v1
; GCN-NEXT: v_lshrrev_b32_e32 v1, 8, v3
; GCN-NEXT: v_cvt_f32_u32_e32 v2, v1
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GCN-NEXT: v_mul_f32_e32 v2, 0x4f800000, v2
; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
; GCN-NEXT: v_mul_hi_u32 v3, v2, v1
; GCN-NEXT: v_mul_lo_u32 v4, v2, v1
; GCN-NEXT: v_sub_i32_e32 v5, vcc, 0, v4
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; GCN-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
; GCN-NEXT: v_mul_hi_u32 v3, v3, v2
; GCN-NEXT: v_add_i32_e64 v4, s[4:5], v2, v3
; GCN-NEXT: v_sub_i32_e64 v2, s[4:5], v2, v3
; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GCN-NEXT: v_mul_hi_u32 v2, v2, v0
; GCN-NEXT: v_mul_lo_u32 v3, v2, v1
; GCN-NEXT: v_add_i32_e32 v4, vcc, 1, v2
; GCN-NEXT: v_add_i32_e32 v5, vcc, -1, v2
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3
; GCN-NEXT: v_sub_i32_e64 v0, s[4:5], v0, v3
; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v1
; GCN-NEXT: s_and_b64 s[4:5], s[4:5], vcc
; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v4, s[4:5]
; GCN-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: s_setpc_b64 s[30:31]
%1 = lshr i64 %x, 40
%2 = lshr i64 %y, 40
%result = sdiv i64 %1, %2
ret i64 %result
}
define amdgpu_kernel void @s_test_sdiv32_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
; GCN-LABEL: s_test_sdiv32_64:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-NEXT: s_load_dword s2, s[0:1], 0xe
; GCN-NEXT: s_mov_b32 s11, 0xf000
; GCN-NEXT: s_mov_b32 s10, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s8, s4
; GCN-NEXT: s_mov_b32 s9, s5
; GCN-NEXT: s_ashr_i32 s3, s2, 31
; GCN-NEXT: s_ashr_i32 s4, s7, 31
; GCN-NEXT: s_add_i32 s2, s2, s3
; GCN-NEXT: s_add_i32 s0, s7, s4
; GCN-NEXT: s_xor_b32 s5, s2, s3
; GCN-NEXT: s_xor_b32 s2, s0, s4
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s5
; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
; GCN-NEXT: v_mul_hi_u32 v1, v0, s5
; GCN-NEXT: v_mul_lo_u32 v2, v0, s5
; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v2
; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v1
; GCN-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[0:1]
; GCN-NEXT: v_mul_hi_u32 v1, v1, v0
; GCN-NEXT: v_add_i32_e32 v2, vcc, v1, v0
; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0
; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; GCN-NEXT: v_mul_hi_u32 v0, v0, s2
; GCN-NEXT: v_mul_lo_u32 v1, v0, s5
; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0
; GCN-NEXT: v_add_i32_e32 v3, vcc, -1, v0
; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], s2, v1
; GCN-NEXT: v_sub_i32_e32 v1, vcc, s2, v1
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s5, v1
; GCN-NEXT: s_and_b64 vcc, vcc, s[0:1]
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GCN-NEXT: v_cndmask_b32_e64 v0, v3, v0, s[0:1]
; GCN-NEXT: s_xor_b32 s0, s4, s3
; GCN-NEXT: v_xor_b32_e32 v0, s0, v0
; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0
; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
; GCN-NEXT: s_endpgm
%1 = ashr i64 %x, 32
%2 = ashr i64 %y, 32
%result = sdiv i64 %1, %2
store i64 %result, i64 addrspace(1)* %out
ret void
}
define amdgpu_kernel void @s_test_sdiv31_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
; GCN-LABEL: s_test_sdiv31_64:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-NEXT: s_load_dword s3, s[0:1], 0xe
; GCN-NEXT: s_mov_b32 s11, 0xf000
; GCN-NEXT: s_mov_b32 s10, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s8, s4
; GCN-NEXT: s_mov_b32 s9, s5
; GCN-NEXT: s_ashr_i64 s[0:1], s[6:7], 33
; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 33
; GCN-NEXT: s_ashr_i32 s3, s2, 31
; GCN-NEXT: s_ashr_i32 s4, s0, 31
; GCN-NEXT: s_add_i32 s1, s2, s3
; GCN-NEXT: s_add_i32 s0, s0, s4
; GCN-NEXT: s_xor_b32 s5, s1, s3
; GCN-NEXT: s_xor_b32 s2, s0, s4
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s5
; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
; GCN-NEXT: v_mul_hi_u32 v1, v0, s5
; GCN-NEXT: v_mul_lo_u32 v2, v0, s5
; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v2
; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v1
; GCN-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[0:1]
; GCN-NEXT: v_mul_hi_u32 v1, v1, v0
; GCN-NEXT: v_add_i32_e32 v2, vcc, v1, v0
; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0
; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; GCN-NEXT: v_mul_hi_u32 v0, v0, s2
; GCN-NEXT: v_mul_lo_u32 v1, v0, s5
; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0
; GCN-NEXT: v_add_i32_e32 v3, vcc, -1, v0
; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], s2, v1
; GCN-NEXT: v_sub_i32_e32 v1, vcc, s2, v1
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s5, v1
; GCN-NEXT: s_and_b64 vcc, vcc, s[0:1]
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GCN-NEXT: v_cndmask_b32_e64 v0, v3, v0, s[0:1]
; GCN-NEXT: s_xor_b32 s0, s4, s3
; GCN-NEXT: v_xor_b32_e32 v0, s0, v0
; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0
; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
; GCN-NEXT: s_endpgm
%1 = ashr i64 %x, 33
%2 = ashr i64 %y, 33
%result = sdiv i64 %1, %2
store i64 %result, i64 addrspace(1)* %out
ret void
}
define amdgpu_kernel void @s_test_sdiv23_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
; GCN-LABEL: s_test_sdiv23_64:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-NEXT: s_load_dword s9, s[0:1], 0xe
; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s0, s4
; GCN-NEXT: s_mov_b32 s1, s5
; GCN-NEXT: s_ashr_i64 s[4:5], s[6:7], 41
; GCN-NEXT: s_ashr_i64 s[6:7], s[8:9], 41
; GCN-NEXT: s_xor_b32 s5, s4, s6
; GCN-NEXT: v_cvt_f32_i32_e32 v0, s6
; GCN-NEXT: v_cvt_f32_i32_e32 v1, s4
; GCN-NEXT: s_ashr_i32 s4, s5, 30
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
; GCN-NEXT: s_or_b32 s4, s4, 1
; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
; GCN-NEXT: v_trunc_f32_e32 v2, v2
; GCN-NEXT: v_mov_b32_e32 v3, s4
; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; GCN-NEXT: v_cvt_i32_f32_e32 v1, v2
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GCN-NEXT: v_bfe_i32 v0, v0, 0, 23
; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GCN-NEXT: s_endpgm
%1 = ashr i64 %x, 41
%2 = ashr i64 %y, 41
%result = sdiv i64 %1, %2
store i64 %result, i64 addrspace(1)* %out
ret void
}
define amdgpu_kernel void @s_test_sdiv25_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
; GCN-LABEL: s_test_sdiv25_64:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-NEXT: s_load_dword s3, s[0:1], 0xe
; GCN-NEXT: s_mov_b32 s11, 0xf000
; GCN-NEXT: s_mov_b32 s10, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s8, s4
; GCN-NEXT: s_mov_b32 s9, s5
; GCN-NEXT: s_ashr_i64 s[0:1], s[6:7], 39
; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 39
; GCN-NEXT: s_ashr_i32 s3, s2, 31
; GCN-NEXT: s_ashr_i32 s4, s0, 31
; GCN-NEXT: s_add_i32 s1, s2, s3
; GCN-NEXT: s_add_i32 s0, s0, s4
; GCN-NEXT: s_xor_b32 s5, s1, s3
; GCN-NEXT: s_xor_b32 s2, s0, s4
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s5
; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
; GCN-NEXT: v_mul_hi_u32 v1, v0, s5
; GCN-NEXT: v_mul_lo_u32 v2, v0, s5
; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v2
; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v1
; GCN-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[0:1]
; GCN-NEXT: v_mul_hi_u32 v1, v1, v0
; GCN-NEXT: v_add_i32_e32 v2, vcc, v1, v0
; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0
; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; GCN-NEXT: v_mul_hi_u32 v0, v0, s2
; GCN-NEXT: v_mul_lo_u32 v1, v0, s5
; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0
; GCN-NEXT: v_add_i32_e32 v3, vcc, -1, v0
; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], s2, v1
; GCN-NEXT: v_sub_i32_e32 v1, vcc, s2, v1
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s5, v1
; GCN-NEXT: s_and_b64 vcc, vcc, s[0:1]
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GCN-NEXT: v_cndmask_b32_e64 v0, v3, v0, s[0:1]
; GCN-NEXT: s_xor_b32 s0, s4, s3
; GCN-NEXT: v_xor_b32_e32 v0, s0, v0
; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0
; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
; GCN-NEXT: s_endpgm
%1 = ashr i64 %x, 39
%2 = ashr i64 %y, 39
%result = sdiv i64 %1, %2
store i64 %result, i64 addrspace(1)* %out
ret void
}
define amdgpu_kernel void @s_test_sdiv24_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
; GCN-LABEL: s_test_sdiv24_v2i64:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
; GCN-NEXT: s_load_dwordx4 s[12:15], s[0:1], 0x11
; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_ashr_i64 s[0:1], s[8:9], 40
; GCN-NEXT: s_ashr_i64 s[2:3], s[10:11], 40
; GCN-NEXT: s_ashr_i64 s[8:9], s[12:13], 40
; GCN-NEXT: s_ashr_i64 s[10:11], s[14:15], 40
; GCN-NEXT: s_xor_b32 s1, s2, s10
; GCN-NEXT: v_cvt_f32_i32_e32 v0, s2
; GCN-NEXT: v_cvt_f32_i32_e32 v1, s10
; GCN-NEXT: s_xor_b32 s2, s0, s8
; GCN-NEXT: v_cvt_f32_i32_e32 v2, s0
; GCN-NEXT: v_cvt_f32_i32_e32 v3, s8
; GCN-NEXT: s_ashr_i32 s0, s1, 30
; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v1
; GCN-NEXT: s_ashr_i32 s1, s2, 30
; GCN-NEXT: v_rcp_iflag_f32_e32 v5, v3
; GCN-NEXT: s_or_b32 s0, s0, 1
; GCN-NEXT: v_mul_f32_e32 v4, v0, v4
; GCN-NEXT: s_or_b32 s1, s1, 1
; GCN-NEXT: v_mul_f32_e32 v5, v2, v5
; GCN-NEXT: v_trunc_f32_e32 v4, v4
; GCN-NEXT: v_mov_b32_e32 v6, s0
; GCN-NEXT: v_trunc_f32_e32 v5, v5
; GCN-NEXT: v_mov_b32_e32 v7, s1
; GCN-NEXT: v_mad_f32 v0, -v4, v1, v0
; GCN-NEXT: v_cvt_i32_f32_e32 v4, v4
; GCN-NEXT: v_mad_f32 v2, -v5, v3, v2
; GCN-NEXT: v_cvt_i32_f32_e32 v5, v5
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, |v1|
; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, |v3|
; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v7, vcc
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v5
; GCN-NEXT: v_bfe_i32 v2, v0, 0, 24
; GCN-NEXT: v_bfe_i32 v0, v1, 0, 24
; GCN-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; GCN-NEXT: s_endpgm
%1 = ashr <2 x i64> %x, <i64 40, i64 40>
%2 = ashr <2 x i64> %y, <i64 40, i64 40>
%result = sdiv <2 x i64> %1, %2
store <2 x i64> %result, <2 x i64> addrspace(1)* %out
ret void
}
define amdgpu_kernel void @s_test_sdiv24_48(i48 addrspace(1)* %out, i48 %x, i48 %y) {
; GCN-LABEL: s_test_sdiv24_48:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GCN-NEXT: s_load_dword s2, s[0:1], 0xb
; GCN-NEXT: s_load_dword s3, s[0:1], 0xc
; GCN-NEXT: s_load_dword s8, s[0:1], 0xd
; GCN-NEXT: s_load_dword s9, s[0:1], 0xe
; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_sext_i32_i16 s0, s3
; GCN-NEXT: s_sext_i32_i16 s1, s9
; GCN-NEXT: v_mov_b32_e32 v0, s8
; GCN-NEXT: v_mov_b32_e32 v1, s2
; GCN-NEXT: v_alignbit_b32 v0, s1, v0, 24
; GCN-NEXT: v_alignbit_b32 v1, s0, v1, 24
; GCN-NEXT: v_xor_b32_e32 v2, v1, v0
; GCN-NEXT: v_cvt_f32_i32_e32 v1, v1
; GCN-NEXT: v_cvt_f32_i32_e32 v0, v0
; GCN-NEXT: v_ashrrev_i32_e32 v2, 30, v2
; GCN-NEXT: v_rcp_iflag_f32_e32 v3, v0
; GCN-NEXT: v_or_b32_e32 v2, 1, v2
; GCN-NEXT: v_mul_f32_e32 v3, v1, v3
; GCN-NEXT: v_trunc_f32_e32 v3, v3
; GCN-NEXT: v_mad_f32 v1, -v3, v0, v1
; GCN-NEXT: v_cvt_i32_f32_e32 v3, v3
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24
; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GCN-NEXT: buffer_store_short v1, off, s[4:7], 0 offset:4
; GCN-NEXT: s_endpgm
%1 = ashr i48 %x, 24
%2 = ashr i48 %y, 24
%result = sdiv i48 %1, %2
store i48 %result, i48 addrspace(1)* %out
ret void
}
define amdgpu_kernel void @s_test_sdiv_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
; GCN-LABEL: s_test_sdiv_k_num_i64:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_ashr_i32 s2, s11, 31
; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: s_mov_b32 s4, s8
; GCN-NEXT: s_mov_b32 s5, s9
; GCN-NEXT: s_mov_b32 s3, s2
; GCN-NEXT: s_add_u32 s0, s10, s2
; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: s_addc_u32 s1, s11, s2
; GCN-NEXT: s_xor_b64 s[8:9], s[0:1], s[2:3]
; GCN-NEXT: v_cvt_f32_u32_e32 v3, s8
; GCN-NEXT: v_cvt_f32_u32_e32 v4, s9
; GCN-NEXT: s_sub_u32 s3, 0, s8
; GCN-NEXT: v_mov_b32_e32 v5, s9
; GCN-NEXT: v_mac_f32_e32 v3, 0x4f800000, v4
; GCN-NEXT: s_subb_u32 s10, 0, s9
; GCN-NEXT: v_rcp_f32_e32 v3, v3
; GCN-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v3
; GCN-NEXT: v_mul_f32_e32 v4, 0x2f800000, v3
; GCN-NEXT: v_trunc_f32_e32 v4, v4
; GCN-NEXT: v_mac_f32_e32 v3, 0xcf800000, v4
; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4
; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
; GCN-NEXT: v_mul_lo_u32 v6, s3, v4
; GCN-NEXT: v_mul_lo_u32 v7, s10, v3
; GCN-NEXT: v_mul_hi_u32 v8, s3, v3
; GCN-NEXT: v_mul_lo_u32 v9, s3, v3
; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; GCN-NEXT: v_mul_hi_u32 v8, v3, v9
; GCN-NEXT: v_mul_hi_u32 v10, v4, v9
; GCN-NEXT: v_mul_lo_u32 v9, v4, v9
; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7
; GCN-NEXT: v_mul_hi_u32 v7, v3, v6
; GCN-NEXT: v_mul_lo_u32 v11, v3, v6
; GCN-NEXT: v_mul_hi_u32 v12, v4, v6
; GCN-NEXT: v_mul_lo_u32 v6, v4, v6
; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v11
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v1, v7, vcc
; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v10, vcc
; GCN-NEXT: v_addc_u32_e32 v8, vcc, v12, v0, vcc
; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v1, v8, vcc
; GCN-NEXT: v_add_i32_e64 v3, s[0:1], v3, v6
; GCN-NEXT: v_addc_u32_e64 v6, vcc, v4, v7, s[0:1]
; GCN-NEXT: v_mul_hi_u32 v8, s3, v3
; GCN-NEXT: v_mul_lo_u32 v9, s10, v3
; GCN-NEXT: v_mul_lo_u32 v10, s3, v3
; GCN-NEXT: v_mul_lo_u32 v11, s3, v6
; GCN-NEXT: v_mul_hi_u32 v12, v6, v10
; GCN-NEXT: v_mul_lo_u32 v13, v6, v10
; GCN-NEXT: v_mul_hi_u32 v10, v3, v10
; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v11
; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GCN-NEXT: v_mul_hi_u32 v9, v6, v8
; GCN-NEXT: v_mul_hi_u32 v11, v3, v8
; GCN-NEXT: v_mul_lo_u32 v14, v3, v8
; GCN-NEXT: v_mul_lo_u32 v6, v6, v8
; GCN-NEXT: v_add_i32_e32 v8, vcc, v10, v14
; GCN-NEXT: v_addc_u32_e32 v10, vcc, v1, v11, vcc
; GCN-NEXT: v_add_i32_e32 v8, vcc, v13, v8
; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v12, vcc
; GCN-NEXT: v_addc_u32_e32 v9, vcc, v9, v0, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7
; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v1, v9, vcc
; GCN-NEXT: v_addc_u32_e64 v4, vcc, v4, v7, s[0:1]
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6
; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc
; GCN-NEXT: v_mul_hi_u32 v6, 24, v3
; GCN-NEXT: v_mul_hi_u32 v3, 0, v3
; GCN-NEXT: v_mul_hi_u32 v7, 24, v4
; GCN-NEXT: v_mul_lo_u32 v8, v4, 24
; GCN-NEXT: v_mul_hi_u32 v4, 0, v4
; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v7, vcc
; GCN-NEXT: v_add_i32_e32 v6, vcc, 0, v6
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GCN-NEXT: v_addc_u32_e32 v0, vcc, v4, v0, vcc
; GCN-NEXT: v_mul_hi_u32 v3, s8, v1
; GCN-NEXT: v_mul_lo_u32 v4, s9, v1
; GCN-NEXT: v_mul_lo_u32 v6, s8, v1
; GCN-NEXT: v_mul_lo_u32 v7, s8, v0
; GCN-NEXT: v_add_i32_e32 v8, vcc, 2, v1
; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v0, vcc
; GCN-NEXT: v_add_i32_e32 v10, vcc, 1, v1
; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v0, vcc
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v7
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v4
; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v3
; GCN-NEXT: v_sub_i32_e32 v6, vcc, 24, v6
; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
; GCN-NEXT: v_subrev_i32_e64 v5, s[0:1], s8, v6
; GCN-NEXT: v_subb_u32_e32 v3, vcc, 0, v3, vcc
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s8, v6
; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
; GCN-NEXT: v_subbrev_u32_e64 v4, vcc, 0, v4, s[0:1]
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s8, v5
; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s9, v3
; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s9, v4
; GCN-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s9, v3
; GCN-NEXT: v_cndmask_b32_e32 v3, v7, v6, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s9, v4
; GCN-NEXT: v_cndmask_b32_e32 v4, v12, v5, vcc
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; GCN-NEXT: v_cndmask_b32_e32 v4, v11, v9, vcc
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v3
; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1]
; GCN-NEXT: v_cndmask_b32_e32 v3, v10, v8, vcc
; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
; GCN-NEXT: v_xor_b32_e32 v3, s2, v0
; GCN-NEXT: v_xor_b32_e32 v0, s2, v1
; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0
; GCN-NEXT: v_subb_u32_e32 v1, vcc, v3, v2, vcc
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-NEXT: s_endpgm
%result = sdiv i64 24, %x
store i64 %result, i64 addrspace(1)* %out
ret void
}
define i64 @v_test_sdiv_k_num_i64(i64 %x) {
; GCN-LABEL: v_test_sdiv_k_num_i64:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_ashrrev_i32_e32 v2, 31, v1
; GCN-NEXT: v_mov_b32_e32 v3, 0
; GCN-NEXT: v_mov_b32_e32 v4, 0
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; GCN-NEXT: v_xor_b32_e32 v1, v1, v2
; GCN-NEXT: v_xor_b32_e32 v0, v0, v2
; GCN-NEXT: v_cvt_f32_u32_e32 v5, v0
; GCN-NEXT: v_cvt_f32_u32_e32 v6, v1
; GCN-NEXT: v_sub_i32_e32 v7, vcc, 0, v0
; GCN-NEXT: v_subb_u32_e32 v8, vcc, 0, v1, vcc
; GCN-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6
; GCN-NEXT: v_rcp_f32_e32 v5, v5
; GCN-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5
; GCN-NEXT: v_mul_f32_e32 v6, 0x2f800000, v5
; GCN-NEXT: v_trunc_f32_e32 v6, v6
; GCN-NEXT: v_mac_f32_e32 v5, 0xcf800000, v6
; GCN-NEXT: v_cvt_u32_f32_e32 v6, v6
; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5
; GCN-NEXT: v_mul_lo_u32 v9, v7, v6
; GCN-NEXT: v_mul_lo_u32 v10, v8, v5
; GCN-NEXT: v_mul_hi_u32 v11, v7, v5
; GCN-NEXT: v_mul_lo_u32 v12, v7, v5
; GCN-NEXT: v_add_i32_e32 v9, vcc, v11, v9
; GCN-NEXT: v_mul_hi_u32 v11, v5, v12
; GCN-NEXT: v_mul_hi_u32 v13, v6, v12
; GCN-NEXT: v_mul_lo_u32 v12, v6, v12
; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; GCN-NEXT: v_mul_hi_u32 v10, v5, v9
; GCN-NEXT: v_mul_lo_u32 v14, v5, v9
; GCN-NEXT: v_mul_hi_u32 v15, v6, v9
; GCN-NEXT: v_mul_lo_u32 v9, v6, v9
; GCN-NEXT: v_add_i32_e32 v11, vcc, v11, v14
; GCN-NEXT: v_addc_u32_e32 v10, vcc, v4, v10, vcc
; GCN-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; GCN-NEXT: v_addc_u32_e32 v10, vcc, v10, v13, vcc
; GCN-NEXT: v_addc_u32_e32 v11, vcc, v15, v3, vcc
; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GCN-NEXT: v_addc_u32_e32 v10, vcc, v4, v11, vcc
; GCN-NEXT: v_add_i32_e64 v5, s[4:5], v5, v9
; GCN-NEXT: v_addc_u32_e64 v9, vcc, v6, v10, s[4:5]
; GCN-NEXT: v_mul_hi_u32 v11, v7, v5
; GCN-NEXT: v_mul_lo_u32 v8, v8, v5
; GCN-NEXT: v_mul_lo_u32 v12, v7, v5
; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v10
; GCN-NEXT: v_mul_lo_u32 v7, v7, v9
; GCN-NEXT: v_mul_hi_u32 v10, v9, v12
; GCN-NEXT: v_mul_lo_u32 v13, v9, v12
; GCN-NEXT: v_mul_hi_u32 v12, v5, v12
; GCN-NEXT: v_add_i32_e32 v7, vcc, v11, v7
; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GCN-NEXT: v_mul_hi_u32 v8, v9, v7
; GCN-NEXT: v_mul_hi_u32 v11, v5, v7
; GCN-NEXT: v_mul_lo_u32 v14, v5, v7
; GCN-NEXT: v_mul_lo_u32 v7, v9, v7
; GCN-NEXT: v_add_i32_e32 v9, vcc, v12, v14
; GCN-NEXT: v_addc_u32_e32 v11, vcc, v4, v11, vcc
; GCN-NEXT: v_add_i32_e32 v9, vcc, v13, v9
; GCN-NEXT: v_addc_u32_e32 v9, vcc, v11, v10, vcc
; GCN-NEXT: v_addc_u32_e32 v8, vcc, v8, v3, vcc
; GCN-NEXT: v_add_i32_e32 v7, vcc, v9, v7
; GCN-NEXT: v_addc_u32_e32 v8, vcc, v4, v8, vcc
; GCN-NEXT: v_addc_u32_e64 v6, vcc, v6, v8, s[4:5]
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc
; GCN-NEXT: v_mul_hi_u32 v7, 24, v5
; GCN-NEXT: v_mul_hi_u32 v5, 0, v5
; GCN-NEXT: v_mul_hi_u32 v8, 24, v6
; GCN-NEXT: v_mul_lo_u32 v9, v6, 24
; GCN-NEXT: v_mul_hi_u32 v6, 0, v6
; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v4, v8, vcc
; GCN-NEXT: v_add_i32_e32 v7, vcc, 0, v7
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v4, v5, vcc
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v6, v3, vcc
; GCN-NEXT: v_mul_hi_u32 v5, v0, v4
; GCN-NEXT: v_mul_lo_u32 v6, v1, v4
; GCN-NEXT: v_mul_lo_u32 v7, v0, v4
; GCN-NEXT: v_mul_lo_u32 v8, v0, v3
; GCN-NEXT: v_add_i32_e32 v9, vcc, 2, v4
; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v3, vcc
; GCN-NEXT: v_add_i32_e32 v11, vcc, 1, v4
; GCN-NEXT: v_addc_u32_e32 v12, vcc, 0, v3, vcc
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; GCN-NEXT: v_sub_i32_e32 v6, vcc, 0, v5
; GCN-NEXT: v_sub_i32_e32 v7, vcc, 24, v7
; GCN-NEXT: v_subb_u32_e64 v6, s[4:5], v6, v1, vcc
; GCN-NEXT: v_sub_i32_e64 v8, s[4:5], v7, v0
; GCN-NEXT: v_subb_u32_e32 v5, vcc, 0, v5, vcc
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v7, v0
; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
; GCN-NEXT: v_subbrev_u32_e64 v6, vcc, 0, v6, s[4:5]
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v8, v0
; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v5, v1
; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v6, v1
; GCN-NEXT: v_cndmask_b32_e64 v13, 0, -1, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v5, v1
; GCN-NEXT: v_cndmask_b32_e32 v5, v8, v7, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v6, v1
; GCN-NEXT: v_cndmask_b32_e32 v0, v13, v0, vcc
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GCN-NEXT: v_cndmask_b32_e32 v0, v12, v10, vcc
; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v5
; GCN-NEXT: v_cndmask_b32_e64 v0, v3, v0, s[4:5]
; GCN-NEXT: v_cndmask_b32_e32 v1, v11, v9, vcc
; GCN-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5]
; GCN-NEXT: v_xor_b32_e32 v3, v0, v2
; GCN-NEXT: v_xor_b32_e32 v0, v1, v2
; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GCN-NEXT: v_subb_u32_e32 v1, vcc, v3, v2, vcc
; GCN-NEXT: s_setpc_b64 s[30:31]
%result = sdiv i64 24, %x
ret i64 %result
}
define i64 @v_test_sdiv_pow2_k_num_i64(i64 %x) {
; GCN-LABEL: v_test_sdiv_pow2_k_num_i64:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_ashrrev_i32_e32 v2, 31, v1
; GCN-NEXT: v_mov_b32_e32 v3, 0
; GCN-NEXT: v_mov_b32_e32 v4, 0
; GCN-NEXT: s_mov_b32 s6, 0x8000
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; GCN-NEXT: v_xor_b32_e32 v1, v1, v2
; GCN-NEXT: v_xor_b32_e32 v0, v0, v2
; GCN-NEXT: v_cvt_f32_u32_e32 v5, v0
; GCN-NEXT: v_cvt_f32_u32_e32 v6, v1
; GCN-NEXT: v_sub_i32_e32 v7, vcc, 0, v0
; GCN-NEXT: v_subb_u32_e32 v8, vcc, 0, v1, vcc
; GCN-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6
; GCN-NEXT: v_rcp_f32_e32 v5, v5
; GCN-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5
; GCN-NEXT: v_mul_f32_e32 v6, 0x2f800000, v5
; GCN-NEXT: v_trunc_f32_e32 v6, v6
; GCN-NEXT: v_mac_f32_e32 v5, 0xcf800000, v6
; GCN-NEXT: v_cvt_u32_f32_e32 v6, v6
; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5
; GCN-NEXT: v_mul_lo_u32 v9, v7, v6
; GCN-NEXT: v_mul_lo_u32 v10, v8, v5
; GCN-NEXT: v_mul_hi_u32 v11, v7, v5
; GCN-NEXT: v_mul_lo_u32 v12, v7, v5
; GCN-NEXT: v_add_i32_e32 v9, vcc, v11, v9
; GCN-NEXT: v_mul_hi_u32 v11, v5, v12
; GCN-NEXT: v_mul_hi_u32 v13, v6, v12
; GCN-NEXT: v_mul_lo_u32 v12, v6, v12
; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; GCN-NEXT: v_mul_hi_u32 v10, v5, v9
; GCN-NEXT: v_mul_lo_u32 v14, v5, v9
; GCN-NEXT: v_mul_hi_u32 v15, v6, v9
; GCN-NEXT: v_mul_lo_u32 v9, v6, v9
; GCN-NEXT: v_add_i32_e32 v11, vcc, v11, v14
; GCN-NEXT: v_addc_u32_e32 v10, vcc, v4, v10, vcc
; GCN-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; GCN-NEXT: v_addc_u32_e32 v10, vcc, v10, v13, vcc
; GCN-NEXT: v_addc_u32_e32 v11, vcc, v15, v3, vcc
; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GCN-NEXT: v_addc_u32_e32 v10, vcc, v4, v11, vcc
; GCN-NEXT: v_add_i32_e64 v5, s[4:5], v5, v9
; GCN-NEXT: v_addc_u32_e64 v9, vcc, v6, v10, s[4:5]
; GCN-NEXT: v_mul_hi_u32 v11, v7, v5
; GCN-NEXT: v_mul_lo_u32 v8, v8, v5
; GCN-NEXT: v_mul_lo_u32 v12, v7, v5
; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v10
; GCN-NEXT: v_mul_lo_u32 v7, v7, v9
; GCN-NEXT: v_mul_hi_u32 v10, v9, v12
; GCN-NEXT: v_mul_lo_u32 v13, v9, v12
; GCN-NEXT: v_mul_hi_u32 v12, v5, v12
; GCN-NEXT: v_add_i32_e32 v7, vcc, v11, v7
; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GCN-NEXT: v_mul_hi_u32 v8, v9, v7
; GCN-NEXT: v_mul_hi_u32 v11, v5, v7
; GCN-NEXT: v_mul_lo_u32 v14, v5, v7
; GCN-NEXT: v_mul_lo_u32 v7, v9, v7
; GCN-NEXT: v_add_i32_e32 v9, vcc, v12, v14
; GCN-NEXT: v_addc_u32_e32 v11, vcc, v4, v11, vcc
; GCN-NEXT: v_add_i32_e32 v9, vcc, v13, v9
; GCN-NEXT: v_addc_u32_e32 v9, vcc, v11, v10, vcc
; GCN-NEXT: v_addc_u32_e32 v8, vcc, v8, v3, vcc
; GCN-NEXT: v_add_i32_e32 v7, vcc, v9, v7
; GCN-NEXT: v_addc_u32_e32 v8, vcc, v4, v8, vcc
; GCN-NEXT: v_addc_u32_e64 v6, vcc, v6, v8, s[4:5]
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc
; GCN-NEXT: v_mul_hi_u32 v7, s6, v5
; GCN-NEXT: v_mul_hi_u32 v5, 0, v5
; GCN-NEXT: v_mul_hi_u32 v8, s6, v6
; GCN-NEXT: v_lshlrev_b32_e32 v9, 15, v6
; GCN-NEXT: v_mul_hi_u32 v6, 0, v6
; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v4, v8, vcc
; GCN-NEXT: v_add_i32_e32 v7, vcc, 0, v7
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v4, v5, vcc
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v6, v3, vcc
; GCN-NEXT: v_mul_hi_u32 v5, v0, v4
; GCN-NEXT: v_mul_lo_u32 v6, v1, v4
; GCN-NEXT: v_mul_lo_u32 v7, v0, v4
; GCN-NEXT: v_mul_lo_u32 v8, v0, v3
; GCN-NEXT: v_add_i32_e32 v9, vcc, 2, v4
; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v3, vcc
; GCN-NEXT: v_add_i32_e32 v11, vcc, 1, v4
; GCN-NEXT: v_addc_u32_e32 v12, vcc, 0, v3, vcc
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; GCN-NEXT: v_sub_i32_e32 v6, vcc, 0, v5
; GCN-NEXT: v_sub_i32_e32 v7, vcc, s6, v7
; GCN-NEXT: v_subb_u32_e64 v6, s[4:5], v6, v1, vcc
; GCN-NEXT: v_sub_i32_e64 v8, s[4:5], v7, v0
; GCN-NEXT: v_subb_u32_e32 v5, vcc, 0, v5, vcc
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v7, v0
; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
; GCN-NEXT: v_subbrev_u32_e64 v6, vcc, 0, v6, s[4:5]
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v8, v0
; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v5, v1
; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v6, v1
; GCN-NEXT: v_cndmask_b32_e64 v13, 0, -1, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v5, v1
; GCN-NEXT: v_cndmask_b32_e32 v5, v8, v7, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v6, v1
; GCN-NEXT: v_cndmask_b32_e32 v0, v13, v0, vcc
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GCN-NEXT: v_cndmask_b32_e32 v0, v12, v10, vcc
; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v5
; GCN-NEXT: v_cndmask_b32_e64 v0, v3, v0, s[4:5]
; GCN-NEXT: v_cndmask_b32_e32 v1, v11, v9, vcc
; GCN-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5]
; GCN-NEXT: v_xor_b32_e32 v3, v0, v2
; GCN-NEXT: v_xor_b32_e32 v0, v1, v2
; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GCN-NEXT: v_subb_u32_e32 v1, vcc, v3, v2, vcc
; GCN-NEXT: s_setpc_b64 s[30:31]
%result = sdiv i64 32768, %x
ret i64 %result
}
define i64 @v_test_sdiv_pow2_k_den_i64(i64 %x) {
; GCN-LABEL: v_test_sdiv_pow2_k_den_i64:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_ashrrev_i32_e32 v2, 31, v1
; GCN-NEXT: v_lshrrev_b32_e32 v2, 17, v2
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-NEXT: v_ashr_i64 v[0:1], v[0:1], 15
; GCN-NEXT: s_setpc_b64 s[30:31]
%result = sdiv i64 %x, 32768
ret i64 %result
}
define amdgpu_kernel void @s_test_sdiv24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
; GCN-LABEL: s_test_sdiv24_k_num_i64:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s2, 0x41c00000
; GCN-NEXT: s_mov_b32 s4, s0
; GCN-NEXT: s_mov_b32 s5, s1
; GCN-NEXT: s_ashr_i64 s[0:1], s[2:3], 40
; GCN-NEXT: v_cvt_f32_i32_e32 v0, s0
; GCN-NEXT: s_ashr_i32 s0, s0, 30
; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0
; GCN-NEXT: s_or_b32 s0, s0, 1
; GCN-NEXT: v_mul_f32_e32 v1, s2, v1
; GCN-NEXT: v_mov_b32_e32 v2, s0
; GCN-NEXT: v_trunc_f32_e32 v1, v1
; GCN-NEXT: v_mad_f32 v3, -v1, v0, s2
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v0|
; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GCN-NEXT: v_cvt_i32_f32_e32 v1, v1
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24
; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-NEXT: s_endpgm
%x.shr = ashr i64 %x, 40
%result = sdiv i64 24, %x.shr
store i64 %result, i64 addrspace(1)* %out
ret void
}
define amdgpu_kernel void @s_test_sdiv24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
; GCN-LABEL: s_test_sdiv24_k_den_i64:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s2, 0x46b6fe00
; GCN-NEXT: s_mov_b32 s4, s0
; GCN-NEXT: s_mov_b32 s5, s1
; GCN-NEXT: s_ashr_i64 s[0:1], s[2:3], 40
; GCN-NEXT: v_cvt_f32_i32_e32 v0, s0
; GCN-NEXT: s_ashr_i32 s0, s0, 30
; GCN-NEXT: v_mul_f32_e32 v1, 0x38331158, v0
; GCN-NEXT: s_or_b32 s0, s0, 1
; GCN-NEXT: v_trunc_f32_e32 v1, v1
; GCN-NEXT: v_mov_b32_e32 v2, s0
; GCN-NEXT: v_mad_f32 v0, -v1, s2, v0
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s2
; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GCN-NEXT: v_cvt_i32_f32_e32 v1, v1
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24
; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-NEXT: s_endpgm
%x.shr = ashr i64 %x, 40
%result = sdiv i64 %x.shr, 23423
store i64 %result, i64 addrspace(1)* %out
ret void
}
define i64 @v_test_sdiv24_k_num_i64(i64 %x) {
; GCN-LABEL: v_test_sdiv24_k_num_i64:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_ashr_i64 v[0:1], v[0:1], 40
; GCN-NEXT: s_mov_b32 s4, 0x41c00000
; GCN-NEXT: v_cvt_f32_i32_e32 v1, v0
; GCN-NEXT: v_ashrrev_i32_e32 v0, 30, v0
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1
; GCN-NEXT: v_or_b32_e32 v0, 1, v0
; GCN-NEXT: v_mul_f32_e32 v2, s4, v2
; GCN-NEXT: v_trunc_f32_e32 v2, v2
; GCN-NEXT: v_mad_f32 v3, -v2, v1, s4
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v1|
; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; GCN-NEXT: v_cvt_i32_f32_e32 v1, v2
; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0
; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24
; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-NEXT: s_setpc_b64 s[30:31]
%x.shr = ashr i64 %x, 40
%result = sdiv i64 24, %x.shr
ret i64 %result
}
define i64 @v_test_sdiv24_pow2_k_num_i64(i64 %x) {
; GCN-LABEL: v_test_sdiv24_pow2_k_num_i64:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_ashr_i64 v[0:1], v[0:1], 40
; GCN-NEXT: s_mov_b32 s4, 0x47000000
; GCN-NEXT: v_cvt_f32_i32_e32 v1, v0
; GCN-NEXT: v_ashrrev_i32_e32 v0, 30, v0
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1
; GCN-NEXT: v_or_b32_e32 v0, 1, v0
; GCN-NEXT: v_mul_f32_e32 v2, s4, v2
; GCN-NEXT: v_trunc_f32_e32 v2, v2
; GCN-NEXT: v_mad_f32 v3, -v2, v1, s4
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v1|
; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; GCN-NEXT: v_cvt_i32_f32_e32 v1, v2
; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0
; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24
; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-NEXT: s_setpc_b64 s[30:31]
%x.shr = ashr i64 %x, 40
%result = sdiv i64 32768, %x.shr
ret i64 %result
}
define i64 @v_test_sdiv24_pow2_k_den_i64(i64 %x) {
; GCN-LABEL: v_test_sdiv24_pow2_k_den_i64:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
[TargetLowering] SimplifyDemandedBits - Remove ashr if all our demandedbits already match the sign bit Differential Revision: https://reviews.llvm.org/D73412
2020-01-26 01:36:21 +08:00
; GCN-NEXT: v_ashr_i64 v[0:1], v[0:1], 40
; GCN-NEXT: v_lshrrev_b32_e32 v2, 17, v1
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
AMDGPU: Cleanup and generate 64-bit div tests Split out r600 tests, and try to be more consistent with coverage. Cover a few more cases for 24-bit optimization and constants.
2020-01-19 05:51:43 +08:00
; GCN-NEXT: v_ashr_i64 v[0:1], v[0:1], 15
; GCN-NEXT: s_setpc_b64 s[30:31]
%x.shr = ashr i64 %x, 40
%result = sdiv i64 %x.shr, 32768
ret i64 %result
}