forked from OSchip/llvm-project
34 lines
1004 B
LLVM
34 lines
1004 B
LLVM
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; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
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; We do not want to see a 'cannot select' error,
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; we would like to see a vasrh instruction
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; CHECK: vasrh
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target triple = "hexagon"
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@g0 = global [6 x i64] [i64 0, i64 1, i64 10000, i64 -9223372036854775808, i64 9223372036854775807, i64 -1], align 8
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@g1 = common global i32 0, align 4
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; Function Attrs: nounwind
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define i32 @f0() #0 {
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b0:
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%v0 = load i64, i64* getelementptr inbounds ([6 x i64], [6 x i64]* @g0, i32 0, i32 0), align 8, !tbaa !0
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%v1 = tail call i64 @llvm.hexagon.S2.asr.i.vh(i64 %v0, i32 62)
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%v2 = trunc i64 %v1 to i32
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store i32 %v2, i32* @g1, align 4, !tbaa !4
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ret i32 0
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}
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; Function Attrs: nounwind readnone
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declare i64 @llvm.hexagon.S2.asr.i.vh(i64, i32) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv55" }
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attributes #1 = { nounwind readnone }
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!0 = !{!1, !1, i64 0}
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!1 = !{!"long long", !2, i64 0}
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!2 = !{!"omnipotent char", !3, i64 0}
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!3 = !{!"Simple C/C++ TBAA"}
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!4 = !{!5, !5, i64 0}
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!5 = !{!"int", !2, i64 0}
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