forked from OSchip/llvm-project
30 lines
818 B
LLVM
30 lines
818 B
LLVM
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; RUN: llc -march=hexagon -O2 -disable-hexagon-shuffle=1 < %s | FileCheck %s
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; CHECK: q{{[0-3]}} = vsetq(r{{[0-9]+}})
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target triple = "hexagon"
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; Function Attrs: nounwind
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define void @f0(i32 %a0, <16 x i32> %a1) #0 {
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b0:
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%v0 = alloca i32, align 4
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%v1 = alloca <16 x i32>, align 64
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%v2 = alloca <16 x i32>, align 64
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store i32 %a0, i32* %v0, align 4
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store <16 x i32> %a1, <16 x i32>* %v1, align 64
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%v3 = load i32, i32* %v0, align 4
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%v4 = load <16 x i32>, <16 x i32>* %v2, align 64
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call void asm sideeffect " $1 = vsetq($0);\0A", "r,q"(i32 %v3, <16 x i32> %v4) #1, !srcloc !0
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ret void
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}
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; Function Attrs: nounwind
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define i32 @f1() #0 {
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b0:
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ret i32 0
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
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attributes #1 = { nounwind }
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!0 = !{i32 222}
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