forked from OSchip/llvm-project
74 lines
2.3 KiB
LLVM
74 lines
2.3 KiB
LLVM
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; RUN: llc -march=hexagon -enable-pipeliner < %s
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; REQUIRES: asserts
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; Make sure we fix up the Phis when we connect the last
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; epilog block to the CFG.
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define void @f0(i16* nocapture %a0) #0 {
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b0:
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br i1 undef, label %b1, label %b2
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b1: ; preds = %b0
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br label %b3
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b2: ; preds = %b0
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unreachable
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b3: ; preds = %b3, %b1
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br i1 undef, label %b4, label %b3
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b4: ; preds = %b3
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br i1 undef, label %b6, label %b5
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b5: ; preds = %b4
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store i16 4096, i16* %a0, align 2
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br label %b11
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b6: ; preds = %b4
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br i1 undef, label %b7, label %b8
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b7: ; preds = %b7, %b6
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br label %b7
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b8: ; preds = %b8, %b6
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br i1 undef, label %b9, label %b8
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b9: ; preds = %b8
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%v0 = icmp sgt i32 undef, 1
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br i1 %v0, label %b10, label %b11
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b10: ; preds = %b10, %b9
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%v1 = phi i32 [ %v8, %b10 ], [ 1, %b9 ]
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%v2 = getelementptr inbounds [11 x i32], [11 x i32]* undef, i32 0, i32 %v1
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%v3 = load i32, i32* undef, align 4
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%v4 = add nsw i32 %v3, 0
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%v5 = add nsw i32 %v4, 2048
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%v6 = lshr i32 %v5, 12
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%v7 = trunc i32 %v6 to i16
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store i16 %v7, i16* undef, align 2
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%v8 = add nsw i32 %v1, 1
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%v9 = icmp eq i32 %v8, undef
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br i1 %v9, label %b11, label %b10
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b11: ; preds = %b10, %b9, %b5
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%v10 = phi i1 [ false, %b9 ], [ false, %b5 ], [ %v0, %b10 ]
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br i1 undef, label %b16, label %b12
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b12: ; preds = %b11
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br i1 undef, label %b13, label %b16
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b13: ; preds = %b12
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br i1 %v10, label %b14, label %b15
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b14: ; preds = %b14, %b13
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br i1 undef, label %b15, label %b14
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b15: ; preds = %b14, %b13
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br label %b16
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b16: ; preds = %b15, %b12, %b11
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ret void
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv55" }
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