forked from OSchip/llvm-project
91 lines
3.3 KiB
LLVM
91 lines
3.3 KiB
LLVM
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; RUN: llc -march=hexagon -enable-pipeliner < %s
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; REQUIRES: asserts
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; Test that the pipeliner doesn't ICE due to incorrect PHI
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; generation code that attemps to reuse an exsting PHI.
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; Similar to the other swp-epillog-reuse test, but from a
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; different test case.
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.S2.asl.r.r.sat(i32, i32) #0
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; Function Attrs: nounwind
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define void @f0() #1 {
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b0:
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br label %b1
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b1: ; preds = %b1, %b0
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br i1 undef, label %b2, label %b1
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b2: ; preds = %b2, %b1
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br i1 undef, label %b3, label %b2
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b3: ; preds = %b3, %b2
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%v0 = phi i16 [ %v10, %b3 ], [ undef, %b2 ]
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%v1 = phi i16 [ %v0, %b3 ], [ undef, %b2 ]
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%v2 = phi i32 [ %v26, %b3 ], [ undef, %b2 ]
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%v3 = phi i32* [ undef, %b3 ], [ undef, %b2 ]
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%v4 = phi i16* [ %v5, %b3 ], [ undef, %b2 ]
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%v5 = getelementptr inbounds i16, i16* %v4, i32 1
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%v6 = sext i16 %v1 to i32
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%v7 = call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32 0, i32 %v6, i32 undef)
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%v8 = getelementptr inbounds i16, i16* %v4, i32 2
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%v9 = call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32 %v7, i32 undef, i32 undef)
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%v10 = load i16, i16* %v8, align 2, !tbaa !0
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%v11 = call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32 %v9, i32 undef, i32 undef)
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%v12 = call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %v11, i32 undef)
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%v13 = getelementptr [166 x i32], [166 x i32]* null, i32 0, i32 undef
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%v14 = load i32, i32* %v13, align 4
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%v15 = call i64 @llvm.hexagon.M2.dpmpyss.s0(i32 %v14, i32 undef)
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%v16 = call i64 @llvm.hexagon.S2.asr.i.p(i64 %v15, i32 15)
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%v17 = call i32 @llvm.hexagon.A2.sat(i64 %v16)
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%v18 = call i32 @llvm.hexagon.A2.subsat(i32 %v12, i32 %v17)
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%v19 = getelementptr [166 x i32], [166 x i32]* null, i32 0, i32 undef
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%v20 = load i32, i32* %v19, align 4
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%v21 = call i64 @llvm.hexagon.M2.dpmpyss.s0(i32 %v20, i32 0)
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%v22 = call i64 @llvm.hexagon.S2.asr.i.p(i64 %v21, i32 15)
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%v23 = call i32 @llvm.hexagon.A2.sat(i64 %v22)
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%v24 = call i32 @llvm.hexagon.A2.subsat(i32 %v18, i32 %v23)
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%v25 = call i32 @llvm.hexagon.S2.asl.r.r.sat(i32 %v24, i32 undef)
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store i32 %v25, i32* %v3, align 4, !tbaa !4
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%v26 = add i32 %v2, 1
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%v27 = icmp eq i32 %v26, 164
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br i1 %v27, label %b4, label %b3
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b4: ; preds = %b3
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call void @llvm.trap()
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unreachable
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32, i32, i32) #0
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.S2.asr.r.r.sat(i32, i32) #0
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.A2.sat(i64) #0
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; Function Attrs: nounwind readnone
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declare i64 @llvm.hexagon.S2.asr.i.p(i64, i32) #0
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; Function Attrs: nounwind readnone
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declare i64 @llvm.hexagon.M2.dpmpyss.s0(i32, i32) #0
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.A2.subsat(i32, i32) #0
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; Function Attrs: noreturn nounwind
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declare void @llvm.trap() #2
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind "target-cpu"="hexagonv55" }
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attributes #2 = { noreturn nounwind }
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!0 = !{!1, !1, i64 0}
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!1 = !{!"short", !2, i64 0}
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!2 = !{!"omnipotent char", !3, i64 0}
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!3 = !{!"Simple C/C++ TBAA"}
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!4 = !{!5, !5, i64 0}
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!5 = !{!"long", !2, i64 0}
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