2014-08-20 03:44:06 +08:00
|
|
|
; RUN: llc -mtriple=x86_64-darwin-unknown < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SDAG
|
|
|
|
|
; RUN: llc -mtriple=x86_64-darwin-unknown -fast-isel -fast-isel-abort < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FAST
|
2014-06-11 07:52:44 +08:00
|
|
|
|
|
|
|
|
;
|
|
|
|
|
; Get the actual value of the overflow bit.
|
|
|
|
|
;
|
|
|
|
|
; SADDO reg, reg
|
|
|
|
|
define zeroext i1 @saddo.i8(i8 signext %v1, i8 signext %v2, i8* %res) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: saddo.i8
|
|
|
|
|
; CHECK: addb %sil, %dil
|
|
|
|
|
; CHECK-NEXT: seto %al
|
2014-06-11 07:52:44 +08:00
|
|
|
%t = call {i8, i1} @llvm.sadd.with.overflow.i8(i8 %v1, i8 %v2)
|
|
|
|
|
%val = extractvalue {i8, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i8, i1} %t, 1
|
|
|
|
|
store i8 %val, i8* %res
|
|
|
|
|
ret i1 %obit
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define zeroext i1 @saddo.i16(i16 %v1, i16 %v2, i16* %res) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: saddo.i16
|
|
|
|
|
; CHECK: addw %si, %di
|
|
|
|
|
; CHECK-NEXT: seto %al
|
2014-06-11 07:52:44 +08:00
|
|
|
%t = call {i16, i1} @llvm.sadd.with.overflow.i16(i16 %v1, i16 %v2)
|
|
|
|
|
%val = extractvalue {i16, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i16, i1} %t, 1
|
|
|
|
|
store i16 %val, i16* %res
|
|
|
|
|
ret i1 %obit
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define zeroext i1 @saddo.i32(i32 %v1, i32 %v2, i32* %res) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: saddo.i32
|
|
|
|
|
; CHECK: addl %esi, %edi
|
|
|
|
|
; CHECK-NEXT: seto %al
|
2014-06-11 07:52:44 +08:00
|
|
|
%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
|
|
|
|
|
%val = extractvalue {i32, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i32, i1} %t, 1
|
|
|
|
|
store i32 %val, i32* %res
|
|
|
|
|
ret i1 %obit
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define zeroext i1 @saddo.i64(i64 %v1, i64 %v2, i64* %res) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: saddo.i64
|
|
|
|
|
; CHECK: addq %rsi, %rdi
|
|
|
|
|
; CHECK-NEXT: seto %al
|
2014-06-11 07:52:44 +08:00
|
|
|
%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
|
|
|
|
|
%val = extractvalue {i64, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i64, i1} %t, 1
|
|
|
|
|
store i64 %val, i64* %res
|
|
|
|
|
ret i1 %obit
|
|
|
|
|
}
|
|
|
|
|
|
2014-08-09 01:21:37 +08:00
|
|
|
; SADDO reg, 1 | INC
|
|
|
|
|
define zeroext i1 @saddo.inc.i8(i8 %v1, i8* %res) {
|
2014-06-11 07:52:44 +08:00
|
|
|
entry:
|
2014-08-09 01:21:37 +08:00
|
|
|
; CHECK-LABEL: saddo.inc.i8
|
|
|
|
|
; CHECK: incb %dil
|
|
|
|
|
; CHECK-NEXT: seto %al
|
|
|
|
|
%t = call {i8, i1} @llvm.sadd.with.overflow.i8(i8 %v1, i8 1)
|
|
|
|
|
%val = extractvalue {i8, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i8, i1} %t, 1
|
|
|
|
|
store i8 %val, i8* %res
|
|
|
|
|
ret i1 %obit
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define zeroext i1 @saddo.inc.i16(i16 %v1, i16* %res) {
|
|
|
|
|
entry:
|
|
|
|
|
; CHECK-LABEL: saddo.inc.i16
|
|
|
|
|
; CHECK: incw %di
|
|
|
|
|
; CHECK-NEXT: seto %al
|
|
|
|
|
%t = call {i16, i1} @llvm.sadd.with.overflow.i16(i16 %v1, i16 1)
|
|
|
|
|
%val = extractvalue {i16, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i16, i1} %t, 1
|
|
|
|
|
store i16 %val, i16* %res
|
|
|
|
|
ret i1 %obit
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define zeroext i1 @saddo.inc.i32(i32 %v1, i32* %res) {
|
|
|
|
|
entry:
|
|
|
|
|
; CHECK-LABEL: saddo.inc.i32
|
|
|
|
|
; CHECK: incl %edi
|
|
|
|
|
; CHECK-NEXT: seto %al
|
|
|
|
|
%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 1)
|
|
|
|
|
%val = extractvalue {i32, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i32, i1} %t, 1
|
|
|
|
|
store i32 %val, i32* %res
|
|
|
|
|
ret i1 %obit
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define zeroext i1 @saddo.inc.i64(i64 %v1, i64* %res) {
|
|
|
|
|
entry:
|
|
|
|
|
; CHECK-LABEL: saddo.inc.i64
|
|
|
|
|
; CHECK: incq %rdi
|
|
|
|
|
; CHECK-NEXT: seto %al
|
2014-06-11 07:52:44 +08:00
|
|
|
%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 1)
|
|
|
|
|
%val = extractvalue {i64, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i64, i1} %t, 1
|
|
|
|
|
store i64 %val, i64* %res
|
|
|
|
|
ret i1 %obit
|
|
|
|
|
}
|
|
|
|
|
|
2014-08-09 01:21:37 +08:00
|
|
|
; SADDO reg, imm | imm, reg
|
2014-06-11 07:52:44 +08:00
|
|
|
; FIXME: DAG doesn't optimize immediates on the LHS.
|
2014-08-09 01:21:37 +08:00
|
|
|
define zeroext i1 @saddo.i64imm1(i64 %v1, i64* %res) {
|
2014-06-11 07:52:44 +08:00
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; SDAG-LABEL: saddo.i64imm1
|
|
|
|
|
; SDAG: mov
|
|
|
|
|
; SDAG-NEXT: addq
|
|
|
|
|
; SDAG-NEXT: seto
|
|
|
|
|
; FAST-LABEL: saddo.i64imm1
|
|
|
|
|
; FAST: addq $2, %rdi
|
|
|
|
|
; FAST-NEXT: seto %al
|
2014-08-09 01:21:37 +08:00
|
|
|
%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 2, i64 %v1)
|
2014-06-11 07:52:44 +08:00
|
|
|
%val = extractvalue {i64, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i64, i1} %t, 1
|
|
|
|
|
store i64 %val, i64* %res
|
|
|
|
|
ret i1 %obit
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; Check boundary conditions for large immediates.
|
2014-08-09 01:21:37 +08:00
|
|
|
define zeroext i1 @saddo.i64imm2(i64 %v1, i64* %res) {
|
2014-06-11 07:52:44 +08:00
|
|
|
entry:
|
[X86] Improve mul w/ overflow codegen, to MUL8+SETO.
Currently, @llvm.smul.with.overflow.i8 expands to 9 instructions, where
3 are really needed.
This adds X86ISD::UMUL8/SMUL8 SD nodes, and custom lowers them to
MUL8/IMUL8 + SETO.
i8 is a special case because there is no two/three operand variants of
(I)MUL8, so the first operand and return value need to go in AL/AX.
Also, we can't write patterns for these instructions: TableGen refuses
patterns where output operands don't match SDNode results. In this case,
instructions where the output operand is an implicitly defined register.
A related special case (and FIXME) exists for MUL8 (X86InstrArith.td):
// FIXME: Used for 8-bit mul, ignore result upper 8 bits.
// This probably ought to be moved to a def : Pat<> if the
// syntax can be accepted.
[(set AL, (mul AL, GR8:$src)), (implicit EFLAGS)]
Ideally, these go away with UMUL8, but we still need to improve TableGen
support of implicit operands in patterns.
Before this change:
movsbl %sil, %eax
movsbl %dil, %ecx
imull %eax, %ecx
movb %cl, %al
sarb $7, %al
movzbl %al, %eax
movzbl %ch, %esi
cmpl %eax, %esi
setne %al
After:
movb %dil, %al
imulb %sil
seto %al
Also, remove a made-redundant testcase for PR19858, and enable more FastISel
ALU-overflow tests for SelectionDAG too.
Differential Revision: http://reviews.llvm.org/D5809
llvm-svn: 220516
2014-10-24 05:55:31 +08:00
|
|
|
; CHECK-LABEL: saddo.i64imm2
|
|
|
|
|
; CHECK: addq $-2147483648, %rdi
|
|
|
|
|
; CHECK-NEXT: seto %al
|
2014-06-11 07:52:44 +08:00
|
|
|
%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 -2147483648)
|
|
|
|
|
%val = extractvalue {i64, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i64, i1} %t, 1
|
|
|
|
|
store i64 %val, i64* %res
|
|
|
|
|
ret i1 %obit
|
|
|
|
|
}
|
|
|
|
|
|
2014-08-09 01:21:37 +08:00
|
|
|
define zeroext i1 @saddo.i64imm3(i64 %v1, i64* %res) {
|
2014-06-11 07:52:44 +08:00
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: saddo.i64imm3
|
|
|
|
|
; CHECK: movabsq $-21474836489, %[[REG:[a-z]+]]
|
|
|
|
|
; CHECK-NEXT: addq %rdi, %[[REG]]
|
|
|
|
|
; CHECK-NEXT: seto
|
2014-06-11 07:52:44 +08:00
|
|
|
%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 -21474836489)
|
|
|
|
|
%val = extractvalue {i64, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i64, i1} %t, 1
|
|
|
|
|
store i64 %val, i64* %res
|
|
|
|
|
ret i1 %obit
|
|
|
|
|
}
|
|
|
|
|
|
2014-08-09 01:21:37 +08:00
|
|
|
define zeroext i1 @saddo.i64imm4(i64 %v1, i64* %res) {
|
2014-06-11 07:52:44 +08:00
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: saddo.i64imm4
|
|
|
|
|
; CHECK: addq $2147483647, %rdi
|
|
|
|
|
; CHECK-NEXT: seto
|
2014-06-11 07:52:44 +08:00
|
|
|
%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 2147483647)
|
|
|
|
|
%val = extractvalue {i64, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i64, i1} %t, 1
|
|
|
|
|
store i64 %val, i64* %res
|
|
|
|
|
ret i1 %obit
|
|
|
|
|
}
|
|
|
|
|
|
2014-08-09 01:21:37 +08:00
|
|
|
define zeroext i1 @saddo.i64imm5(i64 %v1, i64* %res) {
|
2014-06-11 07:52:44 +08:00
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: saddo.i64imm5
|
|
|
|
|
; CHECK: movl $2147483648
|
|
|
|
|
; CHECK: addq %rdi
|
|
|
|
|
; CHECK-NEXT: seto
|
2014-06-11 07:52:44 +08:00
|
|
|
%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 2147483648)
|
|
|
|
|
%val = extractvalue {i64, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i64, i1} %t, 1
|
|
|
|
|
store i64 %val, i64* %res
|
|
|
|
|
ret i1 %obit
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; UADDO
|
|
|
|
|
define zeroext i1 @uaddo.i32(i32 %v1, i32 %v2, i32* %res) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: uaddo.i32
|
|
|
|
|
; CHECK: addl %esi, %edi
|
|
|
|
|
; CHECK-NEXT: setb %al
|
2014-06-11 07:52:44 +08:00
|
|
|
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
|
|
|
|
|
%val = extractvalue {i32, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i32, i1} %t, 1
|
|
|
|
|
store i32 %val, i32* %res
|
|
|
|
|
ret i1 %obit
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define zeroext i1 @uaddo.i64(i64 %v1, i64 %v2, i64* %res) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: uaddo.i64
|
|
|
|
|
; CHECK: addq %rsi, %rdi
|
|
|
|
|
; CHECK-NEXT: setb %al
|
2014-06-11 07:52:44 +08:00
|
|
|
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
|
|
|
|
|
%val = extractvalue {i64, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i64, i1} %t, 1
|
|
|
|
|
store i64 %val, i64* %res
|
|
|
|
|
ret i1 %obit
|
|
|
|
|
}
|
|
|
|
|
|
2014-08-09 02:47:04 +08:00
|
|
|
; UADDO reg, 1 | NOT INC
|
|
|
|
|
define zeroext i1 @uaddo.inc.i8(i8 %v1, i8* %res) {
|
|
|
|
|
entry:
|
|
|
|
|
; CHECK-LABEL: uaddo.inc.i8
|
|
|
|
|
; CHECK-NOT: incb %dil
|
|
|
|
|
%t = call {i8, i1} @llvm.uadd.with.overflow.i8(i8 %v1, i8 1)
|
|
|
|
|
%val = extractvalue {i8, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i8, i1} %t, 1
|
|
|
|
|
store i8 %val, i8* %res
|
|
|
|
|
ret i1 %obit
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define zeroext i1 @uaddo.inc.i16(i16 %v1, i16* %res) {
|
|
|
|
|
entry:
|
|
|
|
|
; CHECK-LABEL: uaddo.inc.i16
|
|
|
|
|
; CHECK-NOT: incw %di
|
|
|
|
|
%t = call {i16, i1} @llvm.uadd.with.overflow.i16(i16 %v1, i16 1)
|
|
|
|
|
%val = extractvalue {i16, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i16, i1} %t, 1
|
|
|
|
|
store i16 %val, i16* %res
|
|
|
|
|
ret i1 %obit
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define zeroext i1 @uaddo.inc.i32(i32 %v1, i32* %res) {
|
|
|
|
|
entry:
|
|
|
|
|
; CHECK-LABEL: uaddo.inc.i32
|
|
|
|
|
; CHECK-NOT: incl %edi
|
|
|
|
|
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 1)
|
|
|
|
|
%val = extractvalue {i32, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i32, i1} %t, 1
|
|
|
|
|
store i32 %val, i32* %res
|
|
|
|
|
ret i1 %obit
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define zeroext i1 @uaddo.inc.i64(i64 %v1, i64* %res) {
|
|
|
|
|
entry:
|
|
|
|
|
; CHECK-LABEL: uaddo.inc.i64
|
|
|
|
|
; CHECK-NOT: incq %rdi
|
|
|
|
|
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 1)
|
|
|
|
|
%val = extractvalue {i64, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i64, i1} %t, 1
|
|
|
|
|
store i64 %val, i64* %res
|
|
|
|
|
ret i1 %obit
|
|
|
|
|
}
|
|
|
|
|
|
2014-06-11 07:52:44 +08:00
|
|
|
; SSUBO
|
|
|
|
|
define zeroext i1 @ssubo.i32(i32 %v1, i32 %v2, i32* %res) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: ssubo.i32
|
|
|
|
|
; CHECK: subl %esi, %edi
|
|
|
|
|
; CHECK-NEXT: seto %al
|
2014-06-11 07:52:44 +08:00
|
|
|
%t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
|
|
|
|
|
%val = extractvalue {i32, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i32, i1} %t, 1
|
|
|
|
|
store i32 %val, i32* %res
|
|
|
|
|
ret i1 %obit
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define zeroext i1 @ssubo.i64(i64 %v1, i64 %v2, i64* %res) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: ssubo.i64
|
|
|
|
|
; CHECK: subq %rsi, %rdi
|
|
|
|
|
; CHECK-NEXT: seto %al
|
2014-06-11 07:52:44 +08:00
|
|
|
%t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
|
|
|
|
|
%val = extractvalue {i64, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i64, i1} %t, 1
|
|
|
|
|
store i64 %val, i64* %res
|
|
|
|
|
ret i1 %obit
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; USUBO
|
|
|
|
|
define zeroext i1 @usubo.i32(i32 %v1, i32 %v2, i32* %res) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: usubo.i32
|
|
|
|
|
; CHECK: subl %esi, %edi
|
|
|
|
|
; CHECK-NEXT: setb %al
|
2014-06-11 07:52:44 +08:00
|
|
|
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
|
|
|
|
|
%val = extractvalue {i32, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i32, i1} %t, 1
|
|
|
|
|
store i32 %val, i32* %res
|
|
|
|
|
ret i1 %obit
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define zeroext i1 @usubo.i64(i64 %v1, i64 %v2, i64* %res) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: usubo.i64
|
|
|
|
|
; CHECK: subq %rsi, %rdi
|
|
|
|
|
; CHECK-NEXT: setb %al
|
2014-06-11 07:52:44 +08:00
|
|
|
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
|
|
|
|
|
%val = extractvalue {i64, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i64, i1} %t, 1
|
|
|
|
|
store i64 %val, i64* %res
|
|
|
|
|
ret i1 %obit
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; SMULO
|
2014-07-08 05:52:21 +08:00
|
|
|
define zeroext i1 @smulo.i8(i8 %v1, i8 %v2, i8* %res) {
|
|
|
|
|
entry:
|
[X86] Improve mul w/ overflow codegen, to MUL8+SETO.
Currently, @llvm.smul.with.overflow.i8 expands to 9 instructions, where
3 are really needed.
This adds X86ISD::UMUL8/SMUL8 SD nodes, and custom lowers them to
MUL8/IMUL8 + SETO.
i8 is a special case because there is no two/three operand variants of
(I)MUL8, so the first operand and return value need to go in AL/AX.
Also, we can't write patterns for these instructions: TableGen refuses
patterns where output operands don't match SDNode results. In this case,
instructions where the output operand is an implicitly defined register.
A related special case (and FIXME) exists for MUL8 (X86InstrArith.td):
// FIXME: Used for 8-bit mul, ignore result upper 8 bits.
// This probably ought to be moved to a def : Pat<> if the
// syntax can be accepted.
[(set AL, (mul AL, GR8:$src)), (implicit EFLAGS)]
Ideally, these go away with UMUL8, but we still need to improve TableGen
support of implicit operands in patterns.
Before this change:
movsbl %sil, %eax
movsbl %dil, %ecx
imull %eax, %ecx
movb %cl, %al
sarb $7, %al
movzbl %al, %eax
movzbl %ch, %esi
cmpl %eax, %esi
setne %al
After:
movb %dil, %al
imulb %sil
seto %al
Also, remove a made-redundant testcase for PR19858, and enable more FastISel
ALU-overflow tests for SelectionDAG too.
Differential Revision: http://reviews.llvm.org/D5809
llvm-svn: 220516
2014-10-24 05:55:31 +08:00
|
|
|
; CHECK-LABEL: smulo.i8
|
|
|
|
|
; CHECK: movb %dil, %al
|
|
|
|
|
; CHECK-NEXT: imulb %sil
|
|
|
|
|
; CHECK-NEXT: seto %cl
|
2014-07-08 05:52:21 +08:00
|
|
|
%t = call {i8, i1} @llvm.smul.with.overflow.i8(i8 %v1, i8 %v2)
|
|
|
|
|
%val = extractvalue {i8, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i8, i1} %t, 1
|
|
|
|
|
store i8 %val, i8* %res
|
|
|
|
|
ret i1 %obit
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define zeroext i1 @smulo.i16(i16 %v1, i16 %v2, i16* %res) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: smulo.i16
|
|
|
|
|
; CHECK: imulw %si, %di
|
|
|
|
|
; CHECK-NEXT: seto %al
|
2014-07-08 05:52:21 +08:00
|
|
|
%t = call {i16, i1} @llvm.smul.with.overflow.i16(i16 %v1, i16 %v2)
|
|
|
|
|
%val = extractvalue {i16, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i16, i1} %t, 1
|
|
|
|
|
store i16 %val, i16* %res
|
|
|
|
|
ret i1 %obit
|
|
|
|
|
}
|
|
|
|
|
|
2014-06-11 07:52:44 +08:00
|
|
|
define zeroext i1 @smulo.i32(i32 %v1, i32 %v2, i32* %res) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: smulo.i32
|
|
|
|
|
; CHECK: imull %esi, %edi
|
|
|
|
|
; CHECK-NEXT: seto %al
|
2014-06-11 07:52:44 +08:00
|
|
|
%t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
|
|
|
|
|
%val = extractvalue {i32, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i32, i1} %t, 1
|
|
|
|
|
store i32 %val, i32* %res
|
|
|
|
|
ret i1 %obit
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define zeroext i1 @smulo.i64(i64 %v1, i64 %v2, i64* %res) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: smulo.i64
|
|
|
|
|
; CHECK: imulq %rsi, %rdi
|
|
|
|
|
; CHECK-NEXT: seto %al
|
2014-06-11 07:52:44 +08:00
|
|
|
%t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
|
|
|
|
|
%val = extractvalue {i64, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i64, i1} %t, 1
|
|
|
|
|
store i64 %val, i64* %res
|
|
|
|
|
ret i1 %obit
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; UMULO
|
2014-07-08 05:52:21 +08:00
|
|
|
define zeroext i1 @umulo.i8(i8 %v1, i8 %v2, i8* %res) {
|
|
|
|
|
entry:
|
[X86] Improve mul w/ overflow codegen, to MUL8+SETO.
Currently, @llvm.smul.with.overflow.i8 expands to 9 instructions, where
3 are really needed.
This adds X86ISD::UMUL8/SMUL8 SD nodes, and custom lowers them to
MUL8/IMUL8 + SETO.
i8 is a special case because there is no two/three operand variants of
(I)MUL8, so the first operand and return value need to go in AL/AX.
Also, we can't write patterns for these instructions: TableGen refuses
patterns where output operands don't match SDNode results. In this case,
instructions where the output operand is an implicitly defined register.
A related special case (and FIXME) exists for MUL8 (X86InstrArith.td):
// FIXME: Used for 8-bit mul, ignore result upper 8 bits.
// This probably ought to be moved to a def : Pat<> if the
// syntax can be accepted.
[(set AL, (mul AL, GR8:$src)), (implicit EFLAGS)]
Ideally, these go away with UMUL8, but we still need to improve TableGen
support of implicit operands in patterns.
Before this change:
movsbl %sil, %eax
movsbl %dil, %ecx
imull %eax, %ecx
movb %cl, %al
sarb $7, %al
movzbl %al, %eax
movzbl %ch, %esi
cmpl %eax, %esi
setne %al
After:
movb %dil, %al
imulb %sil
seto %al
Also, remove a made-redundant testcase for PR19858, and enable more FastISel
ALU-overflow tests for SelectionDAG too.
Differential Revision: http://reviews.llvm.org/D5809
llvm-svn: 220516
2014-10-24 05:55:31 +08:00
|
|
|
; CHECK-LABEL: umulo.i8
|
|
|
|
|
; CHECK: movb %dil, %al
|
|
|
|
|
; CHECK-NEXT: mulb %sil
|
|
|
|
|
; CHECK-NEXT: seto %cl
|
2014-07-08 05:52:21 +08:00
|
|
|
%t = call {i8, i1} @llvm.umul.with.overflow.i8(i8 %v1, i8 %v2)
|
|
|
|
|
%val = extractvalue {i8, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i8, i1} %t, 1
|
|
|
|
|
store i8 %val, i8* %res
|
|
|
|
|
ret i1 %obit
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define zeroext i1 @umulo.i16(i16 %v1, i16 %v2, i16* %res) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: umulo.i16
|
|
|
|
|
; CHECK: mulw %si
|
|
|
|
|
; CHECK-NEXT: seto
|
2014-07-08 05:52:21 +08:00
|
|
|
%t = call {i16, i1} @llvm.umul.with.overflow.i16(i16 %v1, i16 %v2)
|
|
|
|
|
%val = extractvalue {i16, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i16, i1} %t, 1
|
|
|
|
|
store i16 %val, i16* %res
|
|
|
|
|
ret i1 %obit
|
|
|
|
|
}
|
|
|
|
|
|
2014-06-11 07:52:44 +08:00
|
|
|
define zeroext i1 @umulo.i32(i32 %v1, i32 %v2, i32* %res) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: umulo.i32
|
|
|
|
|
; CHECK: mull %esi
|
|
|
|
|
; CHECK-NEXT: seto
|
2014-06-11 07:52:44 +08:00
|
|
|
%t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
|
|
|
|
|
%val = extractvalue {i32, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i32, i1} %t, 1
|
|
|
|
|
store i32 %val, i32* %res
|
|
|
|
|
ret i1 %obit
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define zeroext i1 @umulo.i64(i64 %v1, i64 %v2, i64* %res) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: umulo.i64
|
|
|
|
|
; CHECK: mulq %rsi
|
|
|
|
|
; CHECK-NEXT: seto
|
2014-06-11 07:52:44 +08:00
|
|
|
%t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
|
|
|
|
|
%val = extractvalue {i64, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i64, i1} %t, 1
|
|
|
|
|
store i64 %val, i64* %res
|
|
|
|
|
ret i1 %obit
|
|
|
|
|
}
|
|
|
|
|
|
2014-06-25 07:51:21 +08:00
|
|
|
;
|
|
|
|
|
; Check the use of the overflow bit in combination with a select instruction.
|
|
|
|
|
;
|
|
|
|
|
define i32 @saddo.select.i32(i32 %v1, i32 %v2) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: saddo.select.i32
|
|
|
|
|
; CHECK: addl %esi, %eax
|
|
|
|
|
; CHECK-NEXT: cmovol %edi, %esi
|
2014-06-25 07:51:21 +08:00
|
|
|
%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
|
|
|
|
|
%obit = extractvalue {i32, i1} %t, 1
|
|
|
|
|
%ret = select i1 %obit, i32 %v1, i32 %v2
|
|
|
|
|
ret i32 %ret
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i64 @saddo.select.i64(i64 %v1, i64 %v2) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: saddo.select.i64
|
|
|
|
|
; CHECK: addq %rsi, %rax
|
|
|
|
|
; CHECK-NEXT: cmovoq %rdi, %rsi
|
2014-06-25 07:51:21 +08:00
|
|
|
%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
|
|
|
|
|
%obit = extractvalue {i64, i1} %t, 1
|
|
|
|
|
%ret = select i1 %obit, i64 %v1, i64 %v2
|
|
|
|
|
ret i64 %ret
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i32 @uaddo.select.i32(i32 %v1, i32 %v2) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: uaddo.select.i32
|
|
|
|
|
; CHECK: addl %esi, %eax
|
|
|
|
|
; CHECK-NEXT: cmovbl %edi, %esi
|
2014-06-25 07:51:21 +08:00
|
|
|
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
|
|
|
|
|
%obit = extractvalue {i32, i1} %t, 1
|
|
|
|
|
%ret = select i1 %obit, i32 %v1, i32 %v2
|
|
|
|
|
ret i32 %ret
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i64 @uaddo.select.i64(i64 %v1, i64 %v2) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: uaddo.select.i64
|
|
|
|
|
; CHECK: addq %rsi, %rax
|
|
|
|
|
; CHECK-NEXT: cmovbq %rdi, %rsi
|
2014-06-25 07:51:21 +08:00
|
|
|
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
|
|
|
|
|
%obit = extractvalue {i64, i1} %t, 1
|
|
|
|
|
%ret = select i1 %obit, i64 %v1, i64 %v2
|
|
|
|
|
ret i64 %ret
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i32 @ssubo.select.i32(i32 %v1, i32 %v2) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: ssubo.select.i32
|
|
|
|
|
; CHECK: cmpl %esi, %edi
|
|
|
|
|
; CHECK-NEXT: cmovol %edi, %esi
|
2014-06-25 07:51:21 +08:00
|
|
|
%t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
|
|
|
|
|
%obit = extractvalue {i32, i1} %t, 1
|
|
|
|
|
%ret = select i1 %obit, i32 %v1, i32 %v2
|
|
|
|
|
ret i32 %ret
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i64 @ssubo.select.i64(i64 %v1, i64 %v2) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: ssubo.select.i64
|
|
|
|
|
; CHECK: cmpq %rsi, %rdi
|
|
|
|
|
; CHECK-NEXT: cmovoq %rdi, %rsi
|
2014-06-25 07:51:21 +08:00
|
|
|
%t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
|
|
|
|
|
%obit = extractvalue {i64, i1} %t, 1
|
|
|
|
|
%ret = select i1 %obit, i64 %v1, i64 %v2
|
|
|
|
|
ret i64 %ret
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i32 @usubo.select.i32(i32 %v1, i32 %v2) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: usubo.select.i32
|
|
|
|
|
; CHECK: cmpl %esi, %edi
|
|
|
|
|
; CHECK-NEXT: cmovbl %edi, %esi
|
2014-06-25 07:51:21 +08:00
|
|
|
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
|
|
|
|
|
%obit = extractvalue {i32, i1} %t, 1
|
|
|
|
|
%ret = select i1 %obit, i32 %v1, i32 %v2
|
|
|
|
|
ret i32 %ret
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i64 @usubo.select.i64(i64 %v1, i64 %v2) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: usubo.select.i64
|
|
|
|
|
; CHECK: cmpq %rsi, %rdi
|
|
|
|
|
; CHECK-NEXT: cmovbq %rdi, %rsi
|
2014-06-25 07:51:21 +08:00
|
|
|
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
|
|
|
|
|
%obit = extractvalue {i64, i1} %t, 1
|
|
|
|
|
%ret = select i1 %obit, i64 %v1, i64 %v2
|
|
|
|
|
ret i64 %ret
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i32 @smulo.select.i32(i32 %v1, i32 %v2) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: smulo.select.i32
|
|
|
|
|
; CHECK: imull %esi, %eax
|
|
|
|
|
; CHECK-NEXT: cmovol %edi, %esi
|
2014-06-25 07:51:21 +08:00
|
|
|
%t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
|
|
|
|
|
%obit = extractvalue {i32, i1} %t, 1
|
|
|
|
|
%ret = select i1 %obit, i32 %v1, i32 %v2
|
|
|
|
|
ret i32 %ret
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i64 @smulo.select.i64(i64 %v1, i64 %v2) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: smulo.select.i64
|
|
|
|
|
; CHECK: imulq %rsi, %rax
|
|
|
|
|
; CHECK-NEXT: cmovoq %rdi, %rsi
|
2014-06-25 07:51:21 +08:00
|
|
|
%t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
|
|
|
|
|
%obit = extractvalue {i64, i1} %t, 1
|
|
|
|
|
%ret = select i1 %obit, i64 %v1, i64 %v2
|
|
|
|
|
ret i64 %ret
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i32 @umulo.select.i32(i32 %v1, i32 %v2) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: umulo.select.i32
|
|
|
|
|
; CHECK: mull %esi
|
|
|
|
|
; CHECK-NEXT: cmovol %edi, %esi
|
2014-06-25 07:51:21 +08:00
|
|
|
%t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
|
|
|
|
|
%obit = extractvalue {i32, i1} %t, 1
|
|
|
|
|
%ret = select i1 %obit, i32 %v1, i32 %v2
|
|
|
|
|
ret i32 %ret
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i64 @umulo.select.i64(i64 %v1, i64 %v2) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: umulo.select.i64
|
|
|
|
|
; CHECK: mulq %rsi
|
|
|
|
|
; CHECK-NEXT: cmovoq %rdi, %rsi
|
2014-06-25 07:51:21 +08:00
|
|
|
%t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
|
|
|
|
|
%obit = extractvalue {i64, i1} %t, 1
|
|
|
|
|
%ret = select i1 %obit, i64 %v1, i64 %v2
|
|
|
|
|
ret i64 %ret
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
;
|
|
|
|
|
; Check the use of the overflow bit in combination with a branch instruction.
|
|
|
|
|
;
|
|
|
|
|
define zeroext i1 @saddo.br.i32(i32 %v1, i32 %v2) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: saddo.br.i32
|
|
|
|
|
; CHECK: addl %esi, %edi
|
|
|
|
|
; CHECK-NEXT: jo
|
2014-06-25 07:51:21 +08:00
|
|
|
%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
|
|
|
|
|
%val = extractvalue {i32, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i32, i1} %t, 1
|
|
|
|
|
br i1 %obit, label %overflow, label %continue, !prof !0
|
|
|
|
|
|
|
|
|
|
overflow:
|
|
|
|
|
ret i1 false
|
|
|
|
|
|
|
|
|
|
continue:
|
|
|
|
|
ret i1 true
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define zeroext i1 @saddo.br.i64(i64 %v1, i64 %v2) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: saddo.br.i64
|
|
|
|
|
; CHECK: addq %rsi, %rdi
|
|
|
|
|
; CHECK-NEXT: jo
|
2014-06-25 07:51:21 +08:00
|
|
|
%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
|
|
|
|
|
%val = extractvalue {i64, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i64, i1} %t, 1
|
|
|
|
|
br i1 %obit, label %overflow, label %continue, !prof !0
|
|
|
|
|
|
|
|
|
|
overflow:
|
|
|
|
|
ret i1 false
|
|
|
|
|
|
|
|
|
|
continue:
|
|
|
|
|
ret i1 true
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define zeroext i1 @uaddo.br.i32(i32 %v1, i32 %v2) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: uaddo.br.i32
|
|
|
|
|
; CHECK: addl %esi, %edi
|
|
|
|
|
; CHECK-NEXT: jb
|
2014-06-25 07:51:21 +08:00
|
|
|
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
|
|
|
|
|
%val = extractvalue {i32, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i32, i1} %t, 1
|
|
|
|
|
br i1 %obit, label %overflow, label %continue, !prof !0
|
|
|
|
|
|
|
|
|
|
overflow:
|
|
|
|
|
ret i1 false
|
|
|
|
|
|
|
|
|
|
continue:
|
|
|
|
|
ret i1 true
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define zeroext i1 @uaddo.br.i64(i64 %v1, i64 %v2) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: uaddo.br.i64
|
|
|
|
|
; CHECK: addq %rsi, %rdi
|
|
|
|
|
; CHECK-NEXT: jb
|
2014-06-25 07:51:21 +08:00
|
|
|
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
|
|
|
|
|
%val = extractvalue {i64, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i64, i1} %t, 1
|
|
|
|
|
br i1 %obit, label %overflow, label %continue, !prof !0
|
|
|
|
|
|
|
|
|
|
overflow:
|
|
|
|
|
ret i1 false
|
|
|
|
|
|
|
|
|
|
continue:
|
|
|
|
|
ret i1 true
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define zeroext i1 @ssubo.br.i32(i32 %v1, i32 %v2) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: ssubo.br.i32
|
|
|
|
|
; CHECK: cmpl %esi, %edi
|
|
|
|
|
; CHECK-NEXT: jo
|
2014-06-25 07:51:21 +08:00
|
|
|
%t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
|
|
|
|
|
%val = extractvalue {i32, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i32, i1} %t, 1
|
|
|
|
|
br i1 %obit, label %overflow, label %continue, !prof !0
|
|
|
|
|
|
|
|
|
|
overflow:
|
|
|
|
|
ret i1 false
|
|
|
|
|
|
|
|
|
|
continue:
|
|
|
|
|
ret i1 true
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define zeroext i1 @ssubo.br.i64(i64 %v1, i64 %v2) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: ssubo.br.i64
|
|
|
|
|
; CHECK: cmpq %rsi, %rdi
|
|
|
|
|
; CHECK-NEXT: jo
|
2014-06-25 07:51:21 +08:00
|
|
|
%t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
|
|
|
|
|
%val = extractvalue {i64, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i64, i1} %t, 1
|
|
|
|
|
br i1 %obit, label %overflow, label %continue, !prof !0
|
|
|
|
|
|
|
|
|
|
overflow:
|
|
|
|
|
ret i1 false
|
|
|
|
|
|
|
|
|
|
continue:
|
|
|
|
|
ret i1 true
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define zeroext i1 @usubo.br.i32(i32 %v1, i32 %v2) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: usubo.br.i32
|
|
|
|
|
; CHECK: cmpl %esi, %edi
|
|
|
|
|
; CHECK-NEXT: jb
|
2014-06-25 07:51:21 +08:00
|
|
|
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
|
|
|
|
|
%val = extractvalue {i32, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i32, i1} %t, 1
|
|
|
|
|
br i1 %obit, label %overflow, label %continue, !prof !0
|
|
|
|
|
|
|
|
|
|
overflow:
|
|
|
|
|
ret i1 false
|
|
|
|
|
|
|
|
|
|
continue:
|
|
|
|
|
ret i1 true
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define zeroext i1 @usubo.br.i64(i64 %v1, i64 %v2) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: usubo.br.i64
|
|
|
|
|
; CHECK: cmpq %rsi, %rdi
|
|
|
|
|
; CHECK-NEXT: jb
|
2014-06-25 07:51:21 +08:00
|
|
|
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
|
|
|
|
|
%val = extractvalue {i64, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i64, i1} %t, 1
|
|
|
|
|
br i1 %obit, label %overflow, label %continue, !prof !0
|
|
|
|
|
|
|
|
|
|
overflow:
|
|
|
|
|
ret i1 false
|
|
|
|
|
|
|
|
|
|
continue:
|
|
|
|
|
ret i1 true
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define zeroext i1 @smulo.br.i32(i32 %v1, i32 %v2) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: smulo.br.i32
|
|
|
|
|
; CHECK: imull %esi, %edi
|
|
|
|
|
; CHECK-NEXT: jo
|
2014-06-25 07:51:21 +08:00
|
|
|
%t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
|
|
|
|
|
%val = extractvalue {i32, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i32, i1} %t, 1
|
|
|
|
|
br i1 %obit, label %overflow, label %continue, !prof !0
|
|
|
|
|
|
|
|
|
|
overflow:
|
|
|
|
|
ret i1 false
|
|
|
|
|
|
|
|
|
|
continue:
|
|
|
|
|
ret i1 true
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define zeroext i1 @smulo.br.i64(i64 %v1, i64 %v2) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: smulo.br.i64
|
|
|
|
|
; CHECK: imulq %rsi, %rdi
|
|
|
|
|
; CHECK-NEXT: jo
|
2014-06-25 07:51:21 +08:00
|
|
|
%t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
|
|
|
|
|
%val = extractvalue {i64, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i64, i1} %t, 1
|
|
|
|
|
br i1 %obit, label %overflow, label %continue, !prof !0
|
|
|
|
|
|
|
|
|
|
overflow:
|
|
|
|
|
ret i1 false
|
|
|
|
|
|
|
|
|
|
continue:
|
|
|
|
|
ret i1 true
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define zeroext i1 @umulo.br.i32(i32 %v1, i32 %v2) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: umulo.br.i32
|
|
|
|
|
; CHECK: mull %esi
|
|
|
|
|
; CHECK-NEXT: jo
|
2014-06-25 07:51:21 +08:00
|
|
|
%t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
|
|
|
|
|
%val = extractvalue {i32, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i32, i1} %t, 1
|
|
|
|
|
br i1 %obit, label %overflow, label %continue, !prof !0
|
|
|
|
|
|
|
|
|
|
overflow:
|
|
|
|
|
ret i1 false
|
|
|
|
|
|
|
|
|
|
continue:
|
|
|
|
|
ret i1 true
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define zeroext i1 @umulo.br.i64(i64 %v1, i64 %v2) {
|
|
|
|
|
entry:
|
2014-08-20 03:44:06 +08:00
|
|
|
; CHECK-LABEL: umulo.br.i64
|
|
|
|
|
; CHECK: mulq %rsi
|
|
|
|
|
; CHECK-NEXT: jo
|
2014-06-25 07:51:21 +08:00
|
|
|
%t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
|
|
|
|
|
%val = extractvalue {i64, i1} %t, 0
|
|
|
|
|
%obit = extractvalue {i64, i1} %t, 1
|
|
|
|
|
br i1 %obit, label %overflow, label %continue, !prof !0
|
|
|
|
|
|
|
|
|
|
overflow:
|
|
|
|
|
ret i1 false
|
|
|
|
|
|
|
|
|
|
continue:
|
|
|
|
|
ret i1 true
|
|
|
|
|
}
|
|
|
|
|
|
2014-07-08 05:52:21 +08:00
|
|
|
declare {i8, i1} @llvm.sadd.with.overflow.i8 (i8, i8 ) nounwind readnone
|
2014-06-11 07:52:44 +08:00
|
|
|
declare {i16, i1} @llvm.sadd.with.overflow.i16(i16, i16) nounwind readnone
|
|
|
|
|
declare {i32, i1} @llvm.sadd.with.overflow.i32(i32, i32) nounwind readnone
|
|
|
|
|
declare {i64, i1} @llvm.sadd.with.overflow.i64(i64, i64) nounwind readnone
|
2014-08-09 02:47:04 +08:00
|
|
|
declare {i8, i1} @llvm.uadd.with.overflow.i8 (i8, i8 ) nounwind readnone
|
|
|
|
|
declare {i16, i1} @llvm.uadd.with.overflow.i16(i16, i16) nounwind readnone
|
2014-06-11 07:52:44 +08:00
|
|
|
declare {i32, i1} @llvm.uadd.with.overflow.i32(i32, i32) nounwind readnone
|
|
|
|
|
declare {i64, i1} @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone
|
|
|
|
|
declare {i32, i1} @llvm.ssub.with.overflow.i32(i32, i32) nounwind readnone
|
|
|
|
|
declare {i64, i1} @llvm.ssub.with.overflow.i64(i64, i64) nounwind readnone
|
|
|
|
|
declare {i32, i1} @llvm.usub.with.overflow.i32(i32, i32) nounwind readnone
|
|
|
|
|
declare {i64, i1} @llvm.usub.with.overflow.i64(i64, i64) nounwind readnone
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2014-07-08 05:52:21 +08:00
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declare {i8, i1} @llvm.smul.with.overflow.i8 (i8, i8 ) nounwind readnone
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declare {i16, i1} @llvm.smul.with.overflow.i16(i16, i16) nounwind readnone
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2014-06-11 07:52:44 +08:00
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declare {i32, i1} @llvm.smul.with.overflow.i32(i32, i32) nounwind readnone
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declare {i64, i1} @llvm.smul.with.overflow.i64(i64, i64) nounwind readnone
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2014-07-08 05:52:21 +08:00
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declare {i8, i1} @llvm.umul.with.overflow.i8 (i8, i8 ) nounwind readnone
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declare {i16, i1} @llvm.umul.with.overflow.i16(i16, i16) nounwind readnone
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2014-06-11 07:52:44 +08:00
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declare {i32, i1} @llvm.umul.with.overflow.i32(i32, i32) nounwind readnone
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declare {i64, i1} @llvm.umul.with.overflow.i64(i64, i64) nounwind readnone
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IR: Make metadata typeless in assembly
Now that `Metadata` is typeless, reflect that in the assembly. These
are the matching assembly changes for the metadata/value split in
r223802.
- Only use the `metadata` type when referencing metadata from a call
intrinsic -- i.e., only when it's used as a `Value`.
- Stop pretending that `ValueAsMetadata` is wrapped in an `MDNode`
when referencing it from call intrinsics.
So, assembly like this:
define @foo(i32 %v) {
call void @llvm.foo(metadata !{i32 %v}, metadata !0)
call void @llvm.foo(metadata !{i32 7}, metadata !0)
call void @llvm.foo(metadata !1, metadata !0)
call void @llvm.foo(metadata !3, metadata !0)
call void @llvm.foo(metadata !{metadata !3}, metadata !0)
ret void, !bar !2
}
!0 = metadata !{metadata !2}
!1 = metadata !{i32* @global}
!2 = metadata !{metadata !3}
!3 = metadata !{}
turns into this:
define @foo(i32 %v) {
call void @llvm.foo(metadata i32 %v, metadata !0)
call void @llvm.foo(metadata i32 7, metadata !0)
call void @llvm.foo(metadata i32* @global, metadata !0)
call void @llvm.foo(metadata !3, metadata !0)
call void @llvm.foo(metadata !{!3}, metadata !0)
ret void, !bar !2
}
!0 = !{!2}
!1 = !{i32* @global}
!2 = !{!3}
!3 = !{}
I wrote an upgrade script that handled almost all of the tests in llvm
and many of the tests in cfe (even handling many `CHECK` lines). I've
attached it (or will attach it in a moment if you're speedy) to PR21532
to help everyone update their out-of-tree testcases.
This is part of PR21532.
llvm-svn: 224257
2014-12-16 03:07:53 +08:00
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!0 = !{!"branch_weights", i32 0, i32 2147483647}
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