2019-10-02 02:04:02 +08:00
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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2020-04-22 23:33:11 +08:00
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK
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2019-10-02 02:04:02 +08:00
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define arm_aapcs_vfpcc <4 x i32> @sext_0246(<8 x i16> %src) {
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; CHECK-LABEL: sext_0246:
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; CHECK: @ %bb.0: @ %entry
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2019-10-02 19:40:51 +08:00
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; CHECK-NEXT: vmovlb.s16 q0, q0
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2019-10-02 02:04:02 +08:00
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%out = sext <4 x i16> %strided.vec to <4 x i32>
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ret <4 x i32> %out
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}
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define arm_aapcs_vfpcc <4 x i32> @sext_1357(<8 x i16> %src) {
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; CHECK-LABEL: sext_1357:
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; CHECK: @ %bb.0: @ %entry
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[ARM,MVE] Add the vmovlbq,vmovltq intrinsic family.
Summary:
These intrinsics take a vector of 2n elements, and return a vector of
n wider elements obtained by sign- or zero-extending every other
element of the input vector. They're represented in IR as a
shufflevector that extracts the odd or even elements of the input,
followed by a sext or zext.
Existing LLVM codegen already matches this pattern and generates the
VMOVLB instruction (which widens the even-index input lanes). But no
existing isel rule was generating VMOVLT, so I've added some. However,
the new rules currently only work in little-endian MVE, because the
pattern they expect from isel lowering includes a bitconvert which
doesn't have the right semantics in big-endian.
The output of one existing codegen test is improved by those new
rules.
This commit adds the unpredicated forms only.
Reviewers: dmgreen, miyuki, MarkMurrayARM, ostannard
Reviewed By: dmgreen
Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D74336
2020-02-18 01:06:05 +08:00
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; CHECK-NEXT: vmovlt.s16 q0, q0
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2019-10-02 02:04:02 +08:00
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%out = sext <4 x i16> %strided.vec to <4 x i32>
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ret <4 x i32> %out
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}
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define arm_aapcs_vfpcc <4 x i32> @zext_0246(<8 x i16> %src) {
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; CHECK-LABEL: zext_0246:
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; CHECK: @ %bb.0: @ %entry
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2019-10-02 19:40:51 +08:00
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; CHECK-NEXT: vmovlb.u16 q0, q0
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2019-10-02 02:04:02 +08:00
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%out = zext <4 x i16> %strided.vec to <4 x i32>
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ret <4 x i32> %out
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}
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define arm_aapcs_vfpcc <4 x i32> @zext_1357(<8 x i16> %src) {
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; CHECK-LABEL: zext_1357:
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; CHECK: @ %bb.0: @ %entry
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[ARM,MVE] Add the vmovlbq,vmovltq intrinsic family.
Summary:
These intrinsics take a vector of 2n elements, and return a vector of
n wider elements obtained by sign- or zero-extending every other
element of the input vector. They're represented in IR as a
shufflevector that extracts the odd or even elements of the input,
followed by a sext or zext.
Existing LLVM codegen already matches this pattern and generates the
VMOVLB instruction (which widens the even-index input lanes). But no
existing isel rule was generating VMOVLT, so I've added some. However,
the new rules currently only work in little-endian MVE, because the
pattern they expect from isel lowering includes a bitconvert which
doesn't have the right semantics in big-endian.
The output of one existing codegen test is improved by those new
rules.
This commit adds the unpredicated forms only.
Reviewers: dmgreen, miyuki, MarkMurrayARM, ostannard
Reviewed By: dmgreen
Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D74336
2020-02-18 01:06:05 +08:00
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; CHECK-NEXT: vmovlt.u16 q0, q0
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2019-10-02 02:04:02 +08:00
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%out = zext <4 x i16> %strided.vec to <4 x i32>
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ret <4 x i32> %out
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}
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define arm_aapcs_vfpcc <8 x i16> @sext_02468101214(<16 x i8> %src) {
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; CHECK-LABEL: sext_02468101214:
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; CHECK: @ %bb.0: @ %entry
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2019-10-02 19:40:51 +08:00
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; CHECK-NEXT: vmovlb.s8 q0, q0
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2019-10-02 02:04:02 +08:00
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <16 x i8> %src, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%out = sext <8 x i8> %strided.vec to <8 x i16>
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ret <8 x i16> %out
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}
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define arm_aapcs_vfpcc <8 x i16> @sext_13579111315(<16 x i8> %src) {
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; CHECK-LABEL: sext_13579111315:
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; CHECK: @ %bb.0: @ %entry
|
[ARM,MVE] Add the vmovlbq,vmovltq intrinsic family.
Summary:
These intrinsics take a vector of 2n elements, and return a vector of
n wider elements obtained by sign- or zero-extending every other
element of the input vector. They're represented in IR as a
shufflevector that extracts the odd or even elements of the input,
followed by a sext or zext.
Existing LLVM codegen already matches this pattern and generates the
VMOVLB instruction (which widens the even-index input lanes). But no
existing isel rule was generating VMOVLT, so I've added some. However,
the new rules currently only work in little-endian MVE, because the
pattern they expect from isel lowering includes a bitconvert which
doesn't have the right semantics in big-endian.
The output of one existing codegen test is improved by those new
rules.
This commit adds the unpredicated forms only.
Reviewers: dmgreen, miyuki, MarkMurrayARM, ostannard
Reviewed By: dmgreen
Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D74336
2020-02-18 01:06:05 +08:00
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; CHECK-NEXT: vmovlt.s8 q0, q0
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2019-10-02 02:04:02 +08:00
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <16 x i8> %src, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%out = sext <8 x i8> %strided.vec to <8 x i16>
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ret <8 x i16> %out
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}
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define arm_aapcs_vfpcc <8 x i16> @zext_02468101214(<16 x i8> %src) {
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; CHECK-LABEL: zext_02468101214:
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; CHECK: @ %bb.0: @ %entry
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2019-10-02 19:40:51 +08:00
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; CHECK-NEXT: vmovlb.u8 q0, q0
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2019-10-02 02:04:02 +08:00
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <16 x i8> %src, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%out = zext <8 x i8> %strided.vec to <8 x i16>
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ret <8 x i16> %out
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}
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define arm_aapcs_vfpcc <8 x i16> @zext_13579111315(<16 x i8> %src) {
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; CHECK-LABEL: zext_13579111315:
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; CHECK: @ %bb.0: @ %entry
|
[ARM,MVE] Add the vmovlbq,vmovltq intrinsic family.
Summary:
These intrinsics take a vector of 2n elements, and return a vector of
n wider elements obtained by sign- or zero-extending every other
element of the input vector. They're represented in IR as a
shufflevector that extracts the odd or even elements of the input,
followed by a sext or zext.
Existing LLVM codegen already matches this pattern and generates the
VMOVLB instruction (which widens the even-index input lanes). But no
existing isel rule was generating VMOVLT, so I've added some. However,
the new rules currently only work in little-endian MVE, because the
pattern they expect from isel lowering includes a bitconvert which
doesn't have the right semantics in big-endian.
The output of one existing codegen test is improved by those new
rules.
This commit adds the unpredicated forms only.
Reviewers: dmgreen, miyuki, MarkMurrayARM, ostannard
Reviewed By: dmgreen
Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D74336
2020-02-18 01:06:05 +08:00
|
|
|
; CHECK-NEXT: vmovlt.u8 q0, q0
|
2019-10-02 02:04:02 +08:00
|
|
|
; CHECK-NEXT: bx lr
|
|
|
|
entry:
|
|
|
|
%strided.vec = shufflevector <16 x i8> %src, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%out = zext <8 x i8> %strided.vec to <8 x i16>
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ret <8 x i16> %out
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}
|