2013-08-12 18:28:10 +08:00
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; Test memcmp using CLC.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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declare signext i32 @memcmp(i8 *%src1, i8 *%src2, i64 %size)
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; Zero-length comparisons should be optimized away.
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define i32 @f1(i8 *%src1, i8 *%src2) {
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; CHECK-LABEL: f1:
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; CHECK: lhi %r2, 0
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; CHECK: br %r14
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%res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 0)
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ret i32 %res
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}
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; Check a case where the result is used as an integer.
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define i32 @f2(i8 *%src1, i8 *%src2) {
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; CHECK-LABEL: f2:
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; CHECK: clc 0(2,%r2), 0(%r3)
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[SystemZ] Fix sign of integer memcmp result
r188163 used CLC to implement memcmp. Code that compares the result
directly against zero can test the CC value produced by CLC, but code
that needs an integer result must use IPM. The sequence I'd used was:
ipm <reg>
sll <reg>, 2
sra <reg>, 30
but I'd forgotten that this inverts the order, so that CC==1 ("less")
becomes an integer greater than zero, and CC==2 ("greater") becomes
an integer less than zero. This sequence should only be used if the
CLC arguments are reversed to compensate. The problem then is that
the branch condition must also be reversed when testing the CLC
result directly.
Rather than do that, I went for a different sequence that works with
the natural CLC order:
ipm <reg>
srl <reg>, 28
rll <reg>, <reg>, 31
One advantage of this is that it doesn't clobber CC. A disadvantage
is that any sign extension to 64 bits must be done separately,
rather than being folded into the shifts.
llvm-svn: 188538
2013-08-16 18:22:54 +08:00
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; CHECK: ipm [[REG:%r[0-5]]]
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; CHECK: srl [[REG]], 28
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; CHECK: rll %r2, [[REG]], 31
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2013-08-12 18:28:10 +08:00
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; CHECK: br %r14
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%res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 2)
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ret i32 %res
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}
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; Check a case where the result is tested for equality.
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define void @f3(i8 *%src1, i8 *%src2, i32 *%dest) {
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; CHECK-LABEL: f3:
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; CHECK: clc 0(3,%r2), 0(%r3)
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; CHECK-NEXT: je {{\..*}}
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; CHECK: br %r14
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%res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 3)
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%cmp = icmp eq i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 0, i32 *%dest
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br label %exit
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exit:
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ret void
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}
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; Check a case where the result is tested for inequality.
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define void @f4(i8 *%src1, i8 *%src2, i32 *%dest) {
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; CHECK-LABEL: f4:
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; CHECK: clc 0(4,%r2), 0(%r3)
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; CHECK-NEXT: jlh {{\..*}}
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; CHECK: br %r14
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entry:
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%res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 4)
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%cmp = icmp ne i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 0, i32 *%dest
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br label %exit
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exit:
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ret void
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}
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; Check a case where the result is tested via slt.
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define void @f5(i8 *%src1, i8 *%src2, i32 *%dest) {
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; CHECK-LABEL: f5:
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; CHECK: clc 0(5,%r2), 0(%r3)
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; CHECK-NEXT: jl {{\..*}}
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; CHECK: br %r14
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entry:
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%res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 5)
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%cmp = icmp slt i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 0, i32 *%dest
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br label %exit
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exit:
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ret void
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}
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; Check a case where the result is tested for sgt.
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define void @f6(i8 *%src1, i8 *%src2, i32 *%dest) {
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; CHECK-LABEL: f6:
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; CHECK: clc 0(6,%r2), 0(%r3)
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; CHECK-NEXT: jh {{\..*}}
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; CHECK: br %r14
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entry:
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%res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 6)
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%cmp = icmp sgt i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 0, i32 *%dest
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br label %exit
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exit:
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ret void
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}
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; Check the upper end of the CLC range. Here the result is used both as
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[SystemZ] Fix sign of integer memcmp result
r188163 used CLC to implement memcmp. Code that compares the result
directly against zero can test the CC value produced by CLC, but code
that needs an integer result must use IPM. The sequence I'd used was:
ipm <reg>
sll <reg>, 2
sra <reg>, 30
but I'd forgotten that this inverts the order, so that CC==1 ("less")
becomes an integer greater than zero, and CC==2 ("greater") becomes
an integer less than zero. This sequence should only be used if the
CLC arguments are reversed to compensate. The problem then is that
the branch condition must also be reversed when testing the CLC
result directly.
Rather than do that, I went for a different sequence that works with
the natural CLC order:
ipm <reg>
srl <reg>, 28
rll <reg>, <reg>, 31
One advantage of this is that it doesn't clobber CC. A disadvantage
is that any sign extension to 64 bits must be done separately,
rather than being folded into the shifts.
llvm-svn: 188538
2013-08-16 18:22:54 +08:00
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; an integer and for branching.
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2013-08-12 18:28:10 +08:00
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define i32 @f7(i8 *%src1, i8 *%src2, i32 *%dest) {
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; CHECK-LABEL: f7:
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; CHECK: clc 0(256,%r2), 0(%r3)
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[SystemZ] Fix sign of integer memcmp result
r188163 used CLC to implement memcmp. Code that compares the result
directly against zero can test the CC value produced by CLC, but code
that needs an integer result must use IPM. The sequence I'd used was:
ipm <reg>
sll <reg>, 2
sra <reg>, 30
but I'd forgotten that this inverts the order, so that CC==1 ("less")
becomes an integer greater than zero, and CC==2 ("greater") becomes
an integer less than zero. This sequence should only be used if the
CLC arguments are reversed to compensate. The problem then is that
the branch condition must also be reversed when testing the CLC
result directly.
Rather than do that, I went for a different sequence that works with
the natural CLC order:
ipm <reg>
srl <reg>, 28
rll <reg>, <reg>, 31
One advantage of this is that it doesn't clobber CC. A disadvantage
is that any sign extension to 64 bits must be done separately,
rather than being folded into the shifts.
llvm-svn: 188538
2013-08-16 18:22:54 +08:00
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; CHECK: ipm [[REG:%r[0-5]]]
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; CHECK: srl [[REG]], 28
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; CHECK: rll %r2, [[REG]], 31
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2013-08-12 18:28:10 +08:00
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; CHECK: jl {{.L*}}
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; CHECK: br %r14
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entry:
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%res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 256)
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%cmp = icmp slt i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 0, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; 257 bytes is too big for a single CLC. For now expect a call instead.
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define i32 @f8(i8 *%src1, i8 *%src2) {
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; CHECK-LABEL: f8:
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; CHECK: brasl %r14, memcmp@PLT
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; CHECK: br %r14
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%res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 257)
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ret i32 %res
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}
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