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llvm-project/llvm/test/CodeGen/X86/frameaddr.ll

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[FastISel][X86] Add support for the frameaddress intrinsic. llvm-svn: 210709
2014-06-12 05:44:44 +08:00
; RUN: llc < %s -march=x86 | FileCheck %s --check-prefix=CHECK-32
; RUN: llc < %s -march=x86 -fast-isel -fast-isel-abort | FileCheck %s --check-prefix=CHECK-32
; RUN: llc < %s -march=x86-64 | FileCheck %s --check-prefix=CHECK-64
; RUN: llc < %s -march=x86-64 -fast-isel -fast-isel-abort | FileCheck %s --check-prefix=CHECK-64
[x32] Use ebp/esp as frame and stack pointer Summary: Since pointers are 32-bit on x32 we can use ebp and esp as frame and stack pointer. Some operations like PUSH/POP and CFI_INSTRUCTION still require 64-bit register, so using 64-bit MachineFramePtr where required. X86_64 NaCl uses 64-bit frame/stack pointers, however it's been found that both isTarget64BitLP64 and isTarget64BitILP32 are true for NaCl. Addressing this issue here as well by making isTarget64BitLP64 false. Also mark hasReservedSpillSlot unreachable on X86. See inlined comments. Test Plan: Add one new simple test and upgrade 2 existing with x32 target case. Reviewers: nadav, dschuff Subscribers: llvm-commits, zinovy.nis Differential Revision: http://reviews.llvm.org/D4617 llvm-svn: 215091
2014-08-07 17:41:19 +08:00
; RUN: llc < %s -mtriple=x86_64-gnux32 | FileCheck %s --check-prefix=CHECK-X32ABI
; RUN: llc < %s -mtriple=x86_64-gnux32 -fast-isel -fast-isel-abort | FileCheck %s --check-prefix=CHECK-X32ABI
[FastISel][X86] Add support for the frameaddress intrinsic. llvm-svn: 210709
2014-06-12 05:44:44 +08:00
define i8* @test1() nounwind {
entry:
[x86] Improve frameaddress test from r210709. llvm-svn: 210743
2014-06-12 11:29:29 +08:00
; CHECK-32-LABEL: test1
; CHECK-32: push
; CHECK-32-NEXT: movl %esp, %ebp
; CHECK-32-NEXT: movl %ebp, %eax
; CHECK-32-NEXT: pop
; CHECK-32-NEXT: ret
; CHECK-64-LABEL: test1
; CHECK-64: push
; CHECK-64-NEXT: movq %rsp, %rbp
; CHECK-64-NEXT: movq %rbp, %rax
; CHECK-64-NEXT: pop
; CHECK-64-NEXT: ret
[x32] Use ebp/esp as frame and stack pointer Summary: Since pointers are 32-bit on x32 we can use ebp and esp as frame and stack pointer. Some operations like PUSH/POP and CFI_INSTRUCTION still require 64-bit register, so using 64-bit MachineFramePtr where required. X86_64 NaCl uses 64-bit frame/stack pointers, however it's been found that both isTarget64BitLP64 and isTarget64BitILP32 are true for NaCl. Addressing this issue here as well by making isTarget64BitLP64 false. Also mark hasReservedSpillSlot unreachable on X86. See inlined comments. Test Plan: Add one new simple test and upgrade 2 existing with x32 target case. Reviewers: nadav, dschuff Subscribers: llvm-commits, zinovy.nis Differential Revision: http://reviews.llvm.org/D4617 llvm-svn: 215091
2014-08-07 17:41:19 +08:00
; CHECK-X32ABI-LABEL: test1
; CHECK-X32ABI: pushq %rbp
; CHECK-X32ABI-NEXT: movl %esp, %ebp
; CHECK-X32ABI-NEXT: movl %ebp, %eax
; CHECK-X32ABI-NEXT: popq %rbp
; CHECK-X32ABI-NEXT: ret
[FastISel][X86] Add support for the frameaddress intrinsic. llvm-svn: 210709
2014-06-12 05:44:44 +08:00
%0 = tail call i8* @llvm.frameaddress(i32 0)
ret i8* %0
}
define i8* @test2() nounwind {
entry:
[x86] Improve frameaddress test from r210709. llvm-svn: 210743
2014-06-12 11:29:29 +08:00
; CHECK-32-LABEL: test2
; CHECK-32: push
; CHECK-32-NEXT: movl %esp, %ebp
; CHECK-32-NEXT: movl (%ebp), %eax
; CHECK-32-NEXT: movl (%eax), %eax
; CHECK-32-NEXT: pop
; CHECK-32-NEXT: ret
; CHECK-64-LABEL: test2
; CHECK-64: push
; CHECK-64-NEXT: movq %rsp, %rbp
; CHECK-64-NEXT: movq (%rbp), %rax
; CHECK-64-NEXT: movq (%rax), %rax
; CHECK-64-NEXT: pop
; CHECK-64-NEXT: ret
[x32] Use ebp/esp as frame and stack pointer Summary: Since pointers are 32-bit on x32 we can use ebp and esp as frame and stack pointer. Some operations like PUSH/POP and CFI_INSTRUCTION still require 64-bit register, so using 64-bit MachineFramePtr where required. X86_64 NaCl uses 64-bit frame/stack pointers, however it's been found that both isTarget64BitLP64 and isTarget64BitILP32 are true for NaCl. Addressing this issue here as well by making isTarget64BitLP64 false. Also mark hasReservedSpillSlot unreachable on X86. See inlined comments. Test Plan: Add one new simple test and upgrade 2 existing with x32 target case. Reviewers: nadav, dschuff Subscribers: llvm-commits, zinovy.nis Differential Revision: http://reviews.llvm.org/D4617 llvm-svn: 215091
2014-08-07 17:41:19 +08:00
; CHECK-X32ABI-LABEL: test2
; CHECK-X32ABI: pushq %rbp
; CHECK-X32ABI-NEXT: movl %esp, %ebp
; CHECK-X32ABI-NEXT: movl (%ebp), %eax
; CHECK-X32ABI-NEXT: movl (%eax), %eax
; CHECK-X32ABI-NEXT: popq %rbp
; CHECK-X32ABI-NEXT: ret
[FastISel][X86] Add support for the frameaddress intrinsic. llvm-svn: 210709
2014-06-12 05:44:44 +08:00
%0 = tail call i8* @llvm.frameaddress(i32 2)
ret i8* %0
}
[x86] Improve frameaddress test from r210709. llvm-svn: 210743
2014-06-12 11:29:29 +08:00
[FastISel][X86] Add support for the frameaddress intrinsic. llvm-svn: 210709
2014-06-12 05:44:44 +08:00
declare i8* @llvm.frameaddress(i32) nounwind readnone