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llvm-project/llvm/test/CodeGen/AArch64/arm64-fast-isel-alloca.ll

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ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; This test should cause the TargetMaterializeAlloca to be invoked
; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s
%struct.S1Ty = type { i64 }
%struct.S2Ty = type { %struct.S1Ty, %struct.S1Ty }
define void @takeS1(%struct.S1Ty* %V) nounwind {
entry:
%V.addr = alloca %struct.S1Ty*, align 8
store %struct.S1Ty* %V, %struct.S1Ty** %V.addr, align 8
ret void
}
define void @main() nounwind {
entry:
; CHECK: main
[ARM64] Rename FP to the UAL-compliant 'X29'. llvm-svn: 205884
2014-04-09 22:43:50 +08:00
; CHECK: mov x29, sp
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; CHECK: mov x[[REG:[0-9]+]], sp
; CHECK-NEXT: orr x[[REG1:[0-9]+]], xzr, #0x8
; CHECK-NEXT: add x0, x[[REG]], x[[REG1]]
%E = alloca %struct.S2Ty, align 4
%B = getelementptr inbounds %struct.S2Ty* %E, i32 0, i32 1
call void @takeS1(%struct.S1Ty* %B)
ret void
}