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llvm-project/llvm/test/CodeGen/X86/pr27681.mir

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[MIR] Print on the given output instead of stderr. Currently the MIR framework prints all its outputs (errors and actual representation) on stderr. This patch fixes that by printing the regular output in the output specified with -o. Differential Revision: http://reviews.llvm.org/D22251 llvm-svn: 275314
2016-07-14 04:36:03 +08:00
# RUN: llc -mtriple=i386-unknown-linux-gnu -mcpu=slm -run-pass post-RA-sched -o - %s | FileCheck %s
[CodeGen] Fix problem with X86 byte registers in CriticalAntiDepBreaker CriticalAntiDepBreaker was not correctly tracking defs of the high X86 byte registers, leading to incorrect use of a busy register to break an antidependence. Fixes pr27681, and its duplicates pr27580, pr27804. Differential Revision: http://reviews.llvm.org/D20456 llvm-svn: 270935
2016-05-27 07:08:52 +08:00
#
# Verify that the critical antidependence breaker does not consider
# a high byte register as available as a replacement register
# in a certain context.
--- |
define void @main() { ret void }
...
---
# CHECK-LABEL: main
name: main
tracksRegLiveness: true
frameInfo:
stackSize: 52
fixedStack:
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
- { id: 0, type: spill-slot, offset: -20, size: 4, alignment: 4, callee-saved-register: '$esi' }
- { id: 1, type: spill-slot, offset: -16, size: 4, alignment: 4, callee-saved-register: '$edi' }
- { id: 2, type: spill-slot, offset: -12, size: 4, alignment: 4, callee-saved-register: '$ebx' }
- { id: 3, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '$ebp' }
[CodeGen] Fix problem with X86 byte registers in CriticalAntiDepBreaker CriticalAntiDepBreaker was not correctly tracking defs of the high X86 byte registers, leading to incorrect use of a busy register to break an antidependence. Fixes pr27681, and its duplicates pr27580, pr27804. Differential Revision: http://reviews.llvm.org/D20456 llvm-svn: 270935
2016-05-27 07:08:52 +08:00
stack:
- { id: 0, type: spill-slot, offset: -53, size: 1, alignment: 1 }
- { id: 1, type: spill-slot, offset: -48, size: 4, alignment: 4 }
- { id: 2, type: spill-slot, offset: -32, size: 4, alignment: 4 }
body: |
bb.0:
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
liveins: $ebp, $ebx, $edi, $esi
[CodeGen] Fix problem with X86 byte registers in CriticalAntiDepBreaker CriticalAntiDepBreaker was not correctly tracking defs of the high X86 byte registers, leading to incorrect use of a busy register to break an antidependence. Fixes pr27681, and its duplicates pr27580, pr27804. Differential Revision: http://reviews.llvm.org/D20456 llvm-svn: 270935
2016-05-27 07:08:52 +08:00
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
frame-setup PUSH32r killed $ebp, implicit-def $esp, implicit $esp
frame-setup PUSH32r killed $ebx, implicit-def $esp, implicit $esp
frame-setup PUSH32r killed $edi, implicit-def $esp, implicit $esp
frame-setup PUSH32r killed $esi, implicit-def $esp, implicit $esp
$esp = frame-setup SUB32ri8 $esp, 36, implicit-def dead $eflags
$eax = MOV32ri 1
$ebp = MOV32ri 2
$ebx = MOV32ri 3
$ecx = MOV32ri 4
$edi = MOV32ri 5
$edx = MOV32ri 6
[CodeGen] Fix problem with X86 byte registers in CriticalAntiDepBreaker CriticalAntiDepBreaker was not correctly tracking defs of the high X86 byte registers, leading to incorrect use of a busy register to break an antidependence. Fixes pr27681, and its duplicates pr27580, pr27804. Differential Revision: http://reviews.llvm.org/D20456 llvm-svn: 270935
2016-05-27 07:08:52 +08:00
bb.1:
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
liveins: $eax, $ebp, $ebx, $ecx, $edi, $edx
[CodeGen] Fix problem with X86 byte registers in CriticalAntiDepBreaker CriticalAntiDepBreaker was not correctly tracking defs of the high X86 byte registers, leading to incorrect use of a busy register to break an antidependence. Fixes pr27681, and its duplicates pr27580, pr27804. Differential Revision: http://reviews.llvm.org/D20456 llvm-svn: 270935
2016-05-27 07:08:52 +08:00
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
$ebp = SHR32rCL killed $ebp, implicit-def dead $eflags, implicit $cl
$ebp = XOR32rr killed $ebp, killed $ebx, implicit-def dead $eflags
TEST32rr $edx, $edx, implicit-def $eflags
[X86] Merge the different SETcc instructions for each condition code into single instructions that store the condition code as an operand. Summary: This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between SETcc instructions and condition codes. Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser. Reviewers: andreadb, courbet, RKSimon, spatel, lebedev.ri Reviewed By: andreadb Subscribers: hiraditya, lebedev.ri, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60138 llvm-svn: 357801
2019-04-06 03:27:49 +08:00
$cl = SETCCr 5, implicit $eflags
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
; This %bl def is antidependent on the above use of $ebx
$bl = MOV8rm $esp, 1, $noreg, 3, _ ; :: (load 1 from %stack.0)
$cl = OR8rr killed $cl, $bl, implicit-def dead $eflags
$esi = MOVZX32rr8 killed $cl
$esi = ADD32rr killed $esi, killed $edi, implicit-def dead $eflags
$ecx = MOV32rm $esp, 1, $noreg, 24, _ ; :: (load 4 from %stack.2)
$edx = SAR32rCL killed $edx, implicit-def dead $eflags, implicit $cl
TEST32rr killed $edx, $edx, implicit-def $eflags
[X86] Merge the different SETcc instructions for each condition code into single instructions that store the condition code as an operand. Summary: This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between SETcc instructions and condition codes. Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser. Reviewers: andreadb, courbet, RKSimon, spatel, lebedev.ri Reviewed By: andreadb Subscribers: hiraditya, lebedev.ri, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60138 llvm-svn: 357801
2019-04-06 03:27:49 +08:00
$cl = SETCCr 5, implicit $eflags
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
; Verify that removal of the $bl antidependence does not use $ch
[CodeGen] Fix problem with X86 byte registers in CriticalAntiDepBreaker CriticalAntiDepBreaker was not correctly tracking defs of the high X86 byte registers, leading to incorrect use of a busy register to break an antidependence. Fixes pr27681, and its duplicates pr27580, pr27804. Differential Revision: http://reviews.llvm.org/D20456 llvm-svn: 270935
2016-05-27 07:08:52 +08:00
; as a replacement register.
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
; CHECK: $cl = AND8rr killed $cl, killed $b
$cl = AND8rr killed $cl, killed $bl, implicit-def dead $eflags
CMP32ri8 $ebp, -1, implicit-def $eflags
$edx = MOV32ri 0
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. Summary: This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes. Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser. Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon Reviewed By: RKSimon Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60228 llvm-svn: 357802
2019-04-06 03:28:09 +08:00
JCC_1 %bb.3, 4, implicit $eflags
[CodeGen] Fix problem with X86 byte registers in CriticalAntiDepBreaker CriticalAntiDepBreaker was not correctly tracking defs of the high X86 byte registers, leading to incorrect use of a busy register to break an antidependence. Fixes pr27681, and its duplicates pr27580, pr27804. Differential Revision: http://reviews.llvm.org/D20456 llvm-svn: 270935
2016-05-27 07:08:52 +08:00
bb.2:
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
liveins: $cl, $eax, $ebp, $esi
[CodeGen] Fix problem with X86 byte registers in CriticalAntiDepBreaker CriticalAntiDepBreaker was not correctly tracking defs of the high X86 byte registers, leading to incorrect use of a busy register to break an antidependence. Fixes pr27681, and its duplicates pr27580, pr27804. Differential Revision: http://reviews.llvm.org/D20456 llvm-svn: 270935
2016-05-27 07:08:52 +08:00
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
OR32mr $esp, 1, $noreg, 8, $noreg, killed $eax, implicit-def $eflags ; :: (store 4 into %stack.1)
[X86] Merge the different SETcc instructions for each condition code into single instructions that store the condition code as an operand. Summary: This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between SETcc instructions and condition codes. Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser. Reviewers: andreadb, courbet, RKSimon, spatel, lebedev.ri Reviewed By: andreadb Subscribers: hiraditya, lebedev.ri, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60138 llvm-svn: 357801
2019-04-06 03:27:49 +08:00
$dl = SETCCr 5, implicit $eflags, implicit-def $edx
[CodeGen] Fix problem with X86 byte registers in CriticalAntiDepBreaker CriticalAntiDepBreaker was not correctly tracking defs of the high X86 byte registers, leading to incorrect use of a busy register to break an antidependence. Fixes pr27681, and its duplicates pr27580, pr27804. Differential Revision: http://reviews.llvm.org/D20456 llvm-svn: 270935
2016-05-27 07:08:52 +08:00
bb.3:
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
liveins: $cl, $ebp, $edx, $esi
[CodeGen] Fix problem with X86 byte registers in CriticalAntiDepBreaker CriticalAntiDepBreaker was not correctly tracking defs of the high X86 byte registers, leading to incorrect use of a busy register to break an antidependence. Fixes pr27681, and its duplicates pr27580, pr27804. Differential Revision: http://reviews.llvm.org/D20456 llvm-svn: 270935
2016-05-27 07:08:52 +08:00
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
$eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags
$esp = ADD32ri8 $esp, 36, implicit-def dead $eflags
$esi = POP32r implicit-def $esp, implicit $esp
$edi = POP32r implicit-def $esp, implicit $esp
$ebx = POP32r implicit-def $esp, implicit $esp
$ebp = POP32r implicit-def $esp, implicit $esp
RET 0, $eax
[CodeGen] Fix problem with X86 byte registers in CriticalAntiDepBreaker CriticalAntiDepBreaker was not correctly tracking defs of the high X86 byte registers, leading to incorrect use of a busy register to break an antidependence. Fixes pr27681, and its duplicates pr27580, pr27804. Differential Revision: http://reviews.llvm.org/D20456 llvm-svn: 270935
2016-05-27 07:08:52 +08:00
...