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llvm-project/llvm/test/CodeGen/X86/cmpxchg8b.ll

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[X86] Regenerate cmpxchg tests Add 64-bit cmpxchg8b tests llvm-svn: 326380
2018-03-01 06:57:23 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown- -mcpu=core2 | FileCheck %s --check-prefixes=CHECK,X86
; RUN: llc < %s -mtriple=x86_64-unknown- -mcpu=core2 | FileCheck %s --check-prefixes=CHECK,X64
[X86] Add CMPXCHG8B feature flag. Set it for all CPUs except i386/i486 including 'generic'. Disable use of CMPXCHG8B when this flag isn't set. CMPXCHG8B was introduced on i586/pentium generation. If its not enabled, limit the atomic width to 32 bits so the AtomicExpandPass will expand to lib calls. Unclear if we should be using a different limit for other configs. The default is 1024 and experimentation shows that using an i256 atomic will cause a crash in SelectionDAG. Differential Revision: https://reviews.llvm.org/D59576 llvm-svn: 356631
2019-03-21 07:35:49 +08:00
; RUN: llc < %s -mtriple=i686-unknown- -mcpu=i486 | FileCheck %s --check-prefixes=I486
[X86] Make CMPXCHG16B feature imply CMPXCHG8B feature. This fixes znver1 so that it properly enables CMPXHG8B. We can probably remove explicit CMPXCHG8B from CPUs that also have CMPXCHG16B, but keeping this simple to allow cherry pick to 9.0. Fixes PR42935. llvm-svn: 368324
2019-08-09 02:11:17 +08:00
; RUN: llc < %s -mtriple=i686-unknown- -mcpu=znver1 | FileCheck %s --check-prefixes=CHECK,X86
[X86] Regenerate cmpxchg tests Add 64-bit cmpxchg8b tests llvm-svn: 326380
2018-03-01 06:57:23 +08:00
; Basic 64-bit cmpxchg
define void @t1(i64* nocapture %p) nounwind ssp {
; X86-LABEL: t1:
; X86: # %bb.0: # %entry
; X86-NEXT: pushl %ebx
; X86-NEXT: pushl %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: xorl %eax, %eax
; X86-NEXT: xorl %edx, %edx
; X86-NEXT: xorl %ecx, %ecx
; X86-NEXT: movl $1, %ebx
; X86-NEXT: lock cmpxchg8b (%esi)
; X86-NEXT: popl %esi
; X86-NEXT: popl %ebx
; X86-NEXT: retl
;
; X64-LABEL: t1:
; X64: # %bb.0: # %entry
; X64-NEXT: movl $1, %ecx
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: lock cmpxchgq %rcx, (%rdi)
; X64-NEXT: retq
[X86] Add CMPXCHG8B feature flag. Set it for all CPUs except i386/i486 including 'generic'. Disable use of CMPXCHG8B when this flag isn't set. CMPXCHG8B was introduced on i586/pentium generation. If its not enabled, limit the atomic width to 32 bits so the AtomicExpandPass will expand to lib calls. Unclear if we should be using a different limit for other configs. The default is 1024 and experimentation shows that using an i256 atomic will cause a crash in SelectionDAG. Differential Revision: https://reviews.llvm.org/D59576 llvm-svn: 356631
2019-03-21 07:35:49 +08:00
;
; I486-LABEL: t1:
; I486: # %bb.0: # %entry
; I486-NEXT: pushl %ebp
; I486-NEXT: movl %esp, %ebp
; I486-NEXT: andl $-8, %esp
; I486-NEXT: subl $8, %esp
; I486-NEXT: movl 8(%ebp), %eax
; I486-NEXT: movl $0, {{[0-9]+}}(%esp)
; I486-NEXT: movl $0, (%esp)
; I486-NEXT: movl %esp, %ecx
; I486-NEXT: pushl $5
; I486-NEXT: pushl $5
; I486-NEXT: pushl $0
; I486-NEXT: pushl $1
; I486-NEXT: pushl %ecx
; I486-NEXT: pushl %eax
; I486-NEXT: calll __atomic_compare_exchange_8
; I486-NEXT: addl $24, %esp
; I486-NEXT: movl %ebp, %esp
; I486-NEXT: popl %ebp
; I486-NEXT: retl
[X86] Regenerate cmpxchg tests Add 64-bit cmpxchg8b tests llvm-svn: 326380
2018-03-01 06:57:23 +08:00
entry:
%r = cmpxchg i64* %p, i64 0, i64 1 seq_cst seq_cst
ret void
}