maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/Hexagon/vec-pred-spill1.ll

Ignoring revisions in .git-blame-ignore-revs. Click here to bypass and see the normal blame view.

81 lines
4.3 KiB
LLVM
Raw Normal View History

[Hexagon] New HVX target features. This patch lets the llvm tools handle the new HVX target features that are added by frontend (clang). The target-features are of the form "hvx-length64b" for 64 Byte HVX mode, "hvx-length128b" for 128 Byte mode HVX. "hvx-double" is an alias to "hvx-length128b" and is soon will be deprecated. The hvx version target feature is upgated form "+hvx" to "+hvxv{version_number}. Eg: "+hvxv62" For the correct HVX code generation, the user must use the following target features. For 64B mode: "+hvxv62" "+hvx-length64b" For 128B mode: "+hvxv62" "+hvx-length128b" Clang picks a default length if none is specified. If for some reason, no hvx-length is specified to llvm, the compilation will bail out. There is a corresponding clang patch. Differential Revision: https://reviews.llvm.org/D38851 llvm-svn: 316101
2017-10-19 02:07:07 +08:00
; RUN: llc -march=hexagon -mcpu=hexagonv60 -O2 -mattr=+hvxv60,hvx-length64b < %s | FileCheck %s
[Hexagon] Optimize stack slot spills Replace spills to memory with spills to registers, if possible. This applies mostly to predicate registers (both scalar and vector), since they are very limited in number. A spill of a predicate register may happen even if there is a general-purpose register available. In cases like this the stack spill/reload may be eliminated completely. This optimization will consider all stack objects, regardless of where they came from and try to match the live range of the stack slot with a dead range of a register from an appropriate register class. llvm-svn: 260758
2016-02-13 06:53:35 +08:00
; CHECK: vmem(r{{[0-9]+}}+#3) = v{{[0-9]+}}
; CHECK: call puts
; CHECK: call print_vecpred
[Hexagon] Remove {{ *}} from testcases The spaces in the instructions are now consistent. llvm-svn: 326829
2018-03-07 03:07:21 +08:00
; CHECK: v{{[0-9]+}} = vmem(r{{[0-9]+}}+#3)
[Hexagon] Optimize stack slot spills Replace spills to memory with spills to registers, if possible. This applies mostly to predicate registers (both scalar and vector), since they are very limited in number. A spill of a predicate register may happen even if there is a general-purpose register available. In cases like this the stack spill/reload may be eliminated completely. This optimization will consider all stack objects, regardless of where they came from and try to match the live range of the stack slot with a dead range of a register from an appropriate register class. llvm-svn: 260758
2016-02-13 06:53:35 +08:00
target triple = "hexagon"
@K = global i64 0, align 8
@src = global i32 -1, align 4
@Q6VecPredResult = common global <16 x i32> zeroinitializer, align 64
@dst_addresses = common global [15 x i64] zeroinitializer, align 8
@ptr_addresses = common global [15 x i8*] zeroinitializer, align 8
@src_addresses = common global [15 x i8*] zeroinitializer, align 8
@ptr = common global [32768 x i32] zeroinitializer, align 8
@vecpreds = common global [15 x <16 x i32>] zeroinitializer, align 64
@VectorResult = common global <16 x i32> zeroinitializer, align 64
@vectors = common global [15 x <16 x i32>] zeroinitializer, align 64
@VectorPairResult = common global <32 x i32> zeroinitializer, align 128
@vector_pairs = common global [15 x <32 x i32>] zeroinitializer, align 128
@str = private unnamed_addr constant [106 x i8] c"Q6VecPred4 : Q6_Q_vandor_QVR(Q6_Q_vand_VR(Q6_V_vsplat_R(1+1),(0x01010101)),Q6_V_vsplat_R(0+1),INT32_MIN)\00"
@str3 = private unnamed_addr constant [99 x i8] c"Q6VecPred4 : Q6_Q_vandor_QVR(Q6_Q_vand_VR(Q6_V_vsplat_R(1+1),(0x01010101)),Q6_V_vsplat_R(0+1),-1)\00"
@str4 = private unnamed_addr constant [98 x i8] c"Q6VecPred4 : Q6_Q_vandor_QVR(Q6_Q_vand_VR(Q6_V_vsplat_R(1+1),(0x01010101)),Q6_V_vsplat_R(0+1),0)\00"
; Function Attrs: nounwind
define i32 @main() #0 {
entry:
%call = tail call i32 bitcast (i32 (...)* @init_addresses to i32 ()*)() #3
%call1 = tail call i32 @acquire_vector_unit(i8 zeroext 0) #3
tail call void @init_vectors() #3
%0 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 2)
%1 = tail call <512 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %0, i32 16843009)
%2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1)
%3 = tail call <512 x i1> @llvm.hexagon.V6.vandvrt.acc(<512 x i1> %1, <16 x i32> %2, i32 -2147483648)
%4 = bitcast <512 x i1> %3 to <16 x i32>
store <16 x i32> %4, <16 x i32>* @Q6VecPredResult, align 64, !tbaa !1
%puts = tail call i32 @puts(i8* getelementptr inbounds ([106 x i8], [106 x i8]* @str, i32 0, i32 0))
tail call void @print_vecpred(i32 512, i8* bitcast (<16 x i32>* @Q6VecPredResult to i8*)) #3
%5 = tail call <512 x i1> @llvm.hexagon.V6.vandvrt.acc(<512 x i1> %1, <16 x i32> %2, i32 -1)
%6 = bitcast <512 x i1> %5 to <16 x i32>
store <16 x i32> %6, <16 x i32>* @Q6VecPredResult, align 64, !tbaa !1
%puts5 = tail call i32 @puts(i8* getelementptr inbounds ([99 x i8], [99 x i8]* @str3, i32 0, i32 0))
tail call void @print_vecpred(i32 512, i8* bitcast (<16 x i32>* @Q6VecPredResult to i8*)) #3
%7 = tail call <512 x i1> @llvm.hexagon.V6.vandvrt.acc(<512 x i1> %1, <16 x i32> %2, i32 0)
%8 = bitcast <512 x i1> %7 to <16 x i32>
store <16 x i32> %8, <16 x i32>* @Q6VecPredResult, align 64, !tbaa !1
%puts6 = tail call i32 @puts(i8* getelementptr inbounds ([98 x i8], [98 x i8]* @str4, i32 0, i32 0))
tail call void @print_vecpred(i32 512, i8* bitcast (<16 x i32>* @Q6VecPredResult to i8*)) #3
ret i32 0
}
declare i32 @init_addresses(...) #1
declare i32 @acquire_vector_unit(i8 zeroext) #1
declare void @init_vectors() #1
; Function Attrs: nounwind readnone
declare <512 x i1> @llvm.hexagon.V6.vandvrt.acc(<512 x i1>, <16 x i32>, i32) #2
; Function Attrs: nounwind readnone
declare <512 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32) #2
; Function Attrs: nounwind readnone
declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #2
declare void @print_vecpred(i32, i8*) #1
; Function Attrs: nounwind
declare i32 @puts(i8* nocapture readonly) #3
attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #2 = { nounwind readnone }
attributes #3 = { nounwind }
!1 = !{!2, !2, i64 0}
!2 = !{!"omnipotent char", !3, i64 0}
!3 = !{!"Simple C/C++ TBAA"}