maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/MC/PowerPC/ppc64-encoding-ext.s

1992 lines
111 KiB
ArmAsm
Raw Normal View History

[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck %s
# FIXME: Condition register bit symbols
# Branch mnemonics
# CHECK: blr # encoding: [0x4e,0x80,0x00,0x20]
blr
# CHECK: bctr # encoding: [0x4e,0x80,0x04,0x20]
bctr
[PowerPC] Support blrl and variants in the asm parser This patch adds support for blrl and its conditional variants. The patterns are (currently) used for the asm parser only. llvm-svn: 184718
2013-06-24 19:01:55 +08:00
# CHECK: blrl # encoding: [0x4e,0x80,0x00,0x21]
blrl
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bctrl # encoding: [0x4e,0x80,0x04,0x21]
bctrl
[PowerPC] Add t/f branch mnemonics to asm parser This adds the bt/bf/bd(n)zt/bd(n)zf mnemonics as aliases for the asm parser, resolving to the generic conditional patterns. llvm-svn: 184725
2013-06-24 20:49:20 +08:00
# CHECK: bc 12, 2, target # encoding: [0x41,0x82,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bt 2, target
# CHECK: bca 12, 2, target # encoding: [0x41,0x82,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bta 2, target
# CHECK: bclr 12, 2, 0 # encoding: [0x4d,0x82,0x00,0x20]
btlr 2
# CHECK: bcctr 12, 2, 0 # encoding: [0x4d,0x82,0x04,0x20]
btctr 2
# CHECK: bcl 12, 2, target # encoding: [0x41,0x82,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
btl 2, target
# CHECK: bcla 12, 2, target # encoding: [0x41,0x82,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
btla 2, target
# CHECK: bclrl 12, 2, 0 # encoding: [0x4d,0x82,0x00,0x21]
btlrl 2
# CHECK: bcctrl 12, 2, 0 # encoding: [0x4d,0x82,0x04,0x21]
btctrl 2
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
[PowerPC] Add predicted forms of branches This adds support for the predicted forms of branches (+/-). There are three cases to consider: - Branches using a PPC::Predicate code For these, I've added new PPC::Predicate codes corresponding to the BO values for predicted branch forms, and updated insn printing to print them correctly. I've also added new aliases for the asm parser matching the new forms. - bt/bf I've added new aliases matching to gBC etc. - bd(n)z variants I've added new instruction patterns for the predicted forms. In all cases, the new patterns are used for the asm parser only. (The new infrastructure ought to be sufficient to allow use by the compiler too at some point.) llvm-svn: 184754
2013-06-25 00:52:04 +08:00
# CHECK: bc 15, 2, target # encoding: [0x41,0xe2,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bt+ 2, target
# CHECK: bca 15, 2, target # encoding: [0x41,0xe2,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bta+ 2, target
# CHECK: bclr 15, 2, 0 # encoding: [0x4d,0xe2,0x00,0x20]
btlr+ 2
# CHECK: bcctr 15, 2, 0 # encoding: [0x4d,0xe2,0x04,0x20]
btctr+ 2
# CHECK: bcl 15, 2, target # encoding: [0x41,0xe2,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
btl+ 2, target
# CHECK: bcla 15, 2, target # encoding: [0x41,0xe2,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
btla+ 2, target
# CHECK: bclrl 15, 2, 0 # encoding: [0x4d,0xe2,0x00,0x21]
btlrl+ 2
# CHECK: bcctrl 15, 2, 0 # encoding: [0x4d,0xe2,0x04,0x21]
btctrl+ 2
# CHECK: bc 14, 2, target # encoding: [0x41,0xc2,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bt- 2, target
# CHECK: bca 14, 2, target # encoding: [0x41,0xc2,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bta- 2, target
# CHECK: bclr 14, 2, 0 # encoding: [0x4d,0xc2,0x00,0x20]
btlr- 2
# CHECK: bcctr 14, 2, 0 # encoding: [0x4d,0xc2,0x04,0x20]
btctr- 2
# CHECK: bcl 14, 2, target # encoding: [0x41,0xc2,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
btl- 2, target
# CHECK: bcla 14, 2, target # encoding: [0x41,0xc2,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
btla- 2, target
# CHECK: bclrl 14, 2, 0 # encoding: [0x4d,0xc2,0x00,0x21]
btlrl- 2
# CHECK: bcctrl 14, 2, 0 # encoding: [0x4d,0xc2,0x04,0x21]
btctrl- 2
[PowerPC] Add t/f branch mnemonics to asm parser This adds the bt/bf/bd(n)zt/bd(n)zf mnemonics as aliases for the asm parser, resolving to the generic conditional patterns. llvm-svn: 184725
2013-06-24 20:49:20 +08:00
# CHECK: bc 4, 2, target # encoding: [0x40,0x82,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bf 2, target
# CHECK: bca 4, 2, target # encoding: [0x40,0x82,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bfa 2, target
# CHECK: bclr 4, 2, 0 # encoding: [0x4c,0x82,0x00,0x20]
bflr 2
# CHECK: bcctr 4, 2, 0 # encoding: [0x4c,0x82,0x04,0x20]
bfctr 2
# CHECK: bcl 4, 2, target # encoding: [0x40,0x82,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bfl 2, target
# CHECK: bcla 4, 2, target # encoding: [0x40,0x82,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bfla 2, target
# CHECK: bclrl 4, 2, 0 # encoding: [0x4c,0x82,0x00,0x21]
bflrl 2
# CHECK: bcctrl 4, 2, 0 # encoding: [0x4c,0x82,0x04,0x21]
bfctrl 2
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
[PowerPC] Add predicted forms of branches This adds support for the predicted forms of branches (+/-). There are three cases to consider: - Branches using a PPC::Predicate code For these, I've added new PPC::Predicate codes corresponding to the BO values for predicted branch forms, and updated insn printing to print them correctly. I've also added new aliases for the asm parser matching the new forms. - bt/bf I've added new aliases matching to gBC etc. - bd(n)z variants I've added new instruction patterns for the predicted forms. In all cases, the new patterns are used for the asm parser only. (The new infrastructure ought to be sufficient to allow use by the compiler too at some point.) llvm-svn: 184754
2013-06-25 00:52:04 +08:00
# CHECK: bc 7, 2, target # encoding: [0x40,0xe2,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bf+ 2, target
# CHECK: bca 7, 2, target # encoding: [0x40,0xe2,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bfa+ 2, target
# CHECK: bclr 7, 2, 0 # encoding: [0x4c,0xe2,0x00,0x20]
bflr+ 2
# CHECK: bcctr 7, 2, 0 # encoding: [0x4c,0xe2,0x04,0x20]
bfctr+ 2
# CHECK: bcl 7, 2, target # encoding: [0x40,0xe2,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bfl+ 2, target
# CHECK: bcla 7, 2, target # encoding: [0x40,0xe2,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bfla+ 2, target
# CHECK: bclrl 7, 2, 0 # encoding: [0x4c,0xe2,0x00,0x21]
bflrl+ 2
# CHECK: bcctrl 7, 2, 0 # encoding: [0x4c,0xe2,0x04,0x21]
bfctrl+ 2
# CHECK: bc 6, 2, target # encoding: [0x40,0xc2,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bf- 2, target
# CHECK: bca 6, 2, target # encoding: [0x40,0xc2,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bfa- 2, target
# CHECK: bclr 6, 2, 0 # encoding: [0x4c,0xc2,0x00,0x20]
bflr- 2
# CHECK: bcctr 6, 2, 0 # encoding: [0x4c,0xc2,0x04,0x20]
bfctr- 2
# CHECK: bcl 6, 2, target # encoding: [0x40,0xc2,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bfl- 2, target
# CHECK: bcla 6, 2, target # encoding: [0x40,0xc2,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bfla- 2, target
# CHECK: bclrl 6, 2, 0 # encoding: [0x4c,0xc2,0x00,0x21]
bflrl- 2
# CHECK: bcctrl 6, 2, 0 # encoding: [0x4c,0xc2,0x04,0x21]
bfctrl- 2
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bdnz target # encoding: [0x42,0x00,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bdnz target
[PowerPC] Support absolute branches There is currently only limited support for the "absolute" variants of branch instructions. This patch adds support for the absolute variants of all branches that are currently otherwise supported. This requires adding new fixup types so that the correct variant of relocation type can be selected by the object writer. While the compiler will continue to usually choose the relative branch variants, this will allow the asm parser to fully support the absolute branches, with either immediate (numerical) or symbolic target addresses. No change in code generation intended. llvm-svn: 184721
2013-06-24 19:03:33 +08:00
# CHECK: bdnza target # encoding: [0x42,0x00,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bdnza target
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bdnzlr # encoding: [0x4e,0x00,0x00,0x20]
bdnzlr
[PowerPC] Support bd(n)zl and bd(n)zlrl This adds support for the bd(n)zl and bd(n)zlrl instructions. The patterns are currently used for the asm parser only. llvm-svn: 184720
2013-06-24 19:02:38 +08:00
# CHECK: bdnzl target # encoding: [0x42,0x00,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bdnzl target
[PowerPC] Support absolute branches There is currently only limited support for the "absolute" variants of branch instructions. This patch adds support for the absolute variants of all branches that are currently otherwise supported. This requires adding new fixup types so that the correct variant of relocation type can be selected by the object writer. While the compiler will continue to usually choose the relative branch variants, this will allow the asm parser to fully support the absolute branches, with either immediate (numerical) or symbolic target addresses. No change in code generation intended. llvm-svn: 184721
2013-06-24 19:03:33 +08:00
# CHECK: bdnzla target # encoding: [0x42,0x00,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bdnzla target
[PowerPC] Support bd(n)zl and bd(n)zlrl This adds support for the bd(n)zl and bd(n)zlrl instructions. The patterns are currently used for the asm parser only. llvm-svn: 184720
2013-06-24 19:02:38 +08:00
# CHECK: bdnzlrl # encoding: [0x4e,0x00,0x00,0x21]
bdnzlrl
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
[PowerPC] Add predicted forms of branches This adds support for the predicted forms of branches (+/-). There are three cases to consider: - Branches using a PPC::Predicate code For these, I've added new PPC::Predicate codes corresponding to the BO values for predicted branch forms, and updated insn printing to print them correctly. I've also added new aliases for the asm parser matching the new forms. - bt/bf I've added new aliases matching to gBC etc. - bd(n)z variants I've added new instruction patterns for the predicted forms. In all cases, the new patterns are used for the asm parser only. (The new infrastructure ought to be sufficient to allow use by the compiler too at some point.) llvm-svn: 184754
2013-06-25 00:52:04 +08:00
# CHECK: bdnz+ target # encoding: [0x43,0x20,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bdnz+ target
# CHECK: bdnza+ target # encoding: [0x43,0x20,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bdnza+ target
# CHECK: bdnzlr+ # encoding: [0x4f,0x20,0x00,0x20]
bdnzlr+
# CHECK: bdnzl+ target # encoding: [0x43,0x20,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bdnzl+ target
# CHECK: bdnzla+ target # encoding: [0x43,0x20,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bdnzla+ target
# CHECK: bdnzlrl+ # encoding: [0x4f,0x20,0x00,0x21]
bdnzlrl+
# CHECK: bdnz- target # encoding: [0x43,0x00,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bdnz- target
# CHECK: bdnza- target # encoding: [0x43,0x00,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bdnza- target
# CHECK: bdnzlr- # encoding: [0x4f,0x00,0x00,0x20]
bdnzlr-
# CHECK: bdnzl- target # encoding: [0x43,0x00,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bdnzl- target
# CHECK: bdnzla- target # encoding: [0x43,0x00,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bdnzla- target
# CHECK: bdnzlrl- # encoding: [0x4f,0x00,0x00,0x21]
bdnzlrl-
[PowerPC] Add t/f branch mnemonics to asm parser This adds the bt/bf/bd(n)zt/bd(n)zf mnemonics as aliases for the asm parser, resolving to the generic conditional patterns. llvm-svn: 184725
2013-06-24 20:49:20 +08:00
# CHECK: bc 8, 2, target # encoding: [0x41,0x02,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bdnzt 2, target
# CHECK: bca 8, 2, target # encoding: [0x41,0x02,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bdnzta 2, target
# CHECK: bclr 8, 2, 0 # encoding: [0x4d,0x02,0x00,0x20]
bdnztlr 2
# CHECK: bcl 8, 2, target # encoding: [0x41,0x02,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bdnztl 2, target
# CHECK: bcla 8, 2, target # encoding: [0x41,0x02,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bdnztla 2, target
# CHECK: bclrl 8, 2, 0 # encoding: [0x4d,0x02,0x00,0x21]
bdnztlrl 2
# CHECK: bc 0, 2, target # encoding: [0x40,0x02,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bdnzf 2, target
# CHECK: bca 0, 2, target # encoding: [0x40,0x02,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bdnzfa 2, target
# CHECK: bclr 0, 2, 0 # encoding: [0x4c,0x02,0x00,0x20]
bdnzflr 2
# CHECK: bcl 0, 2, target # encoding: [0x40,0x02,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bdnzfl 2, target
# CHECK: bcla 0, 2, target # encoding: [0x40,0x02,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bdnzfla 2, target
# CHECK: bclrl 0, 2, 0 # encoding: [0x4c,0x02,0x00,0x21]
bdnzflrl 2
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bdz target # encoding: [0x42,0x40,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bdz target
[PowerPC] Support absolute branches There is currently only limited support for the "absolute" variants of branch instructions. This patch adds support for the absolute variants of all branches that are currently otherwise supported. This requires adding new fixup types so that the correct variant of relocation type can be selected by the object writer. While the compiler will continue to usually choose the relative branch variants, this will allow the asm parser to fully support the absolute branches, with either immediate (numerical) or symbolic target addresses. No change in code generation intended. llvm-svn: 184721
2013-06-24 19:03:33 +08:00
# CHECK: bdza target # encoding: [0x42,0x40,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bdza target
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bdzlr # encoding: [0x4e,0x40,0x00,0x20]
bdzlr
[PowerPC] Support bd(n)zl and bd(n)zlrl This adds support for the bd(n)zl and bd(n)zlrl instructions. The patterns are currently used for the asm parser only. llvm-svn: 184720
2013-06-24 19:02:38 +08:00
# CHECK: bdzl target # encoding: [0x42,0x40,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bdzl target
[PowerPC] Support absolute branches There is currently only limited support for the "absolute" variants of branch instructions. This patch adds support for the absolute variants of all branches that are currently otherwise supported. This requires adding new fixup types so that the correct variant of relocation type can be selected by the object writer. While the compiler will continue to usually choose the relative branch variants, this will allow the asm parser to fully support the absolute branches, with either immediate (numerical) or symbolic target addresses. No change in code generation intended. llvm-svn: 184721
2013-06-24 19:03:33 +08:00
# CHECK: bdzla target # encoding: [0x42,0x40,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bdzla target
[PowerPC] Support bd(n)zl and bd(n)zlrl This adds support for the bd(n)zl and bd(n)zlrl instructions. The patterns are currently used for the asm parser only. llvm-svn: 184720
2013-06-24 19:02:38 +08:00
# CHECK: bdzlrl # encoding: [0x4e,0x40,0x00,0x21]
bdzlrl
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
[PowerPC] Add predicted forms of branches This adds support for the predicted forms of branches (+/-). There are three cases to consider: - Branches using a PPC::Predicate code For these, I've added new PPC::Predicate codes corresponding to the BO values for predicted branch forms, and updated insn printing to print them correctly. I've also added new aliases for the asm parser matching the new forms. - bt/bf I've added new aliases matching to gBC etc. - bd(n)z variants I've added new instruction patterns for the predicted forms. In all cases, the new patterns are used for the asm parser only. (The new infrastructure ought to be sufficient to allow use by the compiler too at some point.) llvm-svn: 184754
2013-06-25 00:52:04 +08:00
# CHECK: bdz+ target # encoding: [0x43,0x60,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bdz+ target
# CHECK: bdza+ target # encoding: [0x43,0x60,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bdza+ target
# CHECK: bdzlr+ # encoding: [0x4f,0x60,0x00,0x20]
bdzlr+
# CHECK: bdzl+ target # encoding: [0x43,0x60,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bdzl+ target
# CHECK: bdzla+ target # encoding: [0x43,0x60,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bdzla+ target
# CHECK: bdzlrl+ # encoding: [0x4f,0x60,0x00,0x21]
bdzlrl+
# CHECK: bdz- target # encoding: [0x43,0x40,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bdz- target
# CHECK: bdza- target # encoding: [0x43,0x40,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bdza- target
# CHECK: bdzlr- # encoding: [0x4f,0x40,0x00,0x20]
bdzlr-
# CHECK: bdzl- target # encoding: [0x43,0x40,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bdzl- target
# CHECK: bdzla- target # encoding: [0x43,0x40,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bdzla- target
# CHECK: bdzlrl- # encoding: [0x4f,0x40,0x00,0x21]
bdzlrl-
[PowerPC] Add t/f branch mnemonics to asm parser This adds the bt/bf/bd(n)zt/bd(n)zf mnemonics as aliases for the asm parser, resolving to the generic conditional patterns. llvm-svn: 184725
2013-06-24 20:49:20 +08:00
# CHECK: bc 10, 2, target # encoding: [0x41,0x42,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bdzt 2, target
# CHECK: bca 10, 2, target # encoding: [0x41,0x42,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bdzta 2, target
# CHECK: bclr 10, 2, 0 # encoding: [0x4d,0x42,0x00,0x20]
bdztlr 2
# CHECK: bcl 10, 2, target # encoding: [0x41,0x42,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bdztl 2, target
# CHECK: bcla 10, 2, target # encoding: [0x41,0x42,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bdztla 2, target
# CHECK: bclrl 10, 2, 0 # encoding: [0x4d,0x42,0x00,0x21]
bdztlrl 2
# CHECK: bc 2, 2, target # encoding: [0x40,0x42,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bdzf 2, target
# CHECK: bca 2, 2, target # encoding: [0x40,0x42,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bdzfa 2, target
# CHECK: bclr 2, 2, 0 # encoding: [0x4c,0x42,0x00,0x20]
bdzflr 2
# CHECK: bcl 2, 2, target # encoding: [0x40,0x42,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bdzfl 2, target
# CHECK: bcla 2, 2, target # encoding: [0x40,0x42,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bdzfla 2, target
# CHECK: bclrl 2, 2, 0 # encoding: [0x4c,0x42,0x00,0x21]
bdzflrl 2
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: blt 2, target # encoding: [0x41,0x88,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
blt 2, target
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: blt 0, target # encoding: [0x41,0x80,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
blt target
[PowerPC] Support absolute branches There is currently only limited support for the "absolute" variants of branch instructions. This patch adds support for the absolute variants of all branches that are currently otherwise supported. This requires adding new fixup types so that the correct variant of relocation type can be selected by the object writer. While the compiler will continue to usually choose the relative branch variants, this will allow the asm parser to fully support the absolute branches, with either immediate (numerical) or symbolic target addresses. No change in code generation intended. llvm-svn: 184721
2013-06-24 19:03:33 +08:00
# CHECK: blta 2, target # encoding: [0x41,0x88,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
blta 2, target
# CHECK: blta 0, target # encoding: [0x41,0x80,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
blta target
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bltlr 2 # encoding: [0x4d,0x88,0x00,0x20]
bltlr 2
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: bltlr 0 # encoding: [0x4d,0x80,0x00,0x20]
bltlr
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bltctr 2 # encoding: [0x4d,0x88,0x04,0x20]
bltctr 2
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: bltctr 0 # encoding: [0x4d,0x80,0x04,0x20]
bltctr
[PowerPC] Support b(cond)l in the asm parser This patch adds support for the conditional variants of bl. The pattern is currently used by the asm parser only. llvm-svn: 184719
2013-06-24 19:02:19 +08:00
# CHECK: bltl 2, target # encoding: [0x41,0x88,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bltl 2, target
# CHECK: bltl 0, target # encoding: [0x41,0x80,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bltl target
[PowerPC] Support absolute branches There is currently only limited support for the "absolute" variants of branch instructions. This patch adds support for the absolute variants of all branches that are currently otherwise supported. This requires adding new fixup types so that the correct variant of relocation type can be selected by the object writer. While the compiler will continue to usually choose the relative branch variants, this will allow the asm parser to fully support the absolute branches, with either immediate (numerical) or symbolic target addresses. No change in code generation intended. llvm-svn: 184721
2013-06-24 19:03:33 +08:00
# CHECK: bltla 2, target # encoding: [0x41,0x88,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bltla 2, target
# CHECK: bltla 0, target # encoding: [0x41,0x80,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bltla target
[PowerPC] Support blrl and variants in the asm parser This patch adds support for blrl and its conditional variants. The patterns are (currently) used for the asm parser only. llvm-svn: 184718
2013-06-24 19:01:55 +08:00
# CHECK: bltlrl 2 # encoding: [0x4d,0x88,0x00,0x21]
bltlrl 2
# CHECK: bltlrl 0 # encoding: [0x4d,0x80,0x00,0x21]
bltlrl
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bltctrl 2 # encoding: [0x4d,0x88,0x04,0x21]
bltctrl 2
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: bltctrl 0 # encoding: [0x4d,0x80,0x04,0x21]
bltctrl
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
[PowerPC] Add predicted forms of branches This adds support for the predicted forms of branches (+/-). There are three cases to consider: - Branches using a PPC::Predicate code For these, I've added new PPC::Predicate codes corresponding to the BO values for predicted branch forms, and updated insn printing to print them correctly. I've also added new aliases for the asm parser matching the new forms. - bt/bf I've added new aliases matching to gBC etc. - bd(n)z variants I've added new instruction patterns for the predicted forms. In all cases, the new patterns are used for the asm parser only. (The new infrastructure ought to be sufficient to allow use by the compiler too at some point.) llvm-svn: 184754
2013-06-25 00:52:04 +08:00
# CHECK: blt+ 2, target # encoding: [0x41,0xe8,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
blt+ 2, target
# CHECK: blt+ 0, target # encoding: [0x41,0xe0,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
blt+ target
# CHECK: blta+ 2, target # encoding: [0x41,0xe8,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
blta+ 2, target
# CHECK: blta+ 0, target # encoding: [0x41,0xe0,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
blta+ target
# CHECK: bltlr+ 2 # encoding: [0x4d,0xe8,0x00,0x20]
bltlr+ 2
# CHECK: bltlr+ 0 # encoding: [0x4d,0xe0,0x00,0x20]
bltlr+
# CHECK: bltctr+ 2 # encoding: [0x4d,0xe8,0x04,0x20]
bltctr+ 2
# CHECK: bltctr+ 0 # encoding: [0x4d,0xe0,0x04,0x20]
bltctr+
# CHECK: bltl+ 2, target # encoding: [0x41,0xe8,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bltl+ 2, target
# CHECK: bltl+ 0, target # encoding: [0x41,0xe0,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bltl+ target
# CHECK: bltla+ 2, target # encoding: [0x41,0xe8,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bltla+ 2, target
# CHECK: bltla+ 0, target # encoding: [0x41,0xe0,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bltla+ target
# CHECK: bltlrl+ 2 # encoding: [0x4d,0xe8,0x00,0x21]
bltlrl+ 2
# CHECK: bltlrl+ 0 # encoding: [0x4d,0xe0,0x00,0x21]
bltlrl+
# CHECK: bltctrl+ 2 # encoding: [0x4d,0xe8,0x04,0x21]
bltctrl+ 2
# CHECK: bltctrl+ 0 # encoding: [0x4d,0xe0,0x04,0x21]
bltctrl+
# CHECK: blt- 2, target # encoding: [0x41,0xc8,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
blt- 2, target
# CHECK: blt- 0, target # encoding: [0x41,0xc0,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
blt- target
# CHECK: blta- 2, target # encoding: [0x41,0xc8,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
blta- 2, target
# CHECK: blta- 0, target # encoding: [0x41,0xc0,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
blta- target
# CHECK: bltlr- 2 # encoding: [0x4d,0xc8,0x00,0x20]
bltlr- 2
# CHECK: bltlr- 0 # encoding: [0x4d,0xc0,0x00,0x20]
bltlr-
# CHECK: bltctr- 2 # encoding: [0x4d,0xc8,0x04,0x20]
bltctr- 2
# CHECK: bltctr- 0 # encoding: [0x4d,0xc0,0x04,0x20]
bltctr-
# CHECK: bltl- 2, target # encoding: [0x41,0xc8,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bltl- 2, target
# CHECK: bltl- 0, target # encoding: [0x41,0xc0,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bltl- target
# CHECK: bltla- 2, target # encoding: [0x41,0xc8,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bltla- 2, target
# CHECK: bltla- 0, target # encoding: [0x41,0xc0,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bltla- target
# CHECK: bltlrl- 2 # encoding: [0x4d,0xc8,0x00,0x21]
bltlrl- 2
# CHECK: bltlrl- 0 # encoding: [0x4d,0xc0,0x00,0x21]
bltlrl-
# CHECK: bltctrl- 2 # encoding: [0x4d,0xc8,0x04,0x21]
bltctrl- 2
# CHECK: bltctrl- 0 # encoding: [0x4d,0xc0,0x04,0x21]
bltctrl-
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: ble 2, target # encoding: [0x40,0x89,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
ble 2, target
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: ble 0, target # encoding: [0x40,0x81,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
ble target
[PowerPC] Support absolute branches There is currently only limited support for the "absolute" variants of branch instructions. This patch adds support for the absolute variants of all branches that are currently otherwise supported. This requires adding new fixup types so that the correct variant of relocation type can be selected by the object writer. While the compiler will continue to usually choose the relative branch variants, this will allow the asm parser to fully support the absolute branches, with either immediate (numerical) or symbolic target addresses. No change in code generation intended. llvm-svn: 184721
2013-06-24 19:03:33 +08:00
# CHECK: blea 2, target # encoding: [0x40,0x89,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
blea 2, target
# CHECK: blea 0, target # encoding: [0x40,0x81,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
blea target
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: blelr 2 # encoding: [0x4c,0x89,0x00,0x20]
blelr 2
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: blelr 0 # encoding: [0x4c,0x81,0x00,0x20]
blelr
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: blectr 2 # encoding: [0x4c,0x89,0x04,0x20]
blectr 2
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: blectr 0 # encoding: [0x4c,0x81,0x04,0x20]
blectr
[PowerPC] Support b(cond)l in the asm parser This patch adds support for the conditional variants of bl. The pattern is currently used by the asm parser only. llvm-svn: 184719
2013-06-24 19:02:19 +08:00
# CHECK: blel 2, target # encoding: [0x40,0x89,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
blel 2, target
# CHECK: blel 0, target # encoding: [0x40,0x81,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
blel target
[PowerPC] Support absolute branches There is currently only limited support for the "absolute" variants of branch instructions. This patch adds support for the absolute variants of all branches that are currently otherwise supported. This requires adding new fixup types so that the correct variant of relocation type can be selected by the object writer. While the compiler will continue to usually choose the relative branch variants, this will allow the asm parser to fully support the absolute branches, with either immediate (numerical) or symbolic target addresses. No change in code generation intended. llvm-svn: 184721
2013-06-24 19:03:33 +08:00
# CHECK: blela 2, target # encoding: [0x40,0x89,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
blela 2, target
# CHECK: blela 0, target # encoding: [0x40,0x81,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
blela target
[PowerPC] Support blrl and variants in the asm parser This patch adds support for blrl and its conditional variants. The patterns are (currently) used for the asm parser only. llvm-svn: 184718
2013-06-24 19:01:55 +08:00
# CHECK: blelrl 2 # encoding: [0x4c,0x89,0x00,0x21]
blelrl 2
# CHECK: blelrl 0 # encoding: [0x4c,0x81,0x00,0x21]
blelrl
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: blectrl 2 # encoding: [0x4c,0x89,0x04,0x21]
blectrl 2
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: blectrl 0 # encoding: [0x4c,0x81,0x04,0x21]
blectrl
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
[PowerPC] Add predicted forms of branches This adds support for the predicted forms of branches (+/-). There are three cases to consider: - Branches using a PPC::Predicate code For these, I've added new PPC::Predicate codes corresponding to the BO values for predicted branch forms, and updated insn printing to print them correctly. I've also added new aliases for the asm parser matching the new forms. - bt/bf I've added new aliases matching to gBC etc. - bd(n)z variants I've added new instruction patterns for the predicted forms. In all cases, the new patterns are used for the asm parser only. (The new infrastructure ought to be sufficient to allow use by the compiler too at some point.) llvm-svn: 184754
2013-06-25 00:52:04 +08:00
# CHECK: ble+ 2, target # encoding: [0x40,0xe9,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
ble+ 2, target
# CHECK: ble+ 0, target # encoding: [0x40,0xe1,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
ble+ target
# CHECK: blea+ 2, target # encoding: [0x40,0xe9,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
blea+ 2, target
# CHECK: blea+ 0, target # encoding: [0x40,0xe1,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
blea+ target
# CHECK: blelr+ 2 # encoding: [0x4c,0xe9,0x00,0x20]
blelr+ 2
# CHECK: blelr+ 0 # encoding: [0x4c,0xe1,0x00,0x20]
blelr+
# CHECK: blectr+ 2 # encoding: [0x4c,0xe9,0x04,0x20]
blectr+ 2
# CHECK: blectr+ 0 # encoding: [0x4c,0xe1,0x04,0x20]
blectr+
# CHECK: blel+ 2, target # encoding: [0x40,0xe9,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
blel+ 2, target
# CHECK: blel+ 0, target # encoding: [0x40,0xe1,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
blel+ target
# CHECK: blela+ 2, target # encoding: [0x40,0xe9,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
blela+ 2, target
# CHECK: blela+ 0, target # encoding: [0x40,0xe1,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
blela+ target
# CHECK: blelrl+ 2 # encoding: [0x4c,0xe9,0x00,0x21]
blelrl+ 2
# CHECK: blelrl+ 0 # encoding: [0x4c,0xe1,0x00,0x21]
blelrl+
# CHECK: blectrl+ 2 # encoding: [0x4c,0xe9,0x04,0x21]
blectrl+ 2
# CHECK: blectrl+ 0 # encoding: [0x4c,0xe1,0x04,0x21]
blectrl+
# CHECK: ble- 2, target # encoding: [0x40,0xc9,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
ble- 2, target
# CHECK: ble- 0, target # encoding: [0x40,0xc1,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
ble- target
# CHECK: blea- 2, target # encoding: [0x40,0xc9,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
blea- 2, target
# CHECK: blea- 0, target # encoding: [0x40,0xc1,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
blea- target
# CHECK: blelr- 2 # encoding: [0x4c,0xc9,0x00,0x20]
blelr- 2
# CHECK: blelr- 0 # encoding: [0x4c,0xc1,0x00,0x20]
blelr-
# CHECK: blectr- 2 # encoding: [0x4c,0xc9,0x04,0x20]
blectr- 2
# CHECK: blectr- 0 # encoding: [0x4c,0xc1,0x04,0x20]
blectr-
# CHECK: blel- 2, target # encoding: [0x40,0xc9,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
blel- 2, target
# CHECK: blel- 0, target # encoding: [0x40,0xc1,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
blel- target
# CHECK: blela- 2, target # encoding: [0x40,0xc9,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
blela- 2, target
# CHECK: blela- 0, target # encoding: [0x40,0xc1,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
blela- target
# CHECK: blelrl- 2 # encoding: [0x4c,0xc9,0x00,0x21]
blelrl- 2
# CHECK: blelrl- 0 # encoding: [0x4c,0xc1,0x00,0x21]
blelrl-
# CHECK: blectrl- 2 # encoding: [0x4c,0xc9,0x04,0x21]
blectrl- 2
# CHECK: blectrl- 0 # encoding: [0x4c,0xc1,0x04,0x21]
blectrl-
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: beq 2, target # encoding: [0x41,0x8a,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
beq 2, target
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: beq 0, target # encoding: [0x41,0x82,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
beq target
[PowerPC] Support absolute branches There is currently only limited support for the "absolute" variants of branch instructions. This patch adds support for the absolute variants of all branches that are currently otherwise supported. This requires adding new fixup types so that the correct variant of relocation type can be selected by the object writer. While the compiler will continue to usually choose the relative branch variants, this will allow the asm parser to fully support the absolute branches, with either immediate (numerical) or symbolic target addresses. No change in code generation intended. llvm-svn: 184721
2013-06-24 19:03:33 +08:00
# CHECK: beqa 2, target # encoding: [0x41,0x8a,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
beqa 2, target
# CHECK: beqa 0, target # encoding: [0x41,0x82,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
beqa target
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: beqlr 2 # encoding: [0x4d,0x8a,0x00,0x20]
beqlr 2
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: beqlr 0 # encoding: [0x4d,0x82,0x00,0x20]
beqlr
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: beqctr 2 # encoding: [0x4d,0x8a,0x04,0x20]
beqctr 2
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: beqctr 0 # encoding: [0x4d,0x82,0x04,0x20]
beqctr
[PowerPC] Support b(cond)l in the asm parser This patch adds support for the conditional variants of bl. The pattern is currently used by the asm parser only. llvm-svn: 184719
2013-06-24 19:02:19 +08:00
# CHECK: beql 2, target # encoding: [0x41,0x8a,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
beql 2, target
# CHECK: beql 0, target # encoding: [0x41,0x82,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
beql target
[PowerPC] Support absolute branches There is currently only limited support for the "absolute" variants of branch instructions. This patch adds support for the absolute variants of all branches that are currently otherwise supported. This requires adding new fixup types so that the correct variant of relocation type can be selected by the object writer. While the compiler will continue to usually choose the relative branch variants, this will allow the asm parser to fully support the absolute branches, with either immediate (numerical) or symbolic target addresses. No change in code generation intended. llvm-svn: 184721
2013-06-24 19:03:33 +08:00
# CHECK: beqla 2, target # encoding: [0x41,0x8a,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
beqla 2, target
# CHECK: beqla 0, target # encoding: [0x41,0x82,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
beqla target
[PowerPC] Support blrl and variants in the asm parser This patch adds support for blrl and its conditional variants. The patterns are (currently) used for the asm parser only. llvm-svn: 184718
2013-06-24 19:01:55 +08:00
# CHECK: beqlrl 2 # encoding: [0x4d,0x8a,0x00,0x21]
beqlrl 2
# CHECK: beqlrl 0 # encoding: [0x4d,0x82,0x00,0x21]
beqlrl
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: beqctrl 2 # encoding: [0x4d,0x8a,0x04,0x21]
beqctrl 2
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: beqctrl 0 # encoding: [0x4d,0x82,0x04,0x21]
beqctrl
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
[PowerPC] Add predicted forms of branches This adds support for the predicted forms of branches (+/-). There are three cases to consider: - Branches using a PPC::Predicate code For these, I've added new PPC::Predicate codes corresponding to the BO values for predicted branch forms, and updated insn printing to print them correctly. I've also added new aliases for the asm parser matching the new forms. - bt/bf I've added new aliases matching to gBC etc. - bd(n)z variants I've added new instruction patterns for the predicted forms. In all cases, the new patterns are used for the asm parser only. (The new infrastructure ought to be sufficient to allow use by the compiler too at some point.) llvm-svn: 184754
2013-06-25 00:52:04 +08:00
# CHECK: beq+ 2, target # encoding: [0x41,0xea,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
beq+ 2, target
# CHECK: beq+ 0, target # encoding: [0x41,0xe2,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
beq+ target
# CHECK: beqa+ 2, target # encoding: [0x41,0xea,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
beqa+ 2, target
# CHECK: beqa+ 0, target # encoding: [0x41,0xe2,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
beqa+ target
# CHECK: beqlr+ 2 # encoding: [0x4d,0xea,0x00,0x20]
beqlr+ 2
# CHECK: beqlr+ 0 # encoding: [0x4d,0xe2,0x00,0x20]
beqlr+
# CHECK: beqctr+ 2 # encoding: [0x4d,0xea,0x04,0x20]
beqctr+ 2
# CHECK: beqctr+ 0 # encoding: [0x4d,0xe2,0x04,0x20]
beqctr+
# CHECK: beql+ 2, target # encoding: [0x41,0xea,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
beql+ 2, target
# CHECK: beql+ 0, target # encoding: [0x41,0xe2,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
beql+ target
# CHECK: beqla+ 2, target # encoding: [0x41,0xea,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
beqla+ 2, target
# CHECK: beqla+ 0, target # encoding: [0x41,0xe2,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
beqla+ target
# CHECK: beqlrl+ 2 # encoding: [0x4d,0xea,0x00,0x21]
beqlrl+ 2
# CHECK: beqlrl+ 0 # encoding: [0x4d,0xe2,0x00,0x21]
beqlrl+
# CHECK: beqctrl+ 2 # encoding: [0x4d,0xea,0x04,0x21]
beqctrl+ 2
# CHECK: beqctrl+ 0 # encoding: [0x4d,0xe2,0x04,0x21]
beqctrl+
# CHECK: beq- 2, target # encoding: [0x41,0xca,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
beq- 2, target
# CHECK: beq- 0, target # encoding: [0x41,0xc2,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
beq- target
# CHECK: beqa- 2, target # encoding: [0x41,0xca,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
beqa- 2, target
# CHECK: beqa- 0, target # encoding: [0x41,0xc2,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
beqa- target
# CHECK: beqlr- 2 # encoding: [0x4d,0xca,0x00,0x20]
beqlr- 2
# CHECK: beqlr- 0 # encoding: [0x4d,0xc2,0x00,0x20]
beqlr-
# CHECK: beqctr- 2 # encoding: [0x4d,0xca,0x04,0x20]
beqctr- 2
# CHECK: beqctr- 0 # encoding: [0x4d,0xc2,0x04,0x20]
beqctr-
# CHECK: beql- 2, target # encoding: [0x41,0xca,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
beql- 2, target
# CHECK: beql- 0, target # encoding: [0x41,0xc2,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
beql- target
# CHECK: beqla- 2, target # encoding: [0x41,0xca,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
beqla- 2, target
# CHECK: beqla- 0, target # encoding: [0x41,0xc2,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
beqla- target
# CHECK: beqlrl- 2 # encoding: [0x4d,0xca,0x00,0x21]
beqlrl- 2
# CHECK: beqlrl- 0 # encoding: [0x4d,0xc2,0x00,0x21]
beqlrl-
# CHECK: beqctrl- 2 # encoding: [0x4d,0xca,0x04,0x21]
beqctrl- 2
# CHECK: beqctrl- 0 # encoding: [0x4d,0xc2,0x04,0x21]
beqctrl-
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bge 2, target # encoding: [0x40,0x88,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bge 2, target
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: bge 0, target # encoding: [0x40,0x80,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bge target
[PowerPC] Support absolute branches There is currently only limited support for the "absolute" variants of branch instructions. This patch adds support for the absolute variants of all branches that are currently otherwise supported. This requires adding new fixup types so that the correct variant of relocation type can be selected by the object writer. While the compiler will continue to usually choose the relative branch variants, this will allow the asm parser to fully support the absolute branches, with either immediate (numerical) or symbolic target addresses. No change in code generation intended. llvm-svn: 184721
2013-06-24 19:03:33 +08:00
# CHECK: bgea 2, target # encoding: [0x40,0x88,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bgea 2, target
# CHECK: bgea 0, target # encoding: [0x40,0x80,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bgea target
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bgelr 2 # encoding: [0x4c,0x88,0x00,0x20]
bgelr 2
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: bgelr 0 # encoding: [0x4c,0x80,0x00,0x20]
bgelr
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bgectr 2 # encoding: [0x4c,0x88,0x04,0x20]
bgectr 2
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: bgectr 0 # encoding: [0x4c,0x80,0x04,0x20]
bgectr
[PowerPC] Support b(cond)l in the asm parser This patch adds support for the conditional variants of bl. The pattern is currently used by the asm parser only. llvm-svn: 184719
2013-06-24 19:02:19 +08:00
# CHECK: bgel 2, target # encoding: [0x40,0x88,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bgel 2, target
# CHECK: bgel 0, target # encoding: [0x40,0x80,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bgel target
[PowerPC] Support absolute branches There is currently only limited support for the "absolute" variants of branch instructions. This patch adds support for the absolute variants of all branches that are currently otherwise supported. This requires adding new fixup types so that the correct variant of relocation type can be selected by the object writer. While the compiler will continue to usually choose the relative branch variants, this will allow the asm parser to fully support the absolute branches, with either immediate (numerical) or symbolic target addresses. No change in code generation intended. llvm-svn: 184721
2013-06-24 19:03:33 +08:00
# CHECK: bgela 2, target # encoding: [0x40,0x88,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bgela 2, target
# CHECK: bgela 0, target # encoding: [0x40,0x80,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bgela target
[PowerPC] Support blrl and variants in the asm parser This patch adds support for blrl and its conditional variants. The patterns are (currently) used for the asm parser only. llvm-svn: 184718
2013-06-24 19:01:55 +08:00
# CHECK: bgelrl 2 # encoding: [0x4c,0x88,0x00,0x21]
bgelrl 2
# CHECK: bgelrl 0 # encoding: [0x4c,0x80,0x00,0x21]
bgelrl
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bgectrl 2 # encoding: [0x4c,0x88,0x04,0x21]
bgectrl 2
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: bgectrl 0 # encoding: [0x4c,0x80,0x04,0x21]
bgectrl
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
[PowerPC] Add predicted forms of branches This adds support for the predicted forms of branches (+/-). There are three cases to consider: - Branches using a PPC::Predicate code For these, I've added new PPC::Predicate codes corresponding to the BO values for predicted branch forms, and updated insn printing to print them correctly. I've also added new aliases for the asm parser matching the new forms. - bt/bf I've added new aliases matching to gBC etc. - bd(n)z variants I've added new instruction patterns for the predicted forms. In all cases, the new patterns are used for the asm parser only. (The new infrastructure ought to be sufficient to allow use by the compiler too at some point.) llvm-svn: 184754
2013-06-25 00:52:04 +08:00
# CHECK: bge+ 2, target # encoding: [0x40,0xe8,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bge+ 2, target
# CHECK: bge+ 0, target # encoding: [0x40,0xe0,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bge+ target
# CHECK: bgea+ 2, target # encoding: [0x40,0xe8,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bgea+ 2, target
# CHECK: bgea+ 0, target # encoding: [0x40,0xe0,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bgea+ target
# CHECK: bgelr+ 2 # encoding: [0x4c,0xe8,0x00,0x20]
bgelr+ 2
# CHECK: bgelr+ 0 # encoding: [0x4c,0xe0,0x00,0x20]
bgelr+
# CHECK: bgectr+ 2 # encoding: [0x4c,0xe8,0x04,0x20]
bgectr+ 2
# CHECK: bgectr+ 0 # encoding: [0x4c,0xe0,0x04,0x20]
bgectr+
# CHECK: bgel+ 2, target # encoding: [0x40,0xe8,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bgel+ 2, target
# CHECK: bgel+ 0, target # encoding: [0x40,0xe0,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bgel+ target
# CHECK: bgela+ 2, target # encoding: [0x40,0xe8,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bgela+ 2, target
# CHECK: bgela+ 0, target # encoding: [0x40,0xe0,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bgela+ target
# CHECK: bgelrl+ 2 # encoding: [0x4c,0xe8,0x00,0x21]
bgelrl+ 2
# CHECK: bgelrl+ 0 # encoding: [0x4c,0xe0,0x00,0x21]
bgelrl+
# CHECK: bgectrl+ 2 # encoding: [0x4c,0xe8,0x04,0x21]
bgectrl+ 2
# CHECK: bgectrl+ 0 # encoding: [0x4c,0xe0,0x04,0x21]
bgectrl+
# CHECK: bge- 2, target # encoding: [0x40,0xc8,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bge- 2, target
# CHECK: bge- 0, target # encoding: [0x40,0xc0,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bge- target
# CHECK: bgea- 2, target # encoding: [0x40,0xc8,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bgea- 2, target
# CHECK: bgea- 0, target # encoding: [0x40,0xc0,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bgea- target
# CHECK: bgelr- 2 # encoding: [0x4c,0xc8,0x00,0x20]
bgelr- 2
# CHECK: bgelr- 0 # encoding: [0x4c,0xc0,0x00,0x20]
bgelr-
# CHECK: bgectr- 2 # encoding: [0x4c,0xc8,0x04,0x20]
bgectr- 2
# CHECK: bgectr- 0 # encoding: [0x4c,0xc0,0x04,0x20]
bgectr-
# CHECK: bgel- 2, target # encoding: [0x40,0xc8,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bgel- 2, target
# CHECK: bgel- 0, target # encoding: [0x40,0xc0,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bgel- target
# CHECK: bgela- 2, target # encoding: [0x40,0xc8,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bgela- 2, target
# CHECK: bgela- 0, target # encoding: [0x40,0xc0,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bgela- target
# CHECK: bgelrl- 2 # encoding: [0x4c,0xc8,0x00,0x21]
bgelrl- 2
# CHECK: bgelrl- 0 # encoding: [0x4c,0xc0,0x00,0x21]
bgelrl-
# CHECK: bgectrl- 2 # encoding: [0x4c,0xc8,0x04,0x21]
bgectrl- 2
# CHECK: bgectrl- 0 # encoding: [0x4c,0xc0,0x04,0x21]
bgectrl-
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bgt 2, target # encoding: [0x41,0x89,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bgt 2, target
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: bgt 0, target # encoding: [0x41,0x81,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bgt target
[PowerPC] Support absolute branches There is currently only limited support for the "absolute" variants of branch instructions. This patch adds support for the absolute variants of all branches that are currently otherwise supported. This requires adding new fixup types so that the correct variant of relocation type can be selected by the object writer. While the compiler will continue to usually choose the relative branch variants, this will allow the asm parser to fully support the absolute branches, with either immediate (numerical) or symbolic target addresses. No change in code generation intended. llvm-svn: 184721
2013-06-24 19:03:33 +08:00
# CHECK: bgta 2, target # encoding: [0x41,0x89,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bgta 2, target
# CHECK: bgta 0, target # encoding: [0x41,0x81,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bgta target
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bgtlr 2 # encoding: [0x4d,0x89,0x00,0x20]
bgtlr 2
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: bgtlr 0 # encoding: [0x4d,0x81,0x00,0x20]
bgtlr
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bgtctr 2 # encoding: [0x4d,0x89,0x04,0x20]
bgtctr 2
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: bgtctr 0 # encoding: [0x4d,0x81,0x04,0x20]
bgtctr
[PowerPC] Support b(cond)l in the asm parser This patch adds support for the conditional variants of bl. The pattern is currently used by the asm parser only. llvm-svn: 184719
2013-06-24 19:02:19 +08:00
# CHECK: bgtl 2, target # encoding: [0x41,0x89,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bgtl 2, target
# CHECK: bgtl 0, target # encoding: [0x41,0x81,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bgtl target
[PowerPC] Support absolute branches There is currently only limited support for the "absolute" variants of branch instructions. This patch adds support for the absolute variants of all branches that are currently otherwise supported. This requires adding new fixup types so that the correct variant of relocation type can be selected by the object writer. While the compiler will continue to usually choose the relative branch variants, this will allow the asm parser to fully support the absolute branches, with either immediate (numerical) or symbolic target addresses. No change in code generation intended. llvm-svn: 184721
2013-06-24 19:03:33 +08:00
# CHECK: bgtla 2, target # encoding: [0x41,0x89,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bgtla 2, target
# CHECK: bgtla 0, target # encoding: [0x41,0x81,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bgtla target
[PowerPC] Support blrl and variants in the asm parser This patch adds support for blrl and its conditional variants. The patterns are (currently) used for the asm parser only. llvm-svn: 184718
2013-06-24 19:01:55 +08:00
# CHECK: bgtlrl 2 # encoding: [0x4d,0x89,0x00,0x21]
bgtlrl 2
# CHECK: bgtlrl 0 # encoding: [0x4d,0x81,0x00,0x21]
bgtlrl
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bgtctrl 2 # encoding: [0x4d,0x89,0x04,0x21]
bgtctrl 2
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: bgtctrl 0 # encoding: [0x4d,0x81,0x04,0x21]
bgtctrl
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
[PowerPC] Add predicted forms of branches This adds support for the predicted forms of branches (+/-). There are three cases to consider: - Branches using a PPC::Predicate code For these, I've added new PPC::Predicate codes corresponding to the BO values for predicted branch forms, and updated insn printing to print them correctly. I've also added new aliases for the asm parser matching the new forms. - bt/bf I've added new aliases matching to gBC etc. - bd(n)z variants I've added new instruction patterns for the predicted forms. In all cases, the new patterns are used for the asm parser only. (The new infrastructure ought to be sufficient to allow use by the compiler too at some point.) llvm-svn: 184754
2013-06-25 00:52:04 +08:00
# CHECK: bgt+ 2, target # encoding: [0x41,0xe9,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bgt+ 2, target
# CHECK: bgt+ 0, target # encoding: [0x41,0xe1,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bgt+ target
# CHECK: bgta+ 2, target # encoding: [0x41,0xe9,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bgta+ 2, target
# CHECK: bgta+ 0, target # encoding: [0x41,0xe1,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bgta+ target
# CHECK: bgtlr+ 2 # encoding: [0x4d,0xe9,0x00,0x20]
bgtlr+ 2
# CHECK: bgtlr+ 0 # encoding: [0x4d,0xe1,0x00,0x20]
bgtlr+
# CHECK: bgtctr+ 2 # encoding: [0x4d,0xe9,0x04,0x20]
bgtctr+ 2
# CHECK: bgtctr+ 0 # encoding: [0x4d,0xe1,0x04,0x20]
bgtctr+
# CHECK: bgtl+ 2, target # encoding: [0x41,0xe9,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bgtl+ 2, target
# CHECK: bgtl+ 0, target # encoding: [0x41,0xe1,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bgtl+ target
# CHECK: bgtla+ 2, target # encoding: [0x41,0xe9,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bgtla+ 2, target
# CHECK: bgtla+ 0, target # encoding: [0x41,0xe1,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bgtla+ target
# CHECK: bgtlrl+ 2 # encoding: [0x4d,0xe9,0x00,0x21]
bgtlrl+ 2
# CHECK: bgtlrl+ 0 # encoding: [0x4d,0xe1,0x00,0x21]
bgtlrl+
# CHECK: bgtctrl+ 2 # encoding: [0x4d,0xe9,0x04,0x21]
bgtctrl+ 2
# CHECK: bgtctrl+ 0 # encoding: [0x4d,0xe1,0x04,0x21]
bgtctrl+
# CHECK: bgt- 2, target # encoding: [0x41,0xc9,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bgt- 2, target
# CHECK: bgt- 0, target # encoding: [0x41,0xc1,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bgt- target
# CHECK: bgta- 2, target # encoding: [0x41,0xc9,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bgta- 2, target
# CHECK: bgta- 0, target # encoding: [0x41,0xc1,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bgta- target
# CHECK: bgtlr- 2 # encoding: [0x4d,0xc9,0x00,0x20]
bgtlr- 2
# CHECK: bgtlr- 0 # encoding: [0x4d,0xc1,0x00,0x20]
bgtlr-
# CHECK: bgtctr- 2 # encoding: [0x4d,0xc9,0x04,0x20]
bgtctr- 2
# CHECK: bgtctr- 0 # encoding: [0x4d,0xc1,0x04,0x20]
bgtctr-
# CHECK: bgtl- 2, target # encoding: [0x41,0xc9,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bgtl- 2, target
# CHECK: bgtl- 0, target # encoding: [0x41,0xc1,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bgtl- target
# CHECK: bgtla- 2, target # encoding: [0x41,0xc9,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bgtla- 2, target
# CHECK: bgtla- 0, target # encoding: [0x41,0xc1,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bgtla- target
# CHECK: bgtlrl- 2 # encoding: [0x4d,0xc9,0x00,0x21]
bgtlrl- 2
# CHECK: bgtlrl- 0 # encoding: [0x4d,0xc1,0x00,0x21]
bgtlrl-
# CHECK: bgtctrl- 2 # encoding: [0x4d,0xc9,0x04,0x21]
bgtctrl- 2
# CHECK: bgtctrl- 0 # encoding: [0x4d,0xc1,0x04,0x21]
bgtctrl-
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bge 2, target # encoding: [0x40,0x88,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnl 2, target
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: bge 0, target # encoding: [0x40,0x80,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnl target
[PowerPC] Support absolute branches There is currently only limited support for the "absolute" variants of branch instructions. This patch adds support for the absolute variants of all branches that are currently otherwise supported. This requires adding new fixup types so that the correct variant of relocation type can be selected by the object writer. While the compiler will continue to usually choose the relative branch variants, this will allow the asm parser to fully support the absolute branches, with either immediate (numerical) or symbolic target addresses. No change in code generation intended. llvm-svn: 184721
2013-06-24 19:03:33 +08:00
# CHECK: bgea 2, target # encoding: [0x40,0x88,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnla 2, target
# CHECK: bgea 0, target # encoding: [0x40,0x80,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnla target
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bgelr 2 # encoding: [0x4c,0x88,0x00,0x20]
bnllr 2
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: bgelr 0 # encoding: [0x4c,0x80,0x00,0x20]
bnllr
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bgectr 2 # encoding: [0x4c,0x88,0x04,0x20]
bnlctr 2
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: bgectr 0 # encoding: [0x4c,0x80,0x04,0x20]
bnlctr
[PowerPC] Support b(cond)l in the asm parser This patch adds support for the conditional variants of bl. The pattern is currently used by the asm parser only. llvm-svn: 184719
2013-06-24 19:02:19 +08:00
# CHECK: bgel 2, target # encoding: [0x40,0x88,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnll 2, target
# CHECK: bgel 0, target # encoding: [0x40,0x80,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnll target
[PowerPC] Support absolute branches There is currently only limited support for the "absolute" variants of branch instructions. This patch adds support for the absolute variants of all branches that are currently otherwise supported. This requires adding new fixup types so that the correct variant of relocation type can be selected by the object writer. While the compiler will continue to usually choose the relative branch variants, this will allow the asm parser to fully support the absolute branches, with either immediate (numerical) or symbolic target addresses. No change in code generation intended. llvm-svn: 184721
2013-06-24 19:03:33 +08:00
# CHECK: bgela 2, target # encoding: [0x40,0x88,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnlla 2, target
# CHECK: bgela 0, target # encoding: [0x40,0x80,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnlla target
[PowerPC] Support blrl and variants in the asm parser This patch adds support for blrl and its conditional variants. The patterns are (currently) used for the asm parser only. llvm-svn: 184718
2013-06-24 19:01:55 +08:00
# CHECK: bgelrl 2 # encoding: [0x4c,0x88,0x00,0x21]
bnllrl 2
# CHECK: bgelrl 0 # encoding: [0x4c,0x80,0x00,0x21]
bnllrl
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bgectrl 2 # encoding: [0x4c,0x88,0x04,0x21]
bnlctrl 2
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: bgectrl 0 # encoding: [0x4c,0x80,0x04,0x21]
bnlctrl
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
[PowerPC] Add predicted forms of branches This adds support for the predicted forms of branches (+/-). There are three cases to consider: - Branches using a PPC::Predicate code For these, I've added new PPC::Predicate codes corresponding to the BO values for predicted branch forms, and updated insn printing to print them correctly. I've also added new aliases for the asm parser matching the new forms. - bt/bf I've added new aliases matching to gBC etc. - bd(n)z variants I've added new instruction patterns for the predicted forms. In all cases, the new patterns are used for the asm parser only. (The new infrastructure ought to be sufficient to allow use by the compiler too at some point.) llvm-svn: 184754
2013-06-25 00:52:04 +08:00
# CHECK: bge+ 2, target # encoding: [0x40,0xe8,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnl+ 2, target
# CHECK: bge+ 0, target # encoding: [0x40,0xe0,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnl+ target
# CHECK: bgea+ 2, target # encoding: [0x40,0xe8,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnla+ 2, target
# CHECK: bgea+ 0, target # encoding: [0x40,0xe0,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnla+ target
# CHECK: bgelr+ 2 # encoding: [0x4c,0xe8,0x00,0x20]
bnllr+ 2
# CHECK: bgelr+ 0 # encoding: [0x4c,0xe0,0x00,0x20]
bnllr+
# CHECK: bgectr+ 2 # encoding: [0x4c,0xe8,0x04,0x20]
bnlctr+ 2
# CHECK: bgectr+ 0 # encoding: [0x4c,0xe0,0x04,0x20]
bnlctr+
# CHECK: bgel+ 2, target # encoding: [0x40,0xe8,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnll+ 2, target
# CHECK: bgel+ 0, target # encoding: [0x40,0xe0,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnll+ target
# CHECK: bgela+ 2, target # encoding: [0x40,0xe8,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnlla+ 2, target
# CHECK: bgela+ 0, target # encoding: [0x40,0xe0,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnlla+ target
# CHECK: bgelrl+ 2 # encoding: [0x4c,0xe8,0x00,0x21]
bnllrl+ 2
# CHECK: bgelrl+ 0 # encoding: [0x4c,0xe0,0x00,0x21]
bnllrl+
# CHECK: bgectrl+ 2 # encoding: [0x4c,0xe8,0x04,0x21]
bnlctrl+ 2
# CHECK: bgectrl+ 0 # encoding: [0x4c,0xe0,0x04,0x21]
bnlctrl+
# CHECK: bge- 2, target # encoding: [0x40,0xc8,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnl- 2, target
# CHECK: bge- 0, target # encoding: [0x40,0xc0,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnl- target
# CHECK: bgea- 2, target # encoding: [0x40,0xc8,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnla- 2, target
# CHECK: bgea- 0, target # encoding: [0x40,0xc0,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnla- target
# CHECK: bgelr- 2 # encoding: [0x4c,0xc8,0x00,0x20]
bnllr- 2
# CHECK: bgelr- 0 # encoding: [0x4c,0xc0,0x00,0x20]
bnllr-
# CHECK: bgectr- 2 # encoding: [0x4c,0xc8,0x04,0x20]
bnlctr- 2
# CHECK: bgectr- 0 # encoding: [0x4c,0xc0,0x04,0x20]
bnlctr-
# CHECK: bgel- 2, target # encoding: [0x40,0xc8,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnll- 2, target
# CHECK: bgel- 0, target # encoding: [0x40,0xc0,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnll- target
# CHECK: bgela- 2, target # encoding: [0x40,0xc8,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnlla- 2, target
# CHECK: bgela- 0, target # encoding: [0x40,0xc0,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnlla- target
# CHECK: bgelrl- 2 # encoding: [0x4c,0xc8,0x00,0x21]
bnllrl- 2
# CHECK: bgelrl- 0 # encoding: [0x4c,0xc0,0x00,0x21]
bnllrl-
# CHECK: bgectrl- 2 # encoding: [0x4c,0xc8,0x04,0x21]
bnlctrl- 2
# CHECK: bgectrl- 0 # encoding: [0x4c,0xc0,0x04,0x21]
bnlctrl-
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bne 2, target # encoding: [0x40,0x8a,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bne 2, target
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: bne 0, target # encoding: [0x40,0x82,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bne target
[PowerPC] Support absolute branches There is currently only limited support for the "absolute" variants of branch instructions. This patch adds support for the absolute variants of all branches that are currently otherwise supported. This requires adding new fixup types so that the correct variant of relocation type can be selected by the object writer. While the compiler will continue to usually choose the relative branch variants, this will allow the asm parser to fully support the absolute branches, with either immediate (numerical) or symbolic target addresses. No change in code generation intended. llvm-svn: 184721
2013-06-24 19:03:33 +08:00
# CHECK: bnea 2, target # encoding: [0x40,0x8a,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnea 2, target
# CHECK: bnea 0, target # encoding: [0x40,0x82,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnea target
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bnelr 2 # encoding: [0x4c,0x8a,0x00,0x20]
bnelr 2
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: bnelr 0 # encoding: [0x4c,0x82,0x00,0x20]
bnelr
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bnectr 2 # encoding: [0x4c,0x8a,0x04,0x20]
bnectr 2
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: bnectr 0 # encoding: [0x4c,0x82,0x04,0x20]
bnectr
[PowerPC] Support b(cond)l in the asm parser This patch adds support for the conditional variants of bl. The pattern is currently used by the asm parser only. llvm-svn: 184719
2013-06-24 19:02:19 +08:00
# CHECK: bnel 2, target # encoding: [0x40,0x8a,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnel 2, target
# CHECK: bnel 0, target # encoding: [0x40,0x82,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnel target
[PowerPC] Support absolute branches There is currently only limited support for the "absolute" variants of branch instructions. This patch adds support for the absolute variants of all branches that are currently otherwise supported. This requires adding new fixup types so that the correct variant of relocation type can be selected by the object writer. While the compiler will continue to usually choose the relative branch variants, this will allow the asm parser to fully support the absolute branches, with either immediate (numerical) or symbolic target addresses. No change in code generation intended. llvm-svn: 184721
2013-06-24 19:03:33 +08:00
# CHECK: bnela 2, target # encoding: [0x40,0x8a,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnela 2, target
# CHECK: bnela 0, target # encoding: [0x40,0x82,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnela target
[PowerPC] Support blrl and variants in the asm parser This patch adds support for blrl and its conditional variants. The patterns are (currently) used for the asm parser only. llvm-svn: 184718
2013-06-24 19:01:55 +08:00
# CHECK: bnelrl 2 # encoding: [0x4c,0x8a,0x00,0x21]
bnelrl 2
# CHECK: bnelrl 0 # encoding: [0x4c,0x82,0x00,0x21]
bnelrl
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bnectrl 2 # encoding: [0x4c,0x8a,0x04,0x21]
bnectrl 2
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: bnectrl 0 # encoding: [0x4c,0x82,0x04,0x21]
bnectrl
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
[PowerPC] Add predicted forms of branches This adds support for the predicted forms of branches (+/-). There are three cases to consider: - Branches using a PPC::Predicate code For these, I've added new PPC::Predicate codes corresponding to the BO values for predicted branch forms, and updated insn printing to print them correctly. I've also added new aliases for the asm parser matching the new forms. - bt/bf I've added new aliases matching to gBC etc. - bd(n)z variants I've added new instruction patterns for the predicted forms. In all cases, the new patterns are used for the asm parser only. (The new infrastructure ought to be sufficient to allow use by the compiler too at some point.) llvm-svn: 184754
2013-06-25 00:52:04 +08:00
# CHECK: bne+ 2, target # encoding: [0x40,0xea,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bne+ 2, target
# CHECK: bne+ 0, target # encoding: [0x40,0xe2,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bne+ target
# CHECK: bnea+ 2, target # encoding: [0x40,0xea,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnea+ 2, target
# CHECK: bnea+ 0, target # encoding: [0x40,0xe2,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnea+ target
# CHECK: bnelr+ 2 # encoding: [0x4c,0xea,0x00,0x20]
bnelr+ 2
# CHECK: bnelr+ 0 # encoding: [0x4c,0xe2,0x00,0x20]
bnelr+
# CHECK: bnectr+ 2 # encoding: [0x4c,0xea,0x04,0x20]
bnectr+ 2
# CHECK: bnectr+ 0 # encoding: [0x4c,0xe2,0x04,0x20]
bnectr+
# CHECK: bnel+ 2, target # encoding: [0x40,0xea,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnel+ 2, target
# CHECK: bnel+ 0, target # encoding: [0x40,0xe2,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnel+ target
# CHECK: bnela+ 2, target # encoding: [0x40,0xea,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnela+ 2, target
# CHECK: bnela+ 0, target # encoding: [0x40,0xe2,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnela+ target
# CHECK: bnelrl+ 2 # encoding: [0x4c,0xea,0x00,0x21]
bnelrl+ 2
# CHECK: bnelrl+ 0 # encoding: [0x4c,0xe2,0x00,0x21]
bnelrl+
# CHECK: bnectrl+ 2 # encoding: [0x4c,0xea,0x04,0x21]
bnectrl+ 2
# CHECK: bnectrl+ 0 # encoding: [0x4c,0xe2,0x04,0x21]
bnectrl+
# CHECK: bne- 2, target # encoding: [0x40,0xca,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bne- 2, target
# CHECK: bne- 0, target # encoding: [0x40,0xc2,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bne- target
# CHECK: bnea- 2, target # encoding: [0x40,0xca,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnea- 2, target
# CHECK: bnea- 0, target # encoding: [0x40,0xc2,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnea- target
# CHECK: bnelr- 2 # encoding: [0x4c,0xca,0x00,0x20]
bnelr- 2
# CHECK: bnelr- 0 # encoding: [0x4c,0xc2,0x00,0x20]
bnelr-
# CHECK: bnectr- 2 # encoding: [0x4c,0xca,0x04,0x20]
bnectr- 2
# CHECK: bnectr- 0 # encoding: [0x4c,0xc2,0x04,0x20]
bnectr-
# CHECK: bnel- 2, target # encoding: [0x40,0xca,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnel- 2, target
# CHECK: bnel- 0, target # encoding: [0x40,0xc2,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnel- target
# CHECK: bnela- 2, target # encoding: [0x40,0xca,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnela- 2, target
# CHECK: bnela- 0, target # encoding: [0x40,0xc2,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnela- target
# CHECK: bnelrl- 2 # encoding: [0x4c,0xca,0x00,0x21]
bnelrl- 2
# CHECK: bnelrl- 0 # encoding: [0x4c,0xc2,0x00,0x21]
bnelrl-
# CHECK: bnectrl- 2 # encoding: [0x4c,0xca,0x04,0x21]
bnectrl- 2
# CHECK: bnectrl- 0 # encoding: [0x4c,0xc2,0x04,0x21]
bnectrl-
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: ble 2, target # encoding: [0x40,0x89,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bng 2, target
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: ble 0, target # encoding: [0x40,0x81,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bng target
[PowerPC] Support absolute branches There is currently only limited support for the "absolute" variants of branch instructions. This patch adds support for the absolute variants of all branches that are currently otherwise supported. This requires adding new fixup types so that the correct variant of relocation type can be selected by the object writer. While the compiler will continue to usually choose the relative branch variants, this will allow the asm parser to fully support the absolute branches, with either immediate (numerical) or symbolic target addresses. No change in code generation intended. llvm-svn: 184721
2013-06-24 19:03:33 +08:00
# CHECK: blea 2, target # encoding: [0x40,0x89,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnga 2, target
# CHECK: blea 0, target # encoding: [0x40,0x81,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnga target
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: blelr 2 # encoding: [0x4c,0x89,0x00,0x20]
bnglr 2
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: blelr 0 # encoding: [0x4c,0x81,0x00,0x20]
bnglr
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: blectr 2 # encoding: [0x4c,0x89,0x04,0x20]
bngctr 2
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: blectr 0 # encoding: [0x4c,0x81,0x04,0x20]
bngctr
[PowerPC] Support b(cond)l in the asm parser This patch adds support for the conditional variants of bl. The pattern is currently used by the asm parser only. llvm-svn: 184719
2013-06-24 19:02:19 +08:00
# CHECK: blel 2, target # encoding: [0x40,0x89,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bngl 2, target
# CHECK: blel 0, target # encoding: [0x40,0x81,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bngl target
[PowerPC] Support absolute branches There is currently only limited support for the "absolute" variants of branch instructions. This patch adds support for the absolute variants of all branches that are currently otherwise supported. This requires adding new fixup types so that the correct variant of relocation type can be selected by the object writer. While the compiler will continue to usually choose the relative branch variants, this will allow the asm parser to fully support the absolute branches, with either immediate (numerical) or symbolic target addresses. No change in code generation intended. llvm-svn: 184721
2013-06-24 19:03:33 +08:00
# CHECK: blela 2, target # encoding: [0x40,0x89,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bngla 2, target
# CHECK: blela 0, target # encoding: [0x40,0x81,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bngla target
[PowerPC] Support blrl and variants in the asm parser This patch adds support for blrl and its conditional variants. The patterns are (currently) used for the asm parser only. llvm-svn: 184718
2013-06-24 19:01:55 +08:00
# CHECK: blelrl 2 # encoding: [0x4c,0x89,0x00,0x21]
bnglrl 2
# CHECK: blelrl 0 # encoding: [0x4c,0x81,0x00,0x21]
bnglrl
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: blectrl 2 # encoding: [0x4c,0x89,0x04,0x21]
bngctrl 2
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: blectrl 0 # encoding: [0x4c,0x81,0x04,0x21]
bngctrl
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
[PowerPC] Add predicted forms of branches This adds support for the predicted forms of branches (+/-). There are three cases to consider: - Branches using a PPC::Predicate code For these, I've added new PPC::Predicate codes corresponding to the BO values for predicted branch forms, and updated insn printing to print them correctly. I've also added new aliases for the asm parser matching the new forms. - bt/bf I've added new aliases matching to gBC etc. - bd(n)z variants I've added new instruction patterns for the predicted forms. In all cases, the new patterns are used for the asm parser only. (The new infrastructure ought to be sufficient to allow use by the compiler too at some point.) llvm-svn: 184754
2013-06-25 00:52:04 +08:00
# CHECK: ble+ 2, target # encoding: [0x40,0xe9,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bng+ 2, target
# CHECK: ble+ 0, target # encoding: [0x40,0xe1,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bng+ target
# CHECK: blea+ 2, target # encoding: [0x40,0xe9,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnga+ 2, target
# CHECK: blea+ 0, target # encoding: [0x40,0xe1,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnga+ target
# CHECK: blelr+ 2 # encoding: [0x4c,0xe9,0x00,0x20]
bnglr+ 2
# CHECK: blelr+ 0 # encoding: [0x4c,0xe1,0x00,0x20]
bnglr+
# CHECK: blectr+ 2 # encoding: [0x4c,0xe9,0x04,0x20]
bngctr+ 2
# CHECK: blectr+ 0 # encoding: [0x4c,0xe1,0x04,0x20]
bngctr+
# CHECK: blel+ 2, target # encoding: [0x40,0xe9,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bngl+ 2, target
# CHECK: blel+ 0, target # encoding: [0x40,0xe1,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bngl+ target
# CHECK: blela+ 2, target # encoding: [0x40,0xe9,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bngla+ 2, target
# CHECK: blela+ 0, target # encoding: [0x40,0xe1,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bngla+ target
# CHECK: blelrl+ 2 # encoding: [0x4c,0xe9,0x00,0x21]
bnglrl+ 2
# CHECK: blelrl+ 0 # encoding: [0x4c,0xe1,0x00,0x21]
bnglrl+
# CHECK: blectrl+ 2 # encoding: [0x4c,0xe9,0x04,0x21]
bngctrl+ 2
# CHECK: blectrl+ 0 # encoding: [0x4c,0xe1,0x04,0x21]
bngctrl+
# CHECK: ble- 2, target # encoding: [0x40,0xc9,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bng- 2, target
# CHECK: ble- 0, target # encoding: [0x40,0xc1,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bng- target
# CHECK: blea- 2, target # encoding: [0x40,0xc9,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnga- 2, target
# CHECK: blea- 0, target # encoding: [0x40,0xc1,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnga- target
# CHECK: blelr- 2 # encoding: [0x4c,0xc9,0x00,0x20]
bnglr- 2
# CHECK: blelr- 0 # encoding: [0x4c,0xc1,0x00,0x20]
bnglr-
# CHECK: blectr- 2 # encoding: [0x4c,0xc9,0x04,0x20]
bngctr- 2
# CHECK: blectr- 0 # encoding: [0x4c,0xc1,0x04,0x20]
bngctr-
# CHECK: blel- 2, target # encoding: [0x40,0xc9,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bngl- 2, target
# CHECK: blel- 0, target # encoding: [0x40,0xc1,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bngl- target
# CHECK: blela- 2, target # encoding: [0x40,0xc9,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bngla- 2, target
# CHECK: blela- 0, target # encoding: [0x40,0xc1,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bngla- target
# CHECK: blelrl- 2 # encoding: [0x4c,0xc9,0x00,0x21]
bnglrl- 2
# CHECK: blelrl- 0 # encoding: [0x4c,0xc1,0x00,0x21]
bnglrl-
# CHECK: blectrl- 2 # encoding: [0x4c,0xc9,0x04,0x21]
bngctrl- 2
# CHECK: blectrl- 0 # encoding: [0x4c,0xc1,0x04,0x21]
bngctrl-
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bun 2, target # encoding: [0x41,0x8b,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bso 2, target
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: bun 0, target # encoding: [0x41,0x83,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bso target
[PowerPC] Support absolute branches There is currently only limited support for the "absolute" variants of branch instructions. This patch adds support for the absolute variants of all branches that are currently otherwise supported. This requires adding new fixup types so that the correct variant of relocation type can be selected by the object writer. While the compiler will continue to usually choose the relative branch variants, this will allow the asm parser to fully support the absolute branches, with either immediate (numerical) or symbolic target addresses. No change in code generation intended. llvm-svn: 184721
2013-06-24 19:03:33 +08:00
# CHECK: buna 2, target # encoding: [0x41,0x8b,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bsoa 2, target
# CHECK: buna 0, target # encoding: [0x41,0x83,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bsoa target
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bunlr 2 # encoding: [0x4d,0x8b,0x00,0x20]
bsolr 2
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: bunlr 0 # encoding: [0x4d,0x83,0x00,0x20]
bsolr
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bunctr 2 # encoding: [0x4d,0x8b,0x04,0x20]
bsoctr 2
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: bunctr 0 # encoding: [0x4d,0x83,0x04,0x20]
bsoctr
[PowerPC] Support b(cond)l in the asm parser This patch adds support for the conditional variants of bl. The pattern is currently used by the asm parser only. llvm-svn: 184719
2013-06-24 19:02:19 +08:00
# CHECK: bunl 2, target # encoding: [0x41,0x8b,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bsol 2, target
# CHECK: bunl 0, target # encoding: [0x41,0x83,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bsol target
[PowerPC] Support absolute branches There is currently only limited support for the "absolute" variants of branch instructions. This patch adds support for the absolute variants of all branches that are currently otherwise supported. This requires adding new fixup types so that the correct variant of relocation type can be selected by the object writer. While the compiler will continue to usually choose the relative branch variants, this will allow the asm parser to fully support the absolute branches, with either immediate (numerical) or symbolic target addresses. No change in code generation intended. llvm-svn: 184721
2013-06-24 19:03:33 +08:00
# CHECK: bunla 2, target # encoding: [0x41,0x8b,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bsola 2, target
# CHECK: bunla 0, target # encoding: [0x41,0x83,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bsola target
[PowerPC] Support blrl and variants in the asm parser This patch adds support for blrl and its conditional variants. The patterns are (currently) used for the asm parser only. llvm-svn: 184718
2013-06-24 19:01:55 +08:00
# CHECK: bunlrl 2 # encoding: [0x4d,0x8b,0x00,0x21]
bsolrl 2
# CHECK: bunlrl 0 # encoding: [0x4d,0x83,0x00,0x21]
bsolrl
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bunctrl 2 # encoding: [0x4d,0x8b,0x04,0x21]
bsoctrl 2
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: bunctrl 0 # encoding: [0x4d,0x83,0x04,0x21]
bsoctrl
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
[PowerPC] Add predicted forms of branches This adds support for the predicted forms of branches (+/-). There are three cases to consider: - Branches using a PPC::Predicate code For these, I've added new PPC::Predicate codes corresponding to the BO values for predicted branch forms, and updated insn printing to print them correctly. I've also added new aliases for the asm parser matching the new forms. - bt/bf I've added new aliases matching to gBC etc. - bd(n)z variants I've added new instruction patterns for the predicted forms. In all cases, the new patterns are used for the asm parser only. (The new infrastructure ought to be sufficient to allow use by the compiler too at some point.) llvm-svn: 184754
2013-06-25 00:52:04 +08:00
# CHECK: bun+ 2, target # encoding: [0x41,0xeb,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bso+ 2, target
# CHECK: bun+ 0, target # encoding: [0x41,0xe3,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bso+ target
# CHECK: buna+ 2, target # encoding: [0x41,0xeb,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bsoa+ 2, target
# CHECK: buna+ 0, target # encoding: [0x41,0xe3,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bsoa+ target
# CHECK: bunlr+ 2 # encoding: [0x4d,0xeb,0x00,0x20]
bsolr+ 2
# CHECK: bunlr+ 0 # encoding: [0x4d,0xe3,0x00,0x20]
bsolr+
# CHECK: bunctr+ 2 # encoding: [0x4d,0xeb,0x04,0x20]
bsoctr+ 2
# CHECK: bunctr+ 0 # encoding: [0x4d,0xe3,0x04,0x20]
bsoctr+
# CHECK: bunl+ 2, target # encoding: [0x41,0xeb,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bsol+ 2, target
# CHECK: bunl+ 0, target # encoding: [0x41,0xe3,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bsol+ target
# CHECK: bunla+ 2, target # encoding: [0x41,0xeb,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bsola+ 2, target
# CHECK: bunla+ 0, target # encoding: [0x41,0xe3,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bsola+ target
# CHECK: bunlrl+ 2 # encoding: [0x4d,0xeb,0x00,0x21]
bsolrl+ 2
# CHECK: bunlrl+ 0 # encoding: [0x4d,0xe3,0x00,0x21]
bsolrl+
# CHECK: bunctrl+ 2 # encoding: [0x4d,0xeb,0x04,0x21]
bsoctrl+ 2
# CHECK: bunctrl+ 0 # encoding: [0x4d,0xe3,0x04,0x21]
bsoctrl+
# CHECK: bun- 2, target # encoding: [0x41,0xcb,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bso- 2, target
# CHECK: bun- 0, target # encoding: [0x41,0xc3,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bso- target
# CHECK: buna- 2, target # encoding: [0x41,0xcb,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bsoa- 2, target
# CHECK: buna- 0, target # encoding: [0x41,0xc3,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bsoa- target
# CHECK: bunlr- 2 # encoding: [0x4d,0xcb,0x00,0x20]
bsolr- 2
# CHECK: bunlr- 0 # encoding: [0x4d,0xc3,0x00,0x20]
bsolr-
# CHECK: bunctr- 2 # encoding: [0x4d,0xcb,0x04,0x20]
bsoctr- 2
# CHECK: bunctr- 0 # encoding: [0x4d,0xc3,0x04,0x20]
bsoctr-
# CHECK: bunl- 2, target # encoding: [0x41,0xcb,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bsol- 2, target
# CHECK: bunl- 0, target # encoding: [0x41,0xc3,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bsol- target
# CHECK: bunla- 2, target # encoding: [0x41,0xcb,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bsola- 2, target
# CHECK: bunla- 0, target # encoding: [0x41,0xc3,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bsola- target
# CHECK: bunlrl- 2 # encoding: [0x4d,0xcb,0x00,0x21]
bsolrl- 2
# CHECK: bunlrl- 0 # encoding: [0x4d,0xc3,0x00,0x21]
bsolrl-
# CHECK: bunctrl- 2 # encoding: [0x4d,0xcb,0x04,0x21]
bsoctrl- 2
# CHECK: bunctrl- 0 # encoding: [0x4d,0xc3,0x04,0x21]
bsoctrl-
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bnu 2, target # encoding: [0x40,0x8b,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bns 2, target
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: bnu 0, target # encoding: [0x40,0x83,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bns target
[PowerPC] Support absolute branches There is currently only limited support for the "absolute" variants of branch instructions. This patch adds support for the absolute variants of all branches that are currently otherwise supported. This requires adding new fixup types so that the correct variant of relocation type can be selected by the object writer. While the compiler will continue to usually choose the relative branch variants, this will allow the asm parser to fully support the absolute branches, with either immediate (numerical) or symbolic target addresses. No change in code generation intended. llvm-svn: 184721
2013-06-24 19:03:33 +08:00
# CHECK: bnua 2, target # encoding: [0x40,0x8b,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnsa 2, target
# CHECK: bnua 0, target # encoding: [0x40,0x83,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnsa target
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bnulr 2 # encoding: [0x4c,0x8b,0x00,0x20]
bnslr 2
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: bnulr 0 # encoding: [0x4c,0x83,0x00,0x20]
bnslr
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bnuctr 2 # encoding: [0x4c,0x8b,0x04,0x20]
bnsctr 2
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: bnuctr 0 # encoding: [0x4c,0x83,0x04,0x20]
bnsctr
[PowerPC] Support b(cond)l in the asm parser This patch adds support for the conditional variants of bl. The pattern is currently used by the asm parser only. llvm-svn: 184719
2013-06-24 19:02:19 +08:00
# CHECK: bnul 2, target # encoding: [0x40,0x8b,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnsl 2, target
# CHECK: bnul 0, target # encoding: [0x40,0x83,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnsl target
[PowerPC] Support absolute branches There is currently only limited support for the "absolute" variants of branch instructions. This patch adds support for the absolute variants of all branches that are currently otherwise supported. This requires adding new fixup types so that the correct variant of relocation type can be selected by the object writer. While the compiler will continue to usually choose the relative branch variants, this will allow the asm parser to fully support the absolute branches, with either immediate (numerical) or symbolic target addresses. No change in code generation intended. llvm-svn: 184721
2013-06-24 19:03:33 +08:00
# CHECK: bnula 2, target # encoding: [0x40,0x8b,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnsla 2, target
# CHECK: bnula 0, target # encoding: [0x40,0x83,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnsla target
[PowerPC] Support blrl and variants in the asm parser This patch adds support for blrl and its conditional variants. The patterns are (currently) used for the asm parser only. llvm-svn: 184718
2013-06-24 19:01:55 +08:00
# CHECK: bnulrl 2 # encoding: [0x4c,0x8b,0x00,0x21]
bnslrl 2
# CHECK: bnulrl 0 # encoding: [0x4c,0x83,0x00,0x21]
bnslrl
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bnuctrl 2 # encoding: [0x4c,0x8b,0x04,0x21]
bnsctrl 2
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: bnuctrl 0 # encoding: [0x4c,0x83,0x04,0x21]
bnsctrl
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
[PowerPC] Add predicted forms of branches This adds support for the predicted forms of branches (+/-). There are three cases to consider: - Branches using a PPC::Predicate code For these, I've added new PPC::Predicate codes corresponding to the BO values for predicted branch forms, and updated insn printing to print them correctly. I've also added new aliases for the asm parser matching the new forms. - bt/bf I've added new aliases matching to gBC etc. - bd(n)z variants I've added new instruction patterns for the predicted forms. In all cases, the new patterns are used for the asm parser only. (The new infrastructure ought to be sufficient to allow use by the compiler too at some point.) llvm-svn: 184754
2013-06-25 00:52:04 +08:00
# CHECK: bnu+ 2, target # encoding: [0x40,0xeb,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bns+ 2, target
# CHECK: bnu+ 0, target # encoding: [0x40,0xe3,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bns+ target
# CHECK: bnua+ 2, target # encoding: [0x40,0xeb,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnsa+ 2, target
# CHECK: bnua+ 0, target # encoding: [0x40,0xe3,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnsa+ target
# CHECK: bnulr+ 2 # encoding: [0x4c,0xeb,0x00,0x20]
bnslr+ 2
# CHECK: bnulr+ 0 # encoding: [0x4c,0xe3,0x00,0x20]
bnslr+
# CHECK: bnuctr+ 2 # encoding: [0x4c,0xeb,0x04,0x20]
bnsctr+ 2
# CHECK: bnuctr+ 0 # encoding: [0x4c,0xe3,0x04,0x20]
bnsctr+
# CHECK: bnul+ 2, target # encoding: [0x40,0xeb,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnsl+ 2, target
# CHECK: bnul+ 0, target # encoding: [0x40,0xe3,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnsl+ target
# CHECK: bnula+ 2, target # encoding: [0x40,0xeb,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnsla+ 2, target
# CHECK: bnula+ 0, target # encoding: [0x40,0xe3,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnsla+ target
# CHECK: bnulrl+ 2 # encoding: [0x4c,0xeb,0x00,0x21]
bnslrl+ 2
# CHECK: bnulrl+ 0 # encoding: [0x4c,0xe3,0x00,0x21]
bnslrl+
# CHECK: bnuctrl+ 2 # encoding: [0x4c,0xeb,0x04,0x21]
bnsctrl+ 2
# CHECK: bnuctrl+ 0 # encoding: [0x4c,0xe3,0x04,0x21]
bnsctrl+
# CHECK: bnu- 2, target # encoding: [0x40,0xcb,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bns- 2, target
# CHECK: bnu- 0, target # encoding: [0x40,0xc3,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bns- target
# CHECK: bnua- 2, target # encoding: [0x40,0xcb,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnsa- 2, target
# CHECK: bnua- 0, target # encoding: [0x40,0xc3,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnsa- target
# CHECK: bnulr- 2 # encoding: [0x4c,0xcb,0x00,0x20]
bnslr- 2
# CHECK: bnulr- 0 # encoding: [0x4c,0xc3,0x00,0x20]
bnslr-
# CHECK: bnuctr- 2 # encoding: [0x4c,0xcb,0x04,0x20]
bnsctr- 2
# CHECK: bnuctr- 0 # encoding: [0x4c,0xc3,0x04,0x20]
bnsctr-
# CHECK: bnul- 2, target # encoding: [0x40,0xcb,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnsl- 2, target
# CHECK: bnul- 0, target # encoding: [0x40,0xc3,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnsl- target
# CHECK: bnula- 2, target # encoding: [0x40,0xcb,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnsla- 2, target
# CHECK: bnula- 0, target # encoding: [0x40,0xc3,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnsla- target
# CHECK: bnulrl- 2 # encoding: [0x4c,0xcb,0x00,0x21]
bnslrl- 2
# CHECK: bnulrl- 0 # encoding: [0x4c,0xc3,0x00,0x21]
bnslrl-
# CHECK: bnuctrl- 2 # encoding: [0x4c,0xcb,0x04,0x21]
bnsctrl- 2
# CHECK: bnuctrl- 0 # encoding: [0x4c,0xc3,0x04,0x21]
bnsctrl-
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bun 2, target # encoding: [0x41,0x8b,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bun 2, target
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: bun 0, target # encoding: [0x41,0x83,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bun target
[PowerPC] Support absolute branches There is currently only limited support for the "absolute" variants of branch instructions. This patch adds support for the absolute variants of all branches that are currently otherwise supported. This requires adding new fixup types so that the correct variant of relocation type can be selected by the object writer. While the compiler will continue to usually choose the relative branch variants, this will allow the asm parser to fully support the absolute branches, with either immediate (numerical) or symbolic target addresses. No change in code generation intended. llvm-svn: 184721
2013-06-24 19:03:33 +08:00
# CHECK: buna 2, target # encoding: [0x41,0x8b,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
buna 2, target
# CHECK: buna 0, target # encoding: [0x41,0x83,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
buna target
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bunlr 2 # encoding: [0x4d,0x8b,0x00,0x20]
bunlr 2
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: bunlr 0 # encoding: [0x4d,0x83,0x00,0x20]
bunlr
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bunctr 2 # encoding: [0x4d,0x8b,0x04,0x20]
bunctr 2
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: bunctr 0 # encoding: [0x4d,0x83,0x04,0x20]
bunctr
[PowerPC] Support b(cond)l in the asm parser This patch adds support for the conditional variants of bl. The pattern is currently used by the asm parser only. llvm-svn: 184719
2013-06-24 19:02:19 +08:00
# CHECK: bunl 2, target # encoding: [0x41,0x8b,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bunl 2, target
# CHECK: bunl 0, target # encoding: [0x41,0x83,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bunl target
[PowerPC] Support absolute branches There is currently only limited support for the "absolute" variants of branch instructions. This patch adds support for the absolute variants of all branches that are currently otherwise supported. This requires adding new fixup types so that the correct variant of relocation type can be selected by the object writer. While the compiler will continue to usually choose the relative branch variants, this will allow the asm parser to fully support the absolute branches, with either immediate (numerical) or symbolic target addresses. No change in code generation intended. llvm-svn: 184721
2013-06-24 19:03:33 +08:00
# CHECK: bunla 2, target # encoding: [0x41,0x8b,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bunla 2, target
# CHECK: bunla 0, target # encoding: [0x41,0x83,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bunla target
[PowerPC] Support blrl and variants in the asm parser This patch adds support for blrl and its conditional variants. The patterns are (currently) used for the asm parser only. llvm-svn: 184718
2013-06-24 19:01:55 +08:00
# CHECK: bunlrl 2 # encoding: [0x4d,0x8b,0x00,0x21]
bunlrl 2
# CHECK: bunlrl 0 # encoding: [0x4d,0x83,0x00,0x21]
bunlrl
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bunctrl 2 # encoding: [0x4d,0x8b,0x04,0x21]
bunctrl 2
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: bunctrl 0 # encoding: [0x4d,0x83,0x04,0x21]
bunctrl
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
[PowerPC] Add predicted forms of branches This adds support for the predicted forms of branches (+/-). There are three cases to consider: - Branches using a PPC::Predicate code For these, I've added new PPC::Predicate codes corresponding to the BO values for predicted branch forms, and updated insn printing to print them correctly. I've also added new aliases for the asm parser matching the new forms. - bt/bf I've added new aliases matching to gBC etc. - bd(n)z variants I've added new instruction patterns for the predicted forms. In all cases, the new patterns are used for the asm parser only. (The new infrastructure ought to be sufficient to allow use by the compiler too at some point.) llvm-svn: 184754
2013-06-25 00:52:04 +08:00
# CHECK: bun+ 2, target # encoding: [0x41,0xeb,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bun+ 2, target
# CHECK: bun+ 0, target # encoding: [0x41,0xe3,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bun+ target
# CHECK: buna+ 2, target # encoding: [0x41,0xeb,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
buna+ 2, target
# CHECK: buna+ 0, target # encoding: [0x41,0xe3,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
buna+ target
# CHECK: bunlr+ 2 # encoding: [0x4d,0xeb,0x00,0x20]
bunlr+ 2
# CHECK: bunlr+ 0 # encoding: [0x4d,0xe3,0x00,0x20]
bunlr+
# CHECK: bunctr+ 2 # encoding: [0x4d,0xeb,0x04,0x20]
bunctr+ 2
# CHECK: bunctr+ 0 # encoding: [0x4d,0xe3,0x04,0x20]
bunctr+
# CHECK: bunl+ 2, target # encoding: [0x41,0xeb,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bunl+ 2, target
# CHECK: bunl+ 0, target # encoding: [0x41,0xe3,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bunl+ target
# CHECK: bunla+ 2, target # encoding: [0x41,0xeb,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bunla+ 2, target
# CHECK: bunla+ 0, target # encoding: [0x41,0xe3,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bunla+ target
# CHECK: bunlrl+ 2 # encoding: [0x4d,0xeb,0x00,0x21]
bunlrl+ 2
# CHECK: bunlrl+ 0 # encoding: [0x4d,0xe3,0x00,0x21]
bunlrl+
# CHECK: bunctrl+ 2 # encoding: [0x4d,0xeb,0x04,0x21]
bunctrl+ 2
# CHECK: bunctrl+ 0 # encoding: [0x4d,0xe3,0x04,0x21]
bunctrl+
# CHECK: bun- 2, target # encoding: [0x41,0xcb,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bun- 2, target
# CHECK: bun- 0, target # encoding: [0x41,0xc3,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bun- target
# CHECK: buna- 2, target # encoding: [0x41,0xcb,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
buna- 2, target
# CHECK: buna- 0, target # encoding: [0x41,0xc3,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
buna- target
# CHECK: bunlr- 2 # encoding: [0x4d,0xcb,0x00,0x20]
bunlr- 2
# CHECK: bunlr- 0 # encoding: [0x4d,0xc3,0x00,0x20]
bunlr-
# CHECK: bunctr- 2 # encoding: [0x4d,0xcb,0x04,0x20]
bunctr- 2
# CHECK: bunctr- 0 # encoding: [0x4d,0xc3,0x04,0x20]
bunctr-
# CHECK: bunl- 2, target # encoding: [0x41,0xcb,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bunl- 2, target
# CHECK: bunl- 0, target # encoding: [0x41,0xc3,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bunl- target
# CHECK: bunla- 2, target # encoding: [0x41,0xcb,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bunla- 2, target
# CHECK: bunla- 0, target # encoding: [0x41,0xc3,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bunla- target
# CHECK: bunlrl- 2 # encoding: [0x4d,0xcb,0x00,0x21]
bunlrl- 2
# CHECK: bunlrl- 0 # encoding: [0x4d,0xc3,0x00,0x21]
bunlrl-
# CHECK: bunctrl- 2 # encoding: [0x4d,0xcb,0x04,0x21]
bunctrl- 2
# CHECK: bunctrl- 0 # encoding: [0x4d,0xc3,0x04,0x21]
bunctrl-
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bnu 2, target # encoding: [0x40,0x8b,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnu 2, target
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: bnu 0, target # encoding: [0x40,0x83,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnu target
[PowerPC] Support absolute branches There is currently only limited support for the "absolute" variants of branch instructions. This patch adds support for the absolute variants of all branches that are currently otherwise supported. This requires adding new fixup types so that the correct variant of relocation type can be selected by the object writer. While the compiler will continue to usually choose the relative branch variants, this will allow the asm parser to fully support the absolute branches, with either immediate (numerical) or symbolic target addresses. No change in code generation intended. llvm-svn: 184721
2013-06-24 19:03:33 +08:00
# CHECK: bnua 2, target # encoding: [0x40,0x8b,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnua 2, target
# CHECK: bnua 0, target # encoding: [0x40,0x83,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnua target
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bnulr 2 # encoding: [0x4c,0x8b,0x00,0x20]
bnulr 2
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: bnulr 0 # encoding: [0x4c,0x83,0x00,0x20]
bnulr
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bnuctr 2 # encoding: [0x4c,0x8b,0x04,0x20]
bnuctr 2
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: bnuctr 0 # encoding: [0x4c,0x83,0x04,0x20]
bnuctr
[PowerPC] Support b(cond)l in the asm parser This patch adds support for the conditional variants of bl. The pattern is currently used by the asm parser only. llvm-svn: 184719
2013-06-24 19:02:19 +08:00
# CHECK: bnul 2, target # encoding: [0x40,0x8b,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnul 2, target
# CHECK: bnul 0, target # encoding: [0x40,0x83,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnul target
[PowerPC] Support absolute branches There is currently only limited support for the "absolute" variants of branch instructions. This patch adds support for the absolute variants of all branches that are currently otherwise supported. This requires adding new fixup types so that the correct variant of relocation type can be selected by the object writer. While the compiler will continue to usually choose the relative branch variants, this will allow the asm parser to fully support the absolute branches, with either immediate (numerical) or symbolic target addresses. No change in code generation intended. llvm-svn: 184721
2013-06-24 19:03:33 +08:00
# CHECK: bnula 2, target # encoding: [0x40,0x8b,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnula 2, target
# CHECK: bnula 0, target # encoding: [0x40,0x83,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnula target
[PowerPC] Support blrl and variants in the asm parser This patch adds support for blrl and its conditional variants. The patterns are (currently) used for the asm parser only. llvm-svn: 184718
2013-06-24 19:01:55 +08:00
# CHECK: bnulrl 2 # encoding: [0x4c,0x8b,0x00,0x21]
bnulrl 2
# CHECK: bnulrl 0 # encoding: [0x4c,0x83,0x00,0x21]
bnulrl
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: bnuctrl 2 # encoding: [0x4c,0x8b,0x04,0x21]
bnuctrl 2
[PowerPC] Support branch mnemonics with implied CR0 The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
2013-06-11 01:19:15 +08:00
# CHECK: bnuctrl 0 # encoding: [0x4c,0x83,0x04,0x21]
bnuctrl
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
[PowerPC] Add predicted forms of branches This adds support for the predicted forms of branches (+/-). There are three cases to consider: - Branches using a PPC::Predicate code For these, I've added new PPC::Predicate codes corresponding to the BO values for predicted branch forms, and updated insn printing to print them correctly. I've also added new aliases for the asm parser matching the new forms. - bt/bf I've added new aliases matching to gBC etc. - bd(n)z variants I've added new instruction patterns for the predicted forms. In all cases, the new patterns are used for the asm parser only. (The new infrastructure ought to be sufficient to allow use by the compiler too at some point.) llvm-svn: 184754
2013-06-25 00:52:04 +08:00
# CHECK: bnu+ 2, target # encoding: [0x40,0xeb,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnu+ 2, target
# CHECK: bnu+ 0, target # encoding: [0x40,0xe3,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnu+ target
# CHECK: bnua+ 2, target # encoding: [0x40,0xeb,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnua+ 2, target
# CHECK: bnua+ 0, target # encoding: [0x40,0xe3,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnua+ target
# CHECK: bnulr+ 2 # encoding: [0x4c,0xeb,0x00,0x20]
bnulr+ 2
# CHECK: bnulr+ 0 # encoding: [0x4c,0xe3,0x00,0x20]
bnulr+
# CHECK: bnuctr+ 2 # encoding: [0x4c,0xeb,0x04,0x20]
bnuctr+ 2
# CHECK: bnuctr+ 0 # encoding: [0x4c,0xe3,0x04,0x20]
bnuctr+
# CHECK: bnul+ 2, target # encoding: [0x40,0xeb,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnul+ 2, target
# CHECK: bnul+ 0, target # encoding: [0x40,0xe3,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnul+ target
# CHECK: bnula+ 2, target # encoding: [0x40,0xeb,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnula+ 2, target
# CHECK: bnula+ 0, target # encoding: [0x40,0xe3,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnula+ target
# CHECK: bnulrl+ 2 # encoding: [0x4c,0xeb,0x00,0x21]
bnulrl+ 2
# CHECK: bnulrl+ 0 # encoding: [0x4c,0xe3,0x00,0x21]
bnulrl+
# CHECK: bnuctrl+ 2 # encoding: [0x4c,0xeb,0x04,0x21]
bnuctrl+ 2
# CHECK: bnuctrl+ 0 # encoding: [0x4c,0xe3,0x04,0x21]
bnuctrl+
# CHECK: bnu- 2, target # encoding: [0x40,0xcb,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnu- 2, target
# CHECK: bnu- 0, target # encoding: [0x40,0xc3,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnu- target
# CHECK: bnua- 2, target # encoding: [0x40,0xcb,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnua- 2, target
# CHECK: bnua- 0, target # encoding: [0x40,0xc3,A,0bAAAAAA10]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnua- target
# CHECK: bnulr- 2 # encoding: [0x4c,0xcb,0x00,0x20]
bnulr- 2
# CHECK: bnulr- 0 # encoding: [0x4c,0xc3,0x00,0x20]
bnulr-
# CHECK: bnuctr- 2 # encoding: [0x4c,0xcb,0x04,0x20]
bnuctr- 2
# CHECK: bnuctr- 0 # encoding: [0x4c,0xc3,0x04,0x20]
bnuctr-
# CHECK: bnul- 2, target # encoding: [0x40,0xcb,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnul- 2, target
# CHECK: bnul- 0, target # encoding: [0x40,0xc3,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bnul- target
# CHECK: bnula- 2, target # encoding: [0x40,0xcb,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnula- 2, target
# CHECK: bnula- 0, target # encoding: [0x40,0xc3,A,0bAAAAAA11]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
bnula- target
# CHECK: bnulrl- 2 # encoding: [0x4c,0xcb,0x00,0x21]
bnulrl- 2
# CHECK: bnulrl- 0 # encoding: [0x4c,0xc3,0x00,0x21]
bnulrl-
# CHECK: bnuctrl- 2 # encoding: [0x4c,0xcb,0x04,0x21]
bnuctrl- 2
# CHECK: bnuctrl- 0 # encoding: [0x4c,0xc3,0x04,0x21]
bnuctrl-
[PowerPC] Support all condition register logical instructions This adds support for all missing condition register logical instructions and extended mnemonics to the asm parser. llvm-svn: 185387
2013-07-02 05:40:54 +08:00
# Condition register logical mnemonics
# CHECK: creqv 2, 2, 2 # encoding: [0x4c,0x42,0x12,0x42]
crset 2
# CHECK: crxor 2, 2, 2 # encoding: [0x4c,0x42,0x11,0x82]
crclr 2
# CHECK: cror 2, 3, 3 # encoding: [0x4c,0x43,0x1b,0x82]
crmove 2, 3
# CHECK: crnor 2, 3, 3 # encoding: [0x4c,0x43,0x18,0x42]
crnot 2, 3
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
[PowerPC] Add extended subtract mnemonics This adds support for the extended subtract mnemonics to the asm parser: subi subis subic subic. sub sub. subc subc. llvm-svn: 184832
2013-06-25 21:16:48 +08:00
# Subtract mnemonics
# CHECK: addi 2, 3, -128 # encoding: [0x38,0x43,0xff,0x80]
subi 2, 3, 128
# CHECK: addis 2, 3, -128 # encoding: [0x3c,0x43,0xff,0x80]
subis 2, 3, 128
# CHECK: addic 2, 3, -128 # encoding: [0x30,0x43,0xff,0x80]
subic 2, 3, 128
# CHECK: addic. 2, 3, -128 # encoding: [0x34,0x43,0xff,0x80]
subic. 2, 3, 128
# CHECK: subf 2, 4, 3 # encoding: [0x7c,0x44,0x18,0x50]
sub 2, 3, 4
# CHECK: subf. 2, 4, 3 # encoding: [0x7c,0x44,0x18,0x51]
sub. 2, 3, 4
# CHECK: subfc 2, 4, 3 # encoding: [0x7c,0x44,0x18,0x10]
subc 2, 3, 4
# CHECK: subfc. 2, 4, 3 # encoding: [0x7c,0x44,0x18,0x11]
subc. 2, 3, 4
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# Compare mnemonics
# CHECK: cmpdi 2, 3, 128 # encoding: [0x2d,0x23,0x00,0x80]
cmpdi 2, 3, 128
[PowerPC] Support compare mnemonics with implied CR0 Just like for branch mnemonics (where support was recently added), the assembler is supposed to support extended mnemonics for the compare instructions where no condition register is specified explicitly (and CR0 is assumed implicitly). This patch adds support for those extended compare mnemonics. Index: llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s =================================================================== --- llvm-head.orig/test/MC/PowerPC/ppc64-encoding-ext.s +++ llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s @@ -449,21 +449,37 @@ # CHECK: cmpdi 2, 3, 128 # encoding: [0x2d,0x23,0x00,0x80] cmpdi 2, 3, 128 +# CHECK: cmpdi 0, 3, 128 # encoding: [0x2c,0x23,0x00,0x80] + cmpdi 3, 128 # CHECK: cmpd 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x00] cmpd 2, 3, 4 +# CHECK: cmpd 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x00] + cmpd 3, 4 # CHECK: cmpldi 2, 3, 128 # encoding: [0x29,0x23,0x00,0x80] cmpldi 2, 3, 128 +# CHECK: cmpldi 0, 3, 128 # encoding: [0x28,0x23,0x00,0x80] + cmpldi 3, 128 # CHECK: cmpld 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x40] cmpld 2, 3, 4 +# CHECK: cmpld 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x40] + cmpld 3, 4 # CHECK: cmpwi 2, 3, 128 # encoding: [0x2d,0x03,0x00,0x80] cmpwi 2, 3, 128 +# CHECK: cmpwi 0, 3, 128 # encoding: [0x2c,0x03,0x00,0x80] + cmpwi 3, 128 # CHECK: cmpw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x00] cmpw 2, 3, 4 +# CHECK: cmpw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x00] + cmpw 3, 4 # CHECK: cmplwi 2, 3, 128 # encoding: [0x29,0x03,0x00,0x80] cmplwi 2, 3, 128 +# CHECK: cmplwi 0, 3, 128 # encoding: [0x28,0x03,0x00,0x80] + cmplwi 3, 128 # CHECK: cmplw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x40] cmplw 2, 3, 4 +# CHECK: cmplw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x40] + cmplw 3, 4 # FIXME: Trap mnemonics Index: llvm-head/lib/Target/PowerPC/PPCInstrInfo.td =================================================================== --- llvm-head.orig/lib/Target/PowerPC/PPCInstrInfo.td +++ llvm-head/lib/Target/PowerPC/PPCInstrInfo.td @@ -2201,3 +2201,12 @@ defm : BranchExtendedMnemonic<"ne", 68>; defm : BranchExtendedMnemonic<"nu", 100>; defm : BranchExtendedMnemonic<"ns", 100>; +def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>; +def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>; +def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>; +def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>; +def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>; +def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>; +def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>; +def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>; + llvm-svn: 184435
2013-06-21 00:15:12 +08:00
# CHECK: cmpdi 0, 3, 128 # encoding: [0x2c,0x23,0x00,0x80]
cmpdi 3, 128
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: cmpd 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x00]
cmpd 2, 3, 4
[PowerPC] Support compare mnemonics with implied CR0 Just like for branch mnemonics (where support was recently added), the assembler is supposed to support extended mnemonics for the compare instructions where no condition register is specified explicitly (and CR0 is assumed implicitly). This patch adds support for those extended compare mnemonics. Index: llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s =================================================================== --- llvm-head.orig/test/MC/PowerPC/ppc64-encoding-ext.s +++ llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s @@ -449,21 +449,37 @@ # CHECK: cmpdi 2, 3, 128 # encoding: [0x2d,0x23,0x00,0x80] cmpdi 2, 3, 128 +# CHECK: cmpdi 0, 3, 128 # encoding: [0x2c,0x23,0x00,0x80] + cmpdi 3, 128 # CHECK: cmpd 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x00] cmpd 2, 3, 4 +# CHECK: cmpd 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x00] + cmpd 3, 4 # CHECK: cmpldi 2, 3, 128 # encoding: [0x29,0x23,0x00,0x80] cmpldi 2, 3, 128 +# CHECK: cmpldi 0, 3, 128 # encoding: [0x28,0x23,0x00,0x80] + cmpldi 3, 128 # CHECK: cmpld 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x40] cmpld 2, 3, 4 +# CHECK: cmpld 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x40] + cmpld 3, 4 # CHECK: cmpwi 2, 3, 128 # encoding: [0x2d,0x03,0x00,0x80] cmpwi 2, 3, 128 +# CHECK: cmpwi 0, 3, 128 # encoding: [0x2c,0x03,0x00,0x80] + cmpwi 3, 128 # CHECK: cmpw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x00] cmpw 2, 3, 4 +# CHECK: cmpw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x00] + cmpw 3, 4 # CHECK: cmplwi 2, 3, 128 # encoding: [0x29,0x03,0x00,0x80] cmplwi 2, 3, 128 +# CHECK: cmplwi 0, 3, 128 # encoding: [0x28,0x03,0x00,0x80] + cmplwi 3, 128 # CHECK: cmplw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x40] cmplw 2, 3, 4 +# CHECK: cmplw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x40] + cmplw 3, 4 # FIXME: Trap mnemonics Index: llvm-head/lib/Target/PowerPC/PPCInstrInfo.td =================================================================== --- llvm-head.orig/lib/Target/PowerPC/PPCInstrInfo.td +++ llvm-head/lib/Target/PowerPC/PPCInstrInfo.td @@ -2201,3 +2201,12 @@ defm : BranchExtendedMnemonic<"ne", 68>; defm : BranchExtendedMnemonic<"nu", 100>; defm : BranchExtendedMnemonic<"ns", 100>; +def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>; +def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>; +def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>; +def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>; +def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>; +def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>; +def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>; +def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>; + llvm-svn: 184435
2013-06-21 00:15:12 +08:00
# CHECK: cmpd 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x00]
cmpd 3, 4
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: cmpldi 2, 3, 128 # encoding: [0x29,0x23,0x00,0x80]
cmpldi 2, 3, 128
[PowerPC] Support compare mnemonics with implied CR0 Just like for branch mnemonics (where support was recently added), the assembler is supposed to support extended mnemonics for the compare instructions where no condition register is specified explicitly (and CR0 is assumed implicitly). This patch adds support for those extended compare mnemonics. Index: llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s =================================================================== --- llvm-head.orig/test/MC/PowerPC/ppc64-encoding-ext.s +++ llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s @@ -449,21 +449,37 @@ # CHECK: cmpdi 2, 3, 128 # encoding: [0x2d,0x23,0x00,0x80] cmpdi 2, 3, 128 +# CHECK: cmpdi 0, 3, 128 # encoding: [0x2c,0x23,0x00,0x80] + cmpdi 3, 128 # CHECK: cmpd 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x00] cmpd 2, 3, 4 +# CHECK: cmpd 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x00] + cmpd 3, 4 # CHECK: cmpldi 2, 3, 128 # encoding: [0x29,0x23,0x00,0x80] cmpldi 2, 3, 128 +# CHECK: cmpldi 0, 3, 128 # encoding: [0x28,0x23,0x00,0x80] + cmpldi 3, 128 # CHECK: cmpld 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x40] cmpld 2, 3, 4 +# CHECK: cmpld 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x40] + cmpld 3, 4 # CHECK: cmpwi 2, 3, 128 # encoding: [0x2d,0x03,0x00,0x80] cmpwi 2, 3, 128 +# CHECK: cmpwi 0, 3, 128 # encoding: [0x2c,0x03,0x00,0x80] + cmpwi 3, 128 # CHECK: cmpw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x00] cmpw 2, 3, 4 +# CHECK: cmpw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x00] + cmpw 3, 4 # CHECK: cmplwi 2, 3, 128 # encoding: [0x29,0x03,0x00,0x80] cmplwi 2, 3, 128 +# CHECK: cmplwi 0, 3, 128 # encoding: [0x28,0x03,0x00,0x80] + cmplwi 3, 128 # CHECK: cmplw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x40] cmplw 2, 3, 4 +# CHECK: cmplw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x40] + cmplw 3, 4 # FIXME: Trap mnemonics Index: llvm-head/lib/Target/PowerPC/PPCInstrInfo.td =================================================================== --- llvm-head.orig/lib/Target/PowerPC/PPCInstrInfo.td +++ llvm-head/lib/Target/PowerPC/PPCInstrInfo.td @@ -2201,3 +2201,12 @@ defm : BranchExtendedMnemonic<"ne", 68>; defm : BranchExtendedMnemonic<"nu", 100>; defm : BranchExtendedMnemonic<"ns", 100>; +def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>; +def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>; +def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>; +def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>; +def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>; +def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>; +def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>; +def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>; + llvm-svn: 184435
2013-06-21 00:15:12 +08:00
# CHECK: cmpldi 0, 3, 128 # encoding: [0x28,0x23,0x00,0x80]
cmpldi 3, 128
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: cmpld 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x40]
cmpld 2, 3, 4
[PowerPC] Support compare mnemonics with implied CR0 Just like for branch mnemonics (where support was recently added), the assembler is supposed to support extended mnemonics for the compare instructions where no condition register is specified explicitly (and CR0 is assumed implicitly). This patch adds support for those extended compare mnemonics. Index: llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s =================================================================== --- llvm-head.orig/test/MC/PowerPC/ppc64-encoding-ext.s +++ llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s @@ -449,21 +449,37 @@ # CHECK: cmpdi 2, 3, 128 # encoding: [0x2d,0x23,0x00,0x80] cmpdi 2, 3, 128 +# CHECK: cmpdi 0, 3, 128 # encoding: [0x2c,0x23,0x00,0x80] + cmpdi 3, 128 # CHECK: cmpd 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x00] cmpd 2, 3, 4 +# CHECK: cmpd 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x00] + cmpd 3, 4 # CHECK: cmpldi 2, 3, 128 # encoding: [0x29,0x23,0x00,0x80] cmpldi 2, 3, 128 +# CHECK: cmpldi 0, 3, 128 # encoding: [0x28,0x23,0x00,0x80] + cmpldi 3, 128 # CHECK: cmpld 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x40] cmpld 2, 3, 4 +# CHECK: cmpld 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x40] + cmpld 3, 4 # CHECK: cmpwi 2, 3, 128 # encoding: [0x2d,0x03,0x00,0x80] cmpwi 2, 3, 128 +# CHECK: cmpwi 0, 3, 128 # encoding: [0x2c,0x03,0x00,0x80] + cmpwi 3, 128 # CHECK: cmpw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x00] cmpw 2, 3, 4 +# CHECK: cmpw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x00] + cmpw 3, 4 # CHECK: cmplwi 2, 3, 128 # encoding: [0x29,0x03,0x00,0x80] cmplwi 2, 3, 128 +# CHECK: cmplwi 0, 3, 128 # encoding: [0x28,0x03,0x00,0x80] + cmplwi 3, 128 # CHECK: cmplw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x40] cmplw 2, 3, 4 +# CHECK: cmplw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x40] + cmplw 3, 4 # FIXME: Trap mnemonics Index: llvm-head/lib/Target/PowerPC/PPCInstrInfo.td =================================================================== --- llvm-head.orig/lib/Target/PowerPC/PPCInstrInfo.td +++ llvm-head/lib/Target/PowerPC/PPCInstrInfo.td @@ -2201,3 +2201,12 @@ defm : BranchExtendedMnemonic<"ne", 68>; defm : BranchExtendedMnemonic<"nu", 100>; defm : BranchExtendedMnemonic<"ns", 100>; +def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>; +def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>; +def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>; +def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>; +def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>; +def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>; +def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>; +def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>; + llvm-svn: 184435
2013-06-21 00:15:12 +08:00
# CHECK: cmpld 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x40]
cmpld 3, 4
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: cmpwi 2, 3, 128 # encoding: [0x2d,0x03,0x00,0x80]
cmpwi 2, 3, 128
[PowerPC] Support compare mnemonics with implied CR0 Just like for branch mnemonics (where support was recently added), the assembler is supposed to support extended mnemonics for the compare instructions where no condition register is specified explicitly (and CR0 is assumed implicitly). This patch adds support for those extended compare mnemonics. Index: llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s =================================================================== --- llvm-head.orig/test/MC/PowerPC/ppc64-encoding-ext.s +++ llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s @@ -449,21 +449,37 @@ # CHECK: cmpdi 2, 3, 128 # encoding: [0x2d,0x23,0x00,0x80] cmpdi 2, 3, 128 +# CHECK: cmpdi 0, 3, 128 # encoding: [0x2c,0x23,0x00,0x80] + cmpdi 3, 128 # CHECK: cmpd 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x00] cmpd 2, 3, 4 +# CHECK: cmpd 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x00] + cmpd 3, 4 # CHECK: cmpldi 2, 3, 128 # encoding: [0x29,0x23,0x00,0x80] cmpldi 2, 3, 128 +# CHECK: cmpldi 0, 3, 128 # encoding: [0x28,0x23,0x00,0x80] + cmpldi 3, 128 # CHECK: cmpld 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x40] cmpld 2, 3, 4 +# CHECK: cmpld 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x40] + cmpld 3, 4 # CHECK: cmpwi 2, 3, 128 # encoding: [0x2d,0x03,0x00,0x80] cmpwi 2, 3, 128 +# CHECK: cmpwi 0, 3, 128 # encoding: [0x2c,0x03,0x00,0x80] + cmpwi 3, 128 # CHECK: cmpw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x00] cmpw 2, 3, 4 +# CHECK: cmpw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x00] + cmpw 3, 4 # CHECK: cmplwi 2, 3, 128 # encoding: [0x29,0x03,0x00,0x80] cmplwi 2, 3, 128 +# CHECK: cmplwi 0, 3, 128 # encoding: [0x28,0x03,0x00,0x80] + cmplwi 3, 128 # CHECK: cmplw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x40] cmplw 2, 3, 4 +# CHECK: cmplw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x40] + cmplw 3, 4 # FIXME: Trap mnemonics Index: llvm-head/lib/Target/PowerPC/PPCInstrInfo.td =================================================================== --- llvm-head.orig/lib/Target/PowerPC/PPCInstrInfo.td +++ llvm-head/lib/Target/PowerPC/PPCInstrInfo.td @@ -2201,3 +2201,12 @@ defm : BranchExtendedMnemonic<"ne", 68>; defm : BranchExtendedMnemonic<"nu", 100>; defm : BranchExtendedMnemonic<"ns", 100>; +def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>; +def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>; +def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>; +def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>; +def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>; +def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>; +def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>; +def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>; + llvm-svn: 184435
2013-06-21 00:15:12 +08:00
# CHECK: cmpwi 0, 3, 128 # encoding: [0x2c,0x03,0x00,0x80]
cmpwi 3, 128
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: cmpw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x00]
cmpw 2, 3, 4
[PowerPC] Support compare mnemonics with implied CR0 Just like for branch mnemonics (where support was recently added), the assembler is supposed to support extended mnemonics for the compare instructions where no condition register is specified explicitly (and CR0 is assumed implicitly). This patch adds support for those extended compare mnemonics. Index: llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s =================================================================== --- llvm-head.orig/test/MC/PowerPC/ppc64-encoding-ext.s +++ llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s @@ -449,21 +449,37 @@ # CHECK: cmpdi 2, 3, 128 # encoding: [0x2d,0x23,0x00,0x80] cmpdi 2, 3, 128 +# CHECK: cmpdi 0, 3, 128 # encoding: [0x2c,0x23,0x00,0x80] + cmpdi 3, 128 # CHECK: cmpd 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x00] cmpd 2, 3, 4 +# CHECK: cmpd 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x00] + cmpd 3, 4 # CHECK: cmpldi 2, 3, 128 # encoding: [0x29,0x23,0x00,0x80] cmpldi 2, 3, 128 +# CHECK: cmpldi 0, 3, 128 # encoding: [0x28,0x23,0x00,0x80] + cmpldi 3, 128 # CHECK: cmpld 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x40] cmpld 2, 3, 4 +# CHECK: cmpld 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x40] + cmpld 3, 4 # CHECK: cmpwi 2, 3, 128 # encoding: [0x2d,0x03,0x00,0x80] cmpwi 2, 3, 128 +# CHECK: cmpwi 0, 3, 128 # encoding: [0x2c,0x03,0x00,0x80] + cmpwi 3, 128 # CHECK: cmpw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x00] cmpw 2, 3, 4 +# CHECK: cmpw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x00] + cmpw 3, 4 # CHECK: cmplwi 2, 3, 128 # encoding: [0x29,0x03,0x00,0x80] cmplwi 2, 3, 128 +# CHECK: cmplwi 0, 3, 128 # encoding: [0x28,0x03,0x00,0x80] + cmplwi 3, 128 # CHECK: cmplw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x40] cmplw 2, 3, 4 +# CHECK: cmplw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x40] + cmplw 3, 4 # FIXME: Trap mnemonics Index: llvm-head/lib/Target/PowerPC/PPCInstrInfo.td =================================================================== --- llvm-head.orig/lib/Target/PowerPC/PPCInstrInfo.td +++ llvm-head/lib/Target/PowerPC/PPCInstrInfo.td @@ -2201,3 +2201,12 @@ defm : BranchExtendedMnemonic<"ne", 68>; defm : BranchExtendedMnemonic<"nu", 100>; defm : BranchExtendedMnemonic<"ns", 100>; +def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>; +def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>; +def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>; +def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>; +def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>; +def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>; +def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>; +def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>; + llvm-svn: 184435
2013-06-21 00:15:12 +08:00
# CHECK: cmpw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x00]
cmpw 3, 4
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: cmplwi 2, 3, 128 # encoding: [0x29,0x03,0x00,0x80]
cmplwi 2, 3, 128
[PowerPC] Support compare mnemonics with implied CR0 Just like for branch mnemonics (where support was recently added), the assembler is supposed to support extended mnemonics for the compare instructions where no condition register is specified explicitly (and CR0 is assumed implicitly). This patch adds support for those extended compare mnemonics. Index: llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s =================================================================== --- llvm-head.orig/test/MC/PowerPC/ppc64-encoding-ext.s +++ llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s @@ -449,21 +449,37 @@ # CHECK: cmpdi 2, 3, 128 # encoding: [0x2d,0x23,0x00,0x80] cmpdi 2, 3, 128 +# CHECK: cmpdi 0, 3, 128 # encoding: [0x2c,0x23,0x00,0x80] + cmpdi 3, 128 # CHECK: cmpd 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x00] cmpd 2, 3, 4 +# CHECK: cmpd 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x00] + cmpd 3, 4 # CHECK: cmpldi 2, 3, 128 # encoding: [0x29,0x23,0x00,0x80] cmpldi 2, 3, 128 +# CHECK: cmpldi 0, 3, 128 # encoding: [0x28,0x23,0x00,0x80] + cmpldi 3, 128 # CHECK: cmpld 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x40] cmpld 2, 3, 4 +# CHECK: cmpld 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x40] + cmpld 3, 4 # CHECK: cmpwi 2, 3, 128 # encoding: [0x2d,0x03,0x00,0x80] cmpwi 2, 3, 128 +# CHECK: cmpwi 0, 3, 128 # encoding: [0x2c,0x03,0x00,0x80] + cmpwi 3, 128 # CHECK: cmpw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x00] cmpw 2, 3, 4 +# CHECK: cmpw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x00] + cmpw 3, 4 # CHECK: cmplwi 2, 3, 128 # encoding: [0x29,0x03,0x00,0x80] cmplwi 2, 3, 128 +# CHECK: cmplwi 0, 3, 128 # encoding: [0x28,0x03,0x00,0x80] + cmplwi 3, 128 # CHECK: cmplw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x40] cmplw 2, 3, 4 +# CHECK: cmplw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x40] + cmplw 3, 4 # FIXME: Trap mnemonics Index: llvm-head/lib/Target/PowerPC/PPCInstrInfo.td =================================================================== --- llvm-head.orig/lib/Target/PowerPC/PPCInstrInfo.td +++ llvm-head/lib/Target/PowerPC/PPCInstrInfo.td @@ -2201,3 +2201,12 @@ defm : BranchExtendedMnemonic<"ne", 68>; defm : BranchExtendedMnemonic<"nu", 100>; defm : BranchExtendedMnemonic<"ns", 100>; +def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>; +def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>; +def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>; +def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>; +def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>; +def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>; +def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>; +def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>; + llvm-svn: 184435
2013-06-21 00:15:12 +08:00
# CHECK: cmplwi 0, 3, 128 # encoding: [0x28,0x03,0x00,0x80]
cmplwi 3, 128
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: cmplw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x40]
cmplw 2, 3, 4
[PowerPC] Support compare mnemonics with implied CR0 Just like for branch mnemonics (where support was recently added), the assembler is supposed to support extended mnemonics for the compare instructions where no condition register is specified explicitly (and CR0 is assumed implicitly). This patch adds support for those extended compare mnemonics. Index: llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s =================================================================== --- llvm-head.orig/test/MC/PowerPC/ppc64-encoding-ext.s +++ llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s @@ -449,21 +449,37 @@ # CHECK: cmpdi 2, 3, 128 # encoding: [0x2d,0x23,0x00,0x80] cmpdi 2, 3, 128 +# CHECK: cmpdi 0, 3, 128 # encoding: [0x2c,0x23,0x00,0x80] + cmpdi 3, 128 # CHECK: cmpd 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x00] cmpd 2, 3, 4 +# CHECK: cmpd 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x00] + cmpd 3, 4 # CHECK: cmpldi 2, 3, 128 # encoding: [0x29,0x23,0x00,0x80] cmpldi 2, 3, 128 +# CHECK: cmpldi 0, 3, 128 # encoding: [0x28,0x23,0x00,0x80] + cmpldi 3, 128 # CHECK: cmpld 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x40] cmpld 2, 3, 4 +# CHECK: cmpld 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x40] + cmpld 3, 4 # CHECK: cmpwi 2, 3, 128 # encoding: [0x2d,0x03,0x00,0x80] cmpwi 2, 3, 128 +# CHECK: cmpwi 0, 3, 128 # encoding: [0x2c,0x03,0x00,0x80] + cmpwi 3, 128 # CHECK: cmpw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x00] cmpw 2, 3, 4 +# CHECK: cmpw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x00] + cmpw 3, 4 # CHECK: cmplwi 2, 3, 128 # encoding: [0x29,0x03,0x00,0x80] cmplwi 2, 3, 128 +# CHECK: cmplwi 0, 3, 128 # encoding: [0x28,0x03,0x00,0x80] + cmplwi 3, 128 # CHECK: cmplw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x40] cmplw 2, 3, 4 +# CHECK: cmplw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x40] + cmplw 3, 4 # FIXME: Trap mnemonics Index: llvm-head/lib/Target/PowerPC/PPCInstrInfo.td =================================================================== --- llvm-head.orig/lib/Target/PowerPC/PPCInstrInfo.td +++ llvm-head/lib/Target/PowerPC/PPCInstrInfo.td @@ -2201,3 +2201,12 @@ defm : BranchExtendedMnemonic<"ne", 68>; defm : BranchExtendedMnemonic<"nu", 100>; defm : BranchExtendedMnemonic<"ns", 100>; +def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>; +def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>; +def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>; +def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>; +def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>; +def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>; +def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>; +def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>; + llvm-svn: 184435
2013-06-21 00:15:12 +08:00
# CHECK: cmplw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x40]
cmplw 3, 4
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# FIXME: Trap mnemonics
# Rotate and shift mnemonics
[PowerPC] Add extended rotate/shift mnemonics This adds all missing extended rotate/shift mnemonics to the asm parser. llvm-svn: 184834
2013-06-25 21:17:41 +08:00
# CHECK: rldicr 2, 3, 5, 3 # encoding: [0x78,0x62,0x28,0xc4]
extldi 2, 3, 4, 5
# CHECK: rldicr. 2, 3, 5, 3 # encoding: [0x78,0x62,0x28,0xc5]
extldi. 2, 3, 4, 5
# CHECK: rldicl 2, 3, 9, 60 # encoding: [0x78,0x62,0x4f,0x20]
extrdi 2, 3, 4, 5
# CHECK: rldicl. 2, 3, 9, 60 # encoding: [0x78,0x62,0x4f,0x21]
extrdi. 2, 3, 4, 5
# CHECK: rldimi 2, 3, 55, 5 # encoding: [0x78,0x62,0xb9,0x4e]
insrdi 2, 3, 4, 5
# CHECK: rldimi. 2, 3, 55, 5 # encoding: [0x78,0x62,0xb9,0x4f]
insrdi. 2, 3, 4, 5
# CHECK: rldicl 2, 3, 4, 0 # encoding: [0x78,0x62,0x20,0x00]
rotldi 2, 3, 4
# CHECK: rldicl. 2, 3, 4, 0 # encoding: [0x78,0x62,0x20,0x01]
rotldi. 2, 3, 4
# CHECK: rldicl 2, 3, 60, 0 # encoding: [0x78,0x62,0xe0,0x02]
rotrdi 2, 3, 4
# CHECK: rldicl. 2, 3, 60, 0 # encoding: [0x78,0x62,0xe0,0x03]
rotrdi. 2, 3, 4
# CHECK: rldcl 2, 3, 4, 0 # encoding: [0x78,0x62,0x20,0x10]
rotld 2, 3, 4
# CHECK: rldcl. 2, 3, 4, 0 # encoding: [0x78,0x62,0x20,0x11]
rotld. 2, 3, 4
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: sldi 2, 3, 4 # encoding: [0x78,0x62,0x26,0xe4]
sldi 2, 3, 4
[PowerPC] Add extended rotate/shift mnemonics This adds all missing extended rotate/shift mnemonics to the asm parser. llvm-svn: 184834
2013-06-25 21:17:41 +08:00
# CHECK: rldicr. 2, 3, 4, 59 # encoding: [0x78,0x62,0x26,0xe5]
sldi. 2, 3, 4
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: rldicl 2, 3, 60, 4 # encoding: [0x78,0x62,0xe1,0x02]
srdi 2, 3, 4
[PowerPC] Add extended rotate/shift mnemonics This adds all missing extended rotate/shift mnemonics to the asm parser. llvm-svn: 184834
2013-06-25 21:17:41 +08:00
# CHECK: rldicl. 2, 3, 60, 4 # encoding: [0x78,0x62,0xe1,0x03]
srdi. 2, 3, 4
# CHECK: rldicl 2, 3, 0, 4 # encoding: [0x78,0x62,0x01,0x00]
clrldi 2, 3, 4
# CHECK: rldicl. 2, 3, 0, 4 # encoding: [0x78,0x62,0x01,0x01]
clrldi. 2, 3, 4
# CHECK: rldicr 2, 3, 0, 59 # encoding: [0x78,0x62,0x06,0xe4]
clrrdi 2, 3, 4
# CHECK: rldicr. 2, 3, 0, 59 # encoding: [0x78,0x62,0x06,0xe5]
clrrdi. 2, 3, 4
# CHECK: rldic 2, 3, 4, 1 # encoding: [0x78,0x62,0x20,0x48]
clrlsldi 2, 3, 5, 4
# CHECK: rldic. 2, 3, 4, 1 # encoding: [0x78,0x62,0x20,0x49]
clrlsldi. 2, 3, 5, 4
# CHECK: rlwinm 2, 3, 5, 0, 3 # encoding: [0x54,0x62,0x28,0x06]
extlwi 2, 3, 4, 5
# CHECK: rlwinm. 2, 3, 5, 0, 3 # encoding: [0x54,0x62,0x28,0x07]
extlwi. 2, 3, 4, 5
# CHECK: rlwinm 2, 3, 9, 28, 31 # encoding: [0x54,0x62,0x4f,0x3e]
extrwi 2, 3, 4, 5
# CHECK: rlwinm. 2, 3, 9, 28, 31 # encoding: [0x54,0x62,0x4f,0x3f]
extrwi. 2, 3, 4, 5
# CHECK: rlwimi 2, 3, 27, 5, 8 # encoding: [0x50,0x62,0xd9,0x50]
inslwi 2, 3, 4, 5
# CHECK: rlwimi. 2, 3, 27, 5, 8 # encoding: [0x50,0x62,0xd9,0x51]
inslwi. 2, 3, 4, 5
# CHECK: rlwimi 2, 3, 23, 5, 8 # encoding: [0x50,0x62,0xb9,0x50]
insrwi 2, 3, 4, 5
# CHECK: rlwimi. 2, 3, 23, 5, 8 # encoding: [0x50,0x62,0xb9,0x51]
insrwi. 2, 3, 4, 5
# CHECK: rlwinm 2, 3, 4, 0, 31 # encoding: [0x54,0x62,0x20,0x3e]
rotlwi 2, 3, 4
# CHECK: rlwinm. 2, 3, 4, 0, 31 # encoding: [0x54,0x62,0x20,0x3f]
rotlwi. 2, 3, 4
# CHECK: rlwinm 2, 3, 28, 0, 31 # encoding: [0x54,0x62,0xe0,0x3e]
rotrwi 2, 3, 4
# CHECK: rlwinm. 2, 3, 28, 0, 31 # encoding: [0x54,0x62,0xe0,0x3f]
rotrwi. 2, 3, 4
# CHECK: rlwnm 2, 3, 4, 0, 31 # encoding: [0x5c,0x62,0x20,0x3e]
rotlw 2, 3, 4
# CHECK: rlwnm. 2, 3, 4, 0, 31 # encoding: [0x5c,0x62,0x20,0x3f]
rotlw. 2, 3, 4
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: slwi 2, 3, 4 # encoding: [0x54,0x62,0x20,0x36]
slwi 2, 3, 4
[PowerPC] Add extended rotate/shift mnemonics This adds all missing extended rotate/shift mnemonics to the asm parser. llvm-svn: 184834
2013-06-25 21:17:41 +08:00
# CHECK: rlwinm. 2, 3, 4, 0, 27 # encoding: [0x54,0x62,0x20,0x37]
slwi. 2, 3, 4
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: srwi 2, 3, 4 # encoding: [0x54,0x62,0xe1,0x3e]
srwi 2, 3, 4
[PowerPC] Add extended rotate/shift mnemonics This adds all missing extended rotate/shift mnemonics to the asm parser. llvm-svn: 184834
2013-06-25 21:17:41 +08:00
# CHECK: rlwinm. 2, 3, 28, 4, 31 # encoding: [0x54,0x62,0xe1,0x3f]
srwi. 2, 3, 4
# CHECK: rlwinm 2, 3, 0, 4, 31 # encoding: [0x54,0x62,0x01,0x3e]
clrlwi 2, 3, 4
# CHECK: rlwinm. 2, 3, 0, 4, 31 # encoding: [0x54,0x62,0x01,0x3f]
clrlwi. 2, 3, 4
# CHECK: rlwinm 2, 3, 0, 0, 27 # encoding: [0x54,0x62,0x00,0x36]
clrrwi 2, 3, 4
# CHECK: rlwinm. 2, 3, 0, 0, 27 # encoding: [0x54,0x62,0x00,0x37]
clrrwi. 2, 3, 4
# CHECK: rlwinm 2, 3, 4, 1, 27 # encoding: [0x54,0x62,0x20,0x76]
clrlslwi 2, 3, 5, 4
# CHECK: rlwinm. 2, 3, 4, 1, 27 # encoding: [0x54,0x62,0x20,0x77]
clrlslwi. 2, 3, 5, 4
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# Move to/from special purpose register mnemonics
[PowerPC] Support mtspr/mfspr in the asm parser This adds support for the generic forms of mtspr/mfspr for the asm parser. The compiler will continue to use the specialized patters for mtlr etc. since those are needed to correctly describe data flow. llvm-svn: 185532
2013-07-03 20:32:41 +08:00
# CHECK: mtspr 1, 2 # encoding: [0x7c,0x41,0x03,0xa6]
mtxer 2
# CHECK: mfspr 2, 1 # encoding: [0x7c,0x41,0x02,0xa6]
mfxer 2
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: mtlr 2 # encoding: [0x7c,0x48,0x03,0xa6]
mtlr 2
# CHECK: mflr 2 # encoding: [0x7c,0x48,0x02,0xa6]
mflr 2
# CHECK: mtctr 2 # encoding: [0x7c,0x49,0x03,0xa6]
mtctr 2
# CHECK: mfctr 2 # encoding: [0x7c,0x49,0x02,0xa6]
mfctr 2
# Miscellaneous mnemonics
# CHECK: nop # encoding: [0x60,0x00,0x00,0x00]
nop
[PowerPC] Support some miscellaneous mnemonics in the asm parser This adds support for the following extended mnemonics: xnop mr. not not. la llvm-svn: 184767
2013-06-25 02:08:03 +08:00
# CHECK: xori 0, 0, 0 # encoding: [0x68,0x00,0x00,0x00]
xnop
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: li 2, 128 # encoding: [0x38,0x40,0x00,0x80]
li 2, 128
# CHECK: lis 2, 128 # encoding: [0x3c,0x40,0x00,0x80]
lis 2, 128
[PowerPC] Support some miscellaneous mnemonics in the asm parser This adds support for the following extended mnemonics: xnop mr. not not. la llvm-svn: 184767
2013-06-25 02:08:03 +08:00
# CHECK: la 2, 128(4)
la 2, 128(4)
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00
# CHECK: mr 2, 3 # encoding: [0x7c,0x62,0x1b,0x78]
mr 2, 3
[PowerPC] Support some miscellaneous mnemonics in the asm parser This adds support for the following extended mnemonics: xnop mr. not not. la llvm-svn: 184767
2013-06-25 02:08:03 +08:00
# CHECK: or. 2, 3, 3 # encoding: [0x7c,0x62,0x1b,0x79]
mr. 2, 3
# CHECK: nor 2, 3, 3 # encoding: [0x7c,0x62,0x18,0xf8]
not 2, 3
# CHECK: nor. 2, 3, 3 # encoding: [0x7c,0x62,0x18,0xf9]
not. 2, 3
[PowerPC] Use mtocrf when available Just as with mfocrf, it is also preferable to use mtocrf instead of mtcrf when only a single CR register is to be written. Current code however always emits mtcrf. This probably does not matter when using an external assembler, since the GNU assembler will in fact automatically replace mtcrf with mtocrf when possible. It does create inefficient code with the integrated assembler, however. To fix this, this patch adds MTOCRF/MTOCRF8 instruction patterns and uses those instead of MTCRF/MTCRF8 everything. Just as done in the MFOCRF patch committed as 185556, these patterns will be converted back to MTCRF if MTOCRF is not available on the machine. As a side effect, this allows to modify the MTCRF pattern to accept the full range of mask operands for the benefit of the asm parser. llvm-svn: 185561
2013-07-04 01:59:07 +08:00
# CHECK: mtcrf 255, 2 # encoding: [0x7c,0x4f,0xf1,0x20]
mtcr 2
[PowerPC] Support extended mnemonics in AsmParser This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
2013-05-04 03:50:27 +08:00