2012-12-12 05:25:42 +08:00
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//===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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2018-05-01 23:54:18 +08:00
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/// This file provides AMDGPU specific target descriptions.
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2012-12-12 05:25:42 +08:00
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUMCTargetDesc.h"
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2015-09-26 05:41:28 +08:00
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#include "AMDGPUELFStreamer.h"
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2012-12-12 05:25:42 +08:00
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#include "AMDGPUMCAsmInfo.h"
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2015-06-27 05:15:07 +08:00
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#include "AMDGPUTargetStreamer.h"
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2012-12-12 05:25:42 +08:00
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#include "InstPrinter/AMDGPUInstPrinter.h"
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2015-01-14 19:23:27 +08:00
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#include "SIDefines.h"
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2017-10-11 09:57:21 +08:00
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#include "llvm/MC/MCAsmBackend.h"
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2017-10-12 07:34:47 +08:00
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#include "llvm/MC/MCCodeEmitter.h"
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2015-03-11 06:03:14 +08:00
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#include "llvm/MC/MCContext.h"
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2012-12-12 05:25:42 +08:00
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#include "llvm/MC/MCInstrInfo.h"
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2018-05-19 02:26:45 +08:00
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#include "llvm/MC/MCObjectWriter.h"
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2012-12-12 05:25:42 +08:00
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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2013-01-02 18:22:59 +08:00
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#include "llvm/MC/MachineLocation.h"
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2012-12-12 05:25:42 +08:00
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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2014-04-22 10:03:14 +08:00
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using namespace llvm;
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2012-12-12 05:25:42 +08:00
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#define GET_INSTRINFO_MC_DESC
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#include "AMDGPUGenInstrInfo.inc"
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#define GET_SUBTARGETINFO_MC_DESC
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#include "AMDGPUGenSubtargetInfo.inc"
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#define GET_REGINFO_MC_DESC
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#include "AMDGPUGenRegisterInfo.inc"
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static MCInstrInfo *createAMDGPUMCInstrInfo() {
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MCInstrInfo *X = new MCInstrInfo();
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InitAMDGPUMCInstrInfo(X);
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return X;
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}
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2015-09-16 00:17:27 +08:00
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static MCRegisterInfo *createAMDGPUMCRegisterInfo(const Triple &TT) {
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2012-12-12 05:25:42 +08:00
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MCRegisterInfo *X = new MCRegisterInfo();
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InitAMDGPUMCRegisterInfo(X, 0);
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return X;
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}
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2015-09-16 00:17:27 +08:00
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static MCSubtargetInfo *
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createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
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2015-07-11 06:43:42 +08:00
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return createAMDGPUMCSubtargetInfoImpl(TT, CPU, FS);
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2012-12-12 05:25:42 +08:00
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}
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2015-09-16 00:17:27 +08:00
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static MCInstPrinter *createAMDGPUMCInstPrinter(const Triple &T,
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2015-03-31 08:10:04 +08:00
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unsigned SyntaxVariant,
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2012-12-12 05:25:42 +08:00
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const MCAsmInfo &MAI,
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const MCInstrInfo &MII,
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2015-03-31 08:10:04 +08:00
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const MCRegisterInfo &MRI) {
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AMDGPU: Add R600InstPrinter class
Summary:
This is step towards separating the GCN and R600 tablegen'd code.
This is a little awkward for now, because the R600 functions won't have the
MCSubtargetInfo parameter, so we need to have AMDMGPUInstPrinter
delegate to R600InstPrinter, but once the tablegen'd code is split,
we will be able to drop the delegation and use R600InstPrinter directly.
Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D36444
llvm-svn: 311128
2017-08-18 06:20:04 +08:00
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return T.getArch() == Triple::r600 ? new R600InstPrinter(MAI, MII, MRI) :
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new AMDGPUInstPrinter(MAI, MII, MRI);
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2012-12-12 05:25:42 +08:00
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}
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2015-06-27 05:15:07 +08:00
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static MCTargetStreamer *createAMDGPUAsmTargetStreamer(MCStreamer &S,
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formatted_raw_ostream &OS,
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MCInstPrinter *InstPrint,
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bool isVerboseAsm) {
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return new AMDGPUTargetAsmStreamer(S, OS);
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}
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static MCTargetStreamer * createAMDGPUObjectTargetStreamer(
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MCStreamer &S,
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const MCSubtargetInfo &STI) {
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2018-02-17 06:33:59 +08:00
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return new AMDGPUTargetELFStreamer(S, STI);
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2015-06-27 05:15:07 +08:00
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}
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2015-09-26 05:41:28 +08:00
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static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
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2017-10-11 09:57:21 +08:00
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std::unique_ptr<MCAsmBackend> &&MAB,
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2018-05-19 02:26:45 +08:00
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std::unique_ptr<MCObjectWriter> &&OW,
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2017-10-12 07:34:47 +08:00
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std::unique_ptr<MCCodeEmitter> &&Emitter,
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bool RelaxAll) {
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2018-05-19 02:26:45 +08:00
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return createAMDGPUELFStreamer(T, Context, std::move(MAB), std::move(OW),
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2017-10-12 07:34:47 +08:00
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std::move(Emitter), RelaxAll);
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2015-09-26 05:41:28 +08:00
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}
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2015-06-13 11:28:10 +08:00
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extern "C" void LLVMInitializeAMDGPUTargetMC() {
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2016-10-10 07:00:34 +08:00
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for (Target *T : {&getTheAMDGPUTarget(), &getTheGCNTarget()}) {
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2015-03-19 07:15:49 +08:00
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RegisterMCAsmInfo<AMDGPUMCAsmInfo> X(*T);
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TargetRegistry::RegisterMCInstrInfo(*T, createAMDGPUMCInstrInfo);
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TargetRegistry::RegisterMCRegInfo(*T, createAMDGPUMCRegisterInfo);
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TargetRegistry::RegisterMCSubtargetInfo(*T, createAMDGPUMCSubtargetInfo);
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TargetRegistry::RegisterMCInstPrinter(*T, createAMDGPUMCInstPrinter);
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TargetRegistry::RegisterMCAsmBackend(*T, createAMDGPUAsmBackend);
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2015-09-26 05:41:28 +08:00
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TargetRegistry::RegisterELFStreamer(*T, createMCStreamer);
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2015-03-19 07:15:49 +08:00
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}
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2015-06-27 05:15:07 +08:00
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// R600 specific registration
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2016-10-10 07:00:34 +08:00
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TargetRegistry::RegisterMCCodeEmitter(getTheAMDGPUTarget(),
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2015-03-19 07:15:49 +08:00
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createR600MCCodeEmitter);
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2018-02-17 06:33:59 +08:00
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TargetRegistry::RegisterObjectTargetStreamer(
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getTheAMDGPUTarget(), createAMDGPUObjectTargetStreamer);
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2015-06-27 05:15:07 +08:00
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// GCN specific registration
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2016-10-10 07:00:34 +08:00
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TargetRegistry::RegisterMCCodeEmitter(getTheGCNTarget(),
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createSIMCCodeEmitter);
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2015-06-27 05:15:07 +08:00
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2016-10-10 07:00:34 +08:00
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TargetRegistry::RegisterAsmTargetStreamer(getTheGCNTarget(),
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2015-06-27 05:15:07 +08:00
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createAMDGPUAsmTargetStreamer);
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2016-10-10 07:00:34 +08:00
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TargetRegistry::RegisterObjectTargetStreamer(
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getTheGCNTarget(), createAMDGPUObjectTargetStreamer);
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2012-12-12 05:25:42 +08:00
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}
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