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llvm-project/llvm/test/CodeGen/X86/sse42-intrinsics-fast-isel.ll

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[X86][SSE42] Added fast-isel tests to sync with clang/test/CodeGen/sse42-builtins.c llvm-svn: 269929
2016-05-18 22:28:54 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; RUN: llc < %s -fast-isel -mtriple=i386-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefixes=CHECK,X86,SSE,X86-SSE
[X86][SSE4] Tweak rL333828 sse41/sse42 cleanup to recover SKX/EVEX2VEX testing Just testing for avx512f was missing the tests for EVEX TO VEX Compression encoding etc. llvm-svn: 333830
2018-06-03 02:01:09 +08:00
; RUN: llc < %s -fast-isel -mtriple=i386-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,X86,AVX,X86-AVX,AVX1,X86-AVX1
; RUN: llc < %s -fast-isel -mtriple=i386-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl | FileCheck %s --check-prefixes=CHECK,X86,AVX,X86-AVX,AVX512,X86-AVX512
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefixes=CHECK,X64,SSE,X64-SSE
[X86][SSE4] Tweak rL333828 sse41/sse42 cleanup to recover SKX/EVEX2VEX testing Just testing for avx512f was missing the tests for EVEX TO VEX Compression encoding etc. llvm-svn: 333830
2018-06-03 02:01:09 +08:00
; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,X64,AVX,X64-AVX,AVX1,X64-AVX1
; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl | FileCheck %s --check-prefixes=CHECK,X64,AVX,X64-AVX,AVX512,X64-AVX512
[X86][SSE42] Added fast-isel tests to sync with clang/test/CodeGen/sse42-builtins.c llvm-svn: 269929
2016-05-18 22:28:54 +08:00
; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/sse42-builtins.c
Recommit r274692 - [X86] Transform setcc + movzbl into xorl + setcc xorl + setcc is generally the preferred sequence due to the partial register stall setcc + movzbl suffers from. As a bonus, it also encodes one byte smaller. This fixes PR28146. The original commit tried inserting an 8bit-subreg into a GR32 (not GR32_ABCD) which was not appreciated by fast regalloc on 32-bit. llvm-svn: 274802
2016-07-08 06:50:23 +08:00
define i32 @test_mm_cmpestra(<2 x i64> %a0, i32 %a1, <2 x i64> %a2, i32 %a3) nounwind {
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; X86-SSE-LABEL: test_mm_cmpestra:
; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pushl %ebx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: xorl %ebx, %ebx
; X86-SSE-NEXT: pcmpestri $7, %xmm1, %xmm0
; X86-SSE-NEXT: seta %bl
; X86-SSE-NEXT: movl %ebx, %eax
; X86-SSE-NEXT: popl %ebx
; X86-SSE-NEXT: retl
;
; X86-AVX-LABEL: test_mm_cmpestra:
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: pushl %ebx
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX-NEXT: xorl %ebx, %ebx
; X86-AVX-NEXT: vpcmpestri $7, %xmm1, %xmm0
; X86-AVX-NEXT: seta %bl
; X86-AVX-NEXT: movl %ebx, %eax
; X86-AVX-NEXT: popl %ebx
; X86-AVX-NEXT: retl
;
; X64-SSE-LABEL: test_mm_cmpestra:
; X64-SSE: # %bb.0:
; X64-SSE-NEXT: movl %esi, %edx
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-SSE-NEXT: movl %edi, %eax
; X64-SSE-NEXT: xorl %esi, %esi
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; X64-SSE-NEXT: pcmpestri $7, %xmm1, %xmm0
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-SSE-NEXT: seta %sil
; X64-SSE-NEXT: movl %esi, %eax
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; X64-SSE-NEXT: retq
;
; X64-AVX-LABEL: test_mm_cmpestra:
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: movl %esi, %edx
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-AVX-NEXT: movl %edi, %eax
; X64-AVX-NEXT: xorl %esi, %esi
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; X64-AVX-NEXT: vpcmpestri $7, %xmm1, %xmm0
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-AVX-NEXT: seta %sil
; X64-AVX-NEXT: movl %esi, %eax
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; X64-AVX-NEXT: retq
[X86][SSE42] Added fast-isel tests to sync with clang/test/CodeGen/sse42-builtins.c llvm-svn: 269929
2016-05-18 22:28:54 +08:00
%arg0 = bitcast <2 x i64> %a0 to <16 x i8>
%arg2 = bitcast <2 x i64> %a2 to <16 x i8>
%res = call i32 @llvm.x86.sse42.pcmpestria128(<16 x i8> %arg0, i32 %a1, <16 x i8> %arg2, i32 %a3, i8 7)
ret i32 %res
}
declare i32 @llvm.x86.sse42.pcmpestria128(<16 x i8>, i32, <16 x i8>, i32, i8) nounwind readnone
[x86] don't blindly transform SETB into SBB I noticed unnecessary 'sbb' instructions in D30472 and while looking at 'ptest' codegen recently. This happens because we were transforming any 'setb' - even when we only wanted a single-bit result. This patch moves those transforms under visitAdd/visitSub, so we we're only creating sbb/adc when it is a win. I don't know why we need a SETCC_CARRY node type, but I'm not proposing to change that existing behavior in this patch. Also, I'm skeptical that sbb/adc are a win for all micro-arches, so I added comments to the test files where this transform still fires. The test changes here are all cases where we no longer produce sbb/adc. Avoiding partial register stalls (generating an xor to clear a register) is not handled in some cases, but that's a separate issue. Differential Revision: https://reviews.llvm.org/D30611 llvm-svn: 297586
2017-03-13 02:28:48 +08:00
define i32 @test_mm_cmpestrc(<2 x i64> %a0, i32 %a1, <2 x i64> %a2, i32 %a3) nounwind {
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; X86-SSE-LABEL: test_mm_cmpestrc:
; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pushl %ebx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: xorl %ebx, %ebx
; X86-SSE-NEXT: pcmpestri $7, %xmm1, %xmm0
; X86-SSE-NEXT: setb %bl
; X86-SSE-NEXT: movl %ebx, %eax
; X86-SSE-NEXT: popl %ebx
; X86-SSE-NEXT: retl
;
; X86-AVX-LABEL: test_mm_cmpestrc:
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: pushl %ebx
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX-NEXT: xorl %ebx, %ebx
; X86-AVX-NEXT: vpcmpestri $7, %xmm1, %xmm0
; X86-AVX-NEXT: setb %bl
; X86-AVX-NEXT: movl %ebx, %eax
; X86-AVX-NEXT: popl %ebx
; X86-AVX-NEXT: retl
;
; X64-SSE-LABEL: test_mm_cmpestrc:
; X64-SSE: # %bb.0:
; X64-SSE-NEXT: movl %esi, %edx
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-SSE-NEXT: movl %edi, %eax
; X64-SSE-NEXT: xorl %esi, %esi
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; X64-SSE-NEXT: pcmpestri $7, %xmm1, %xmm0
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-SSE-NEXT: setb %sil
; X64-SSE-NEXT: movl %esi, %eax
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; X64-SSE-NEXT: retq
;
; X64-AVX-LABEL: test_mm_cmpestrc:
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: movl %esi, %edx
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-AVX-NEXT: movl %edi, %eax
; X64-AVX-NEXT: xorl %esi, %esi
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; X64-AVX-NEXT: vpcmpestri $7, %xmm1, %xmm0
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-AVX-NEXT: setb %sil
; X64-AVX-NEXT: movl %esi, %eax
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; X64-AVX-NEXT: retq
[X86][SSE42] Added fast-isel tests to sync with clang/test/CodeGen/sse42-builtins.c llvm-svn: 269929
2016-05-18 22:28:54 +08:00
%arg0 = bitcast <2 x i64> %a0 to <16 x i8>
%arg2 = bitcast <2 x i64> %a2 to <16 x i8>
%res = call i32 @llvm.x86.sse42.pcmpestric128(<16 x i8> %arg0, i32 %a1, <16 x i8> %arg2, i32 %a3, i8 7)
ret i32 %res
}
declare i32 @llvm.x86.sse42.pcmpestric128(<16 x i8>, i32, <16 x i8>, i32, i8) nounwind readnone
define i32 @test_mm_cmpestri(<2 x i64> %a0, i32 %a1, <2 x i64> %a2, i32 %a3) {
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; X86-SSE-LABEL: test_mm_cmpestri:
; X86-SSE: # %bb.0:
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: pcmpestri $7, %xmm1, %xmm0
; X86-SSE-NEXT: movl %ecx, %eax
; X86-SSE-NEXT: retl
;
; X86-AVX-LABEL: test_mm_cmpestri:
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX-NEXT: vpcmpestri $7, %xmm1, %xmm0
; X86-AVX-NEXT: movl %ecx, %eax
; X86-AVX-NEXT: retl
;
; X64-SSE-LABEL: test_mm_cmpestri:
; X64-SSE: # %bb.0:
; X64-SSE-NEXT: movl %esi, %edx
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-SSE-NEXT: movl %edi, %eax
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; X64-SSE-NEXT: pcmpestri $7, %xmm1, %xmm0
; X64-SSE-NEXT: movl %ecx, %eax
; X64-SSE-NEXT: retq
;
; X64-AVX-LABEL: test_mm_cmpestri:
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: movl %esi, %edx
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-AVX-NEXT: movl %edi, %eax
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; X64-AVX-NEXT: vpcmpestri $7, %xmm1, %xmm0
; X64-AVX-NEXT: movl %ecx, %eax
; X64-AVX-NEXT: retq
[X86][SSE42] Added fast-isel tests to sync with clang/test/CodeGen/sse42-builtins.c llvm-svn: 269929
2016-05-18 22:28:54 +08:00
%arg0 = bitcast <2 x i64> %a0 to <16 x i8>
%arg2 = bitcast <2 x i64> %a2 to <16 x i8>
%res = call i32 @llvm.x86.sse42.pcmpestri128(<16 x i8> %arg0, i32 %a1, <16 x i8> %arg2, i32 %a3, i8 7)
ret i32 %res
}
declare i32 @llvm.x86.sse42.pcmpestri128(<16 x i8>, i32, <16 x i8>, i32, i8) nounwind readnone
define <2 x i64> @test_mm_cmpestrm(<2 x i64> %a0, i32 %a1, <2 x i64> %a2, i32 %a3) {
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; X86-SSE-LABEL: test_mm_cmpestrm:
; X86-SSE: # %bb.0:
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: pcmpestrm $7, %xmm1, %xmm0
; X86-SSE-NEXT: retl
;
; X86-AVX-LABEL: test_mm_cmpestrm:
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX-NEXT: vpcmpestrm $7, %xmm1, %xmm0
; X86-AVX-NEXT: retl
;
; X64-SSE-LABEL: test_mm_cmpestrm:
; X64-SSE: # %bb.0:
; X64-SSE-NEXT: movl %esi, %edx
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-SSE-NEXT: movl %edi, %eax
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; X64-SSE-NEXT: pcmpestrm $7, %xmm1, %xmm0
; X64-SSE-NEXT: retq
;
; X64-AVX-LABEL: test_mm_cmpestrm:
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: movl %esi, %edx
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-AVX-NEXT: movl %edi, %eax
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; X64-AVX-NEXT: vpcmpestrm $7, %xmm1, %xmm0
; X64-AVX-NEXT: retq
[X86][SSE42] Added fast-isel tests to sync with clang/test/CodeGen/sse42-builtins.c llvm-svn: 269929
2016-05-18 22:28:54 +08:00
%arg0 = bitcast <2 x i64> %a0 to <16 x i8>
%arg2 = bitcast <2 x i64> %a2 to <16 x i8>
%res = call <16 x i8> @llvm.x86.sse42.pcmpestrm128(<16 x i8> %arg0, i32 %a1, <16 x i8> %arg2, i32 %a3, i8 7)
%bc = bitcast <16 x i8> %res to <2 x i64>
ret <2 x i64> %bc
}
declare <16 x i8> @llvm.x86.sse42.pcmpestrm128(<16 x i8>, i32, <16 x i8>, i32, i8) nounwind readnone
Recommit r274692 - [X86] Transform setcc + movzbl into xorl + setcc xorl + setcc is generally the preferred sequence due to the partial register stall setcc + movzbl suffers from. As a bonus, it also encodes one byte smaller. This fixes PR28146. The original commit tried inserting an 8bit-subreg into a GR32 (not GR32_ABCD) which was not appreciated by fast regalloc on 32-bit. llvm-svn: 274802
2016-07-08 06:50:23 +08:00
define i32 @test_mm_cmpestro(<2 x i64> %a0, i32 %a1, <2 x i64> %a2, i32 %a3) nounwind {
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; X86-SSE-LABEL: test_mm_cmpestro:
; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pushl %ebx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: xorl %ebx, %ebx
; X86-SSE-NEXT: pcmpestri $7, %xmm1, %xmm0
; X86-SSE-NEXT: seto %bl
; X86-SSE-NEXT: movl %ebx, %eax
; X86-SSE-NEXT: popl %ebx
; X86-SSE-NEXT: retl
;
; X86-AVX-LABEL: test_mm_cmpestro:
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: pushl %ebx
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX-NEXT: xorl %ebx, %ebx
; X86-AVX-NEXT: vpcmpestri $7, %xmm1, %xmm0
; X86-AVX-NEXT: seto %bl
; X86-AVX-NEXT: movl %ebx, %eax
; X86-AVX-NEXT: popl %ebx
; X86-AVX-NEXT: retl
;
; X64-SSE-LABEL: test_mm_cmpestro:
; X64-SSE: # %bb.0:
; X64-SSE-NEXT: movl %esi, %edx
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-SSE-NEXT: movl %edi, %eax
; X64-SSE-NEXT: xorl %esi, %esi
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; X64-SSE-NEXT: pcmpestri $7, %xmm1, %xmm0
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-SSE-NEXT: seto %sil
; X64-SSE-NEXT: movl %esi, %eax
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; X64-SSE-NEXT: retq
;
; X64-AVX-LABEL: test_mm_cmpestro:
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: movl %esi, %edx
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-AVX-NEXT: movl %edi, %eax
; X64-AVX-NEXT: xorl %esi, %esi
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; X64-AVX-NEXT: vpcmpestri $7, %xmm1, %xmm0
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-AVX-NEXT: seto %sil
; X64-AVX-NEXT: movl %esi, %eax
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; X64-AVX-NEXT: retq
[X86][SSE42] Added fast-isel tests to sync with clang/test/CodeGen/sse42-builtins.c llvm-svn: 269929
2016-05-18 22:28:54 +08:00
%arg0 = bitcast <2 x i64> %a0 to <16 x i8>
%arg2 = bitcast <2 x i64> %a2 to <16 x i8>
%res = call i32 @llvm.x86.sse42.pcmpestrio128(<16 x i8> %arg0, i32 %a1, <16 x i8> %arg2, i32 %a3, i8 7)
ret i32 %res
}
declare i32 @llvm.x86.sse42.pcmpestrio128(<16 x i8>, i32, <16 x i8>, i32, i8) nounwind readnone
Recommit r274692 - [X86] Transform setcc + movzbl into xorl + setcc xorl + setcc is generally the preferred sequence due to the partial register stall setcc + movzbl suffers from. As a bonus, it also encodes one byte smaller. This fixes PR28146. The original commit tried inserting an 8bit-subreg into a GR32 (not GR32_ABCD) which was not appreciated by fast regalloc on 32-bit. llvm-svn: 274802
2016-07-08 06:50:23 +08:00
define i32 @test_mm_cmpestrs(<2 x i64> %a0, i32 %a1, <2 x i64> %a2, i32 %a3) nounwind {
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; X86-SSE-LABEL: test_mm_cmpestrs:
; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pushl %ebx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: xorl %ebx, %ebx
; X86-SSE-NEXT: pcmpestri $7, %xmm1, %xmm0
; X86-SSE-NEXT: sets %bl
; X86-SSE-NEXT: movl %ebx, %eax
; X86-SSE-NEXT: popl %ebx
; X86-SSE-NEXT: retl
;
; X86-AVX-LABEL: test_mm_cmpestrs:
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: pushl %ebx
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX-NEXT: xorl %ebx, %ebx
; X86-AVX-NEXT: vpcmpestri $7, %xmm1, %xmm0
; X86-AVX-NEXT: sets %bl
; X86-AVX-NEXT: movl %ebx, %eax
; X86-AVX-NEXT: popl %ebx
; X86-AVX-NEXT: retl
;
; X64-SSE-LABEL: test_mm_cmpestrs:
; X64-SSE: # %bb.0:
; X64-SSE-NEXT: movl %esi, %edx
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-SSE-NEXT: movl %edi, %eax
; X64-SSE-NEXT: xorl %esi, %esi
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; X64-SSE-NEXT: pcmpestri $7, %xmm1, %xmm0
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-SSE-NEXT: sets %sil
; X64-SSE-NEXT: movl %esi, %eax
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; X64-SSE-NEXT: retq
;
; X64-AVX-LABEL: test_mm_cmpestrs:
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: movl %esi, %edx
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-AVX-NEXT: movl %edi, %eax
; X64-AVX-NEXT: xorl %esi, %esi
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; X64-AVX-NEXT: vpcmpestri $7, %xmm1, %xmm0
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-AVX-NEXT: sets %sil
; X64-AVX-NEXT: movl %esi, %eax
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; X64-AVX-NEXT: retq
[X86][SSE42] Added fast-isel tests to sync with clang/test/CodeGen/sse42-builtins.c llvm-svn: 269929
2016-05-18 22:28:54 +08:00
%arg0 = bitcast <2 x i64> %a0 to <16 x i8>
%arg2 = bitcast <2 x i64> %a2 to <16 x i8>
%res = call i32 @llvm.x86.sse42.pcmpestris128(<16 x i8> %arg0, i32 %a1, <16 x i8> %arg2, i32 %a3, i8 7)
ret i32 %res
}
declare i32 @llvm.x86.sse42.pcmpestris128(<16 x i8>, i32, <16 x i8>, i32, i8) nounwind readnone
Recommit r274692 - [X86] Transform setcc + movzbl into xorl + setcc xorl + setcc is generally the preferred sequence due to the partial register stall setcc + movzbl suffers from. As a bonus, it also encodes one byte smaller. This fixes PR28146. The original commit tried inserting an 8bit-subreg into a GR32 (not GR32_ABCD) which was not appreciated by fast regalloc on 32-bit. llvm-svn: 274802
2016-07-08 06:50:23 +08:00
define i32 @test_mm_cmpestrz(<2 x i64> %a0, i32 %a1, <2 x i64> %a2, i32 %a3) nounwind {
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; X86-SSE-LABEL: test_mm_cmpestrz:
; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pushl %ebx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: xorl %ebx, %ebx
; X86-SSE-NEXT: pcmpestri $7, %xmm1, %xmm0
; X86-SSE-NEXT: sete %bl
; X86-SSE-NEXT: movl %ebx, %eax
; X86-SSE-NEXT: popl %ebx
; X86-SSE-NEXT: retl
;
; X86-AVX-LABEL: test_mm_cmpestrz:
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: pushl %ebx
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX-NEXT: xorl %ebx, %ebx
; X86-AVX-NEXT: vpcmpestri $7, %xmm1, %xmm0
; X86-AVX-NEXT: sete %bl
; X86-AVX-NEXT: movl %ebx, %eax
; X86-AVX-NEXT: popl %ebx
; X86-AVX-NEXT: retl
;
; X64-SSE-LABEL: test_mm_cmpestrz:
; X64-SSE: # %bb.0:
; X64-SSE-NEXT: movl %esi, %edx
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-SSE-NEXT: movl %edi, %eax
; X64-SSE-NEXT: xorl %esi, %esi
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; X64-SSE-NEXT: pcmpestri $7, %xmm1, %xmm0
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-SSE-NEXT: sete %sil
; X64-SSE-NEXT: movl %esi, %eax
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; X64-SSE-NEXT: retq
;
; X64-AVX-LABEL: test_mm_cmpestrz:
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: movl %esi, %edx
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-AVX-NEXT: movl %edi, %eax
; X64-AVX-NEXT: xorl %esi, %esi
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; X64-AVX-NEXT: vpcmpestri $7, %xmm1, %xmm0
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-AVX-NEXT: sete %sil
; X64-AVX-NEXT: movl %esi, %eax
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; X64-AVX-NEXT: retq
[X86][SSE42] Added fast-isel tests to sync with clang/test/CodeGen/sse42-builtins.c llvm-svn: 269929
2016-05-18 22:28:54 +08:00
%arg0 = bitcast <2 x i64> %a0 to <16 x i8>
%arg2 = bitcast <2 x i64> %a2 to <16 x i8>
%res = call i32 @llvm.x86.sse42.pcmpestriz128(<16 x i8> %arg0, i32 %a1, <16 x i8> %arg2, i32 %a3, i8 7)
ret i32 %res
}
declare i32 @llvm.x86.sse42.pcmpestriz128(<16 x i8>, i32, <16 x i8>, i32, i8) nounwind readnone
define <2 x i64> @test_mm_cmpgt_epi64(<2 x i64> %a0, <2 x i64> %a1) {
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; SSE-LABEL: test_mm_cmpgt_epi64:
; SSE: # %bb.0:
; SSE-NEXT: pcmpgtq %xmm1, %xmm0
; SSE-NEXT: ret{{[l|q]}}
;
[X86][SSE4] Tweak rL333828 sse41/sse42 cleanup to recover SKX/EVEX2VEX testing Just testing for avx512f was missing the tests for EVEX TO VEX Compression encoding etc. llvm-svn: 333830
2018-06-03 02:01:09 +08:00
; AVX1-LABEL: test_mm_cmpgt_epi64:
; AVX1: # %bb.0:
; AVX1-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0
; AVX1-NEXT: ret{{[l|q]}}
;
; AVX512-LABEL: test_mm_cmpgt_epi64:
; AVX512: # %bb.0:
; AVX512-NEXT: vpcmpgtq %xmm1, %xmm0, %k0
; AVX512-NEXT: vpmovm2q %k0, %xmm0
; AVX512-NEXT: ret{{[l|q]}}
[X86][SSE42] Added fast-isel tests to sync with clang/test/CodeGen/sse42-builtins.c llvm-svn: 269929
2016-05-18 22:28:54 +08:00
%cmp = icmp sgt <2 x i64> %a0, %a1
%res = sext <2 x i1> %cmp to <2 x i64>
ret <2 x i64> %res
}
define i32 @test_mm_cmpistra(<2 x i64> %a0, <2 x i64> %a1) {
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; SSE-LABEL: test_mm_cmpistra:
; SSE: # %bb.0:
; SSE-NEXT: xorl %eax, %eax
; SSE-NEXT: pcmpistri $7, %xmm1, %xmm0
; SSE-NEXT: seta %al
; SSE-NEXT: ret{{[l|q]}}
;
; AVX-LABEL: test_mm_cmpistra:
; AVX: # %bb.0:
; AVX-NEXT: xorl %eax, %eax
; AVX-NEXT: vpcmpistri $7, %xmm1, %xmm0
; AVX-NEXT: seta %al
; AVX-NEXT: ret{{[l|q]}}
[X86][SSE42] Added fast-isel tests to sync with clang/test/CodeGen/sse42-builtins.c llvm-svn: 269929
2016-05-18 22:28:54 +08:00
%arg0 = bitcast <2 x i64> %a0 to <16 x i8>
%arg1 = bitcast <2 x i64> %a1 to <16 x i8>
%res = call i32 @llvm.x86.sse42.pcmpistria128(<16 x i8> %arg0, <16 x i8> %arg1, i8 7)
ret i32 %res
}
declare i32 @llvm.x86.sse42.pcmpistria128(<16 x i8>, <16 x i8>, i8) nounwind readnone
define i32 @test_mm_cmpistrc(<2 x i64> %a0, <2 x i64> %a1) {
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; SSE-LABEL: test_mm_cmpistrc:
; SSE: # %bb.0:
; SSE-NEXT: xorl %eax, %eax
; SSE-NEXT: pcmpistri $7, %xmm1, %xmm0
; SSE-NEXT: setb %al
; SSE-NEXT: ret{{[l|q]}}
;
; AVX-LABEL: test_mm_cmpistrc:
; AVX: # %bb.0:
; AVX-NEXT: xorl %eax, %eax
; AVX-NEXT: vpcmpistri $7, %xmm1, %xmm0
; AVX-NEXT: setb %al
; AVX-NEXT: ret{{[l|q]}}
[X86][SSE42] Added fast-isel tests to sync with clang/test/CodeGen/sse42-builtins.c llvm-svn: 269929
2016-05-18 22:28:54 +08:00
%arg0 = bitcast <2 x i64> %a0 to <16 x i8>
%arg1 = bitcast <2 x i64> %a1 to <16 x i8>
%res = call i32 @llvm.x86.sse42.pcmpistric128(<16 x i8> %arg0, <16 x i8> %arg1, i8 7)
ret i32 %res
}
declare i32 @llvm.x86.sse42.pcmpistric128(<16 x i8>, <16 x i8>, i8) nounwind readnone
define i32 @test_mm_cmpistri(<2 x i64> %a0, <2 x i64> %a1) {
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; SSE-LABEL: test_mm_cmpistri:
; SSE: # %bb.0:
; SSE-NEXT: pcmpistri $7, %xmm1, %xmm0
; SSE-NEXT: movl %ecx, %eax
; SSE-NEXT: ret{{[l|q]}}
;
; AVX-LABEL: test_mm_cmpistri:
; AVX: # %bb.0:
; AVX-NEXT: vpcmpistri $7, %xmm1, %xmm0
; AVX-NEXT: movl %ecx, %eax
; AVX-NEXT: ret{{[l|q]}}
[X86][SSE42] Added fast-isel tests to sync with clang/test/CodeGen/sse42-builtins.c llvm-svn: 269929
2016-05-18 22:28:54 +08:00
%arg0 = bitcast <2 x i64> %a0 to <16 x i8>
%arg1 = bitcast <2 x i64> %a1 to <16 x i8>
%res = call i32 @llvm.x86.sse42.pcmpistri128(<16 x i8> %arg0, <16 x i8> %arg1, i8 7)
ret i32 %res
}
declare i32 @llvm.x86.sse42.pcmpistri128(<16 x i8>, <16 x i8>, i8) nounwind readnone
define <2 x i64> @test_mm_cmpistrm(<2 x i64> %a0, <2 x i64> %a1) {
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; SSE-LABEL: test_mm_cmpistrm:
; SSE: # %bb.0:
; SSE-NEXT: pcmpistrm $7, %xmm1, %xmm0
; SSE-NEXT: ret{{[l|q]}}
;
; AVX-LABEL: test_mm_cmpistrm:
; AVX: # %bb.0:
; AVX-NEXT: vpcmpistrm $7, %xmm1, %xmm0
; AVX-NEXT: ret{{[l|q]}}
[X86][SSE42] Added fast-isel tests to sync with clang/test/CodeGen/sse42-builtins.c llvm-svn: 269929
2016-05-18 22:28:54 +08:00
%arg0 = bitcast <2 x i64> %a0 to <16 x i8>
%arg1 = bitcast <2 x i64> %a1 to <16 x i8>
%res = call <16 x i8> @llvm.x86.sse42.pcmpistrm128(<16 x i8> %arg0, <16 x i8> %arg1, i8 7)
%bc = bitcast <16 x i8> %res to <2 x i64>
ret <2 x i64> %bc
}
declare <16 x i8> @llvm.x86.sse42.pcmpistrm128(<16 x i8>, <16 x i8>, i8) nounwind readnone
define i32 @test_mm_cmpistro(<2 x i64> %a0, <2 x i64> %a1) {
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; SSE-LABEL: test_mm_cmpistro:
; SSE: # %bb.0:
; SSE-NEXT: xorl %eax, %eax
; SSE-NEXT: pcmpistri $7, %xmm1, %xmm0
; SSE-NEXT: seto %al
; SSE-NEXT: ret{{[l|q]}}
;
; AVX-LABEL: test_mm_cmpistro:
; AVX: # %bb.0:
; AVX-NEXT: xorl %eax, %eax
; AVX-NEXT: vpcmpistri $7, %xmm1, %xmm0
; AVX-NEXT: seto %al
; AVX-NEXT: ret{{[l|q]}}
[X86][SSE42] Added fast-isel tests to sync with clang/test/CodeGen/sse42-builtins.c llvm-svn: 269929
2016-05-18 22:28:54 +08:00
%arg0 = bitcast <2 x i64> %a0 to <16 x i8>
%arg1 = bitcast <2 x i64> %a1 to <16 x i8>
%res = call i32 @llvm.x86.sse42.pcmpistrio128(<16 x i8> %arg0, <16 x i8> %arg1, i8 7)
ret i32 %res
}
declare i32 @llvm.x86.sse42.pcmpistrio128(<16 x i8>, <16 x i8>, i8) nounwind readnone
define i32 @test_mm_cmpistrs(<2 x i64> %a0, <2 x i64> %a1) {
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; SSE-LABEL: test_mm_cmpistrs:
; SSE: # %bb.0:
; SSE-NEXT: xorl %eax, %eax
; SSE-NEXT: pcmpistri $7, %xmm1, %xmm0
; SSE-NEXT: sets %al
; SSE-NEXT: ret{{[l|q]}}
;
; AVX-LABEL: test_mm_cmpistrs:
; AVX: # %bb.0:
; AVX-NEXT: xorl %eax, %eax
; AVX-NEXT: vpcmpistri $7, %xmm1, %xmm0
; AVX-NEXT: sets %al
; AVX-NEXT: ret{{[l|q]}}
[X86][SSE42] Added fast-isel tests to sync with clang/test/CodeGen/sse42-builtins.c llvm-svn: 269929
2016-05-18 22:28:54 +08:00
%arg0 = bitcast <2 x i64> %a0 to <16 x i8>
%arg1 = bitcast <2 x i64> %a1 to <16 x i8>
%res = call i32 @llvm.x86.sse42.pcmpistris128(<16 x i8> %arg0, <16 x i8> %arg1, i8 7)
ret i32 %res
}
declare i32 @llvm.x86.sse42.pcmpistris128(<16 x i8>, <16 x i8>, i8) nounwind readnone
define i32 @test_mm_cmpistrz(<2 x i64> %a0, <2 x i64> %a1) {
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; SSE-LABEL: test_mm_cmpistrz:
; SSE: # %bb.0:
; SSE-NEXT: xorl %eax, %eax
; SSE-NEXT: pcmpistri $7, %xmm1, %xmm0
; SSE-NEXT: sete %al
; SSE-NEXT: ret{{[l|q]}}
;
; AVX-LABEL: test_mm_cmpistrz:
; AVX: # %bb.0:
; AVX-NEXT: xorl %eax, %eax
; AVX-NEXT: vpcmpistri $7, %xmm1, %xmm0
; AVX-NEXT: sete %al
; AVX-NEXT: ret{{[l|q]}}
[X86][SSE42] Added fast-isel tests to sync with clang/test/CodeGen/sse42-builtins.c llvm-svn: 269929
2016-05-18 22:28:54 +08:00
%arg0 = bitcast <2 x i64> %a0 to <16 x i8>
%arg1 = bitcast <2 x i64> %a1 to <16 x i8>
%res = call i32 @llvm.x86.sse42.pcmpistriz128(<16 x i8> %arg0, <16 x i8> %arg1, i8 7)
ret i32 %res
}
declare i32 @llvm.x86.sse42.pcmpistriz128(<16 x i8>, <16 x i8>, i8) nounwind readnone
define i32 @test_mm_crc32_u8(i32 %a0, i8 %a1) {
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; X86-LABEL: test_mm_crc32_u8:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: crc32b {{[0-9]+}}(%esp), %eax
; X86-NEXT: retl
[X86][SSE42] Added fast-isel tests to sync with clang/test/CodeGen/sse42-builtins.c llvm-svn: 269929
2016-05-18 22:28:54 +08:00
;
; X64-LABEL: test_mm_crc32_u8:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X64: # %bb.0:
[X86][SSE42] Added fast-isel tests to sync with clang/test/CodeGen/sse42-builtins.c llvm-svn: 269929
2016-05-18 22:28:54 +08:00
; X64-NEXT: movl %edi, %eax
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-NEXT: crc32b %sil, %eax
[X86][SSE42] Added fast-isel tests to sync with clang/test/CodeGen/sse42-builtins.c llvm-svn: 269929
2016-05-18 22:28:54 +08:00
; X64-NEXT: retq
%res = call i32 @llvm.x86.sse42.crc32.32.8(i32 %a0, i8 %a1)
ret i32 %res
}
declare i32 @llvm.x86.sse42.crc32.32.8(i32, i8) nounwind readnone
define i32 @test_mm_crc32_u16(i32 %a0, i16 %a1) {
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; X86-LABEL: test_mm_crc32_u16:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: crc32w {{[0-9]+}}(%esp), %eax
; X86-NEXT: retl
[X86][SSE42] Added fast-isel tests to sync with clang/test/CodeGen/sse42-builtins.c llvm-svn: 269929
2016-05-18 22:28:54 +08:00
;
; X64-LABEL: test_mm_crc32_u16:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X64: # %bb.0:
[X86][SSE42] Added fast-isel tests to sync with clang/test/CodeGen/sse42-builtins.c llvm-svn: 269929
2016-05-18 22:28:54 +08:00
; X64-NEXT: movl %edi, %eax
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-NEXT: crc32w %si, %eax
[X86][SSE42] Added fast-isel tests to sync with clang/test/CodeGen/sse42-builtins.c llvm-svn: 269929
2016-05-18 22:28:54 +08:00
; X64-NEXT: retq
%res = call i32 @llvm.x86.sse42.crc32.32.16(i32 %a0, i16 %a1)
ret i32 %res
}
declare i32 @llvm.x86.sse42.crc32.32.16(i32, i16) nounwind readnone
define i32 @test_mm_crc32_u32(i32 %a0, i32 %a1) {
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; X86-LABEL: test_mm_crc32_u32:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: crc32l {{[0-9]+}}(%esp), %eax
; X86-NEXT: retl
[X86][SSE42] Added fast-isel tests to sync with clang/test/CodeGen/sse42-builtins.c llvm-svn: 269929
2016-05-18 22:28:54 +08:00
;
; X64-LABEL: test_mm_crc32_u32:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X64: # %bb.0:
[X86][SSE42] Added fast-isel tests to sync with clang/test/CodeGen/sse42-builtins.c llvm-svn: 269929
2016-05-18 22:28:54 +08:00
; X64-NEXT: movl %edi, %eax
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-NEXT: crc32l %esi, %eax
[X86][SSE42] Added fast-isel tests to sync with clang/test/CodeGen/sse42-builtins.c llvm-svn: 269929
2016-05-18 22:28:54 +08:00
; X64-NEXT: retq
%res = call i32 @llvm.x86.sse42.crc32.32.32(i32 %a0, i32 %a1)
ret i32 %res
}
declare i32 @llvm.x86.sse42.crc32.32.32(i32, i32) nounwind readnone