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llvm-project/llvm/test/CodeGen/X86/avx512vpopcntdq-schedule.ll

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[X86] Add AVX512 VPOPCNTDQ schedule tests Demonstrates how to perform full coverage avx512 schedule tests llvm-svn: 320805
2017-12-15 19:32:31 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=x86-64 -mattr=+avx512vpopcntdq | FileCheck %s --check-prefix=GENERIC
[X86] Split up -march=icelake to -client & -server Reviewers: craig.topper, zvi, echristo Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45055 llvm-svn: 329742
2018-04-11 02:59:13 +08:00
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=icelake-client | FileCheck %s --check-prefix=ICELAKE
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=icelake-server | FileCheck %s --check-prefix=ICELAKE
[X86] Add AVX512 VPOPCNTDQ schedule tests Demonstrates how to perform full coverage avx512 schedule tests llvm-svn: 320805
2017-12-15 19:32:31 +08:00
define void @test_vpopcntd(<16 x i32> %a0, <16 x i32> %a1, <16 x i32> *%a2, i16 %a3) {
; GENERIC-LABEL: test_vpopcntd:
; GENERIC: # %bb.0:
; GENERIC-NEXT: kmovw %esi, %k1 # sched: [1:0.33]
; GENERIC-NEXT: #APP
[X86] Split WriteVecALU/WritePHAdd into XMM and YMM/ZMM scheduler classes llvm-svn: 331453
2018-05-03 21:27:10 +08:00
; GENERIC-NEXT: vpopcntd %zmm1, %zmm0 # sched: [1:0.50]
; GENERIC-NEXT: vpopcntd %zmm1, %zmm0 {%k1} # sched: [1:0.50]
; GENERIC-NEXT: vpopcntd %zmm1, %zmm0 {%k1} {z} # sched: [1:0.50]
; GENERIC-NEXT: vpopcntd (%rdi), %zmm0 # sched: [8:0.50]
; GENERIC-NEXT: vpopcntd (%rdi), %zmm0 {%k1} # sched: [8:0.50]
; GENERIC-NEXT: vpopcntd (%rdi), %zmm0 {%k1} {z} # sched: [8:0.50]
; GENERIC-NEXT: vpopcntd (%rdi){1to16}, %zmm0 # sched: [8:0.50]
; GENERIC-NEXT: vpopcntd (%rdi){1to16}, %zmm0 {%k1} # sched: [8:0.50]
; GENERIC-NEXT: vpopcntd (%rdi){1to16}, %zmm0 {%k1} {z} # sched: [8:0.50]
[X86] Add AVX512 VPOPCNTDQ schedule tests Demonstrates how to perform full coverage avx512 schedule tests llvm-svn: 320805
2017-12-15 19:32:31 +08:00
; GENERIC-NEXT: #NO_APP
[X86] Fix VZEROUPPER scheduling info on SNB,HSW,BDW,SXL,SKX. Summary: Starting from SNB, VZEROUPPER is handled by the renamer and uses no proc resources. After HSW, it also has zero latency. This fixes PR35606. To reproduce: Uops: llvm-exegesis -mode=uops -opcode-name=VZEROUPPER Latency: echo -e '#LLVM-EXEGESIS-DEFREG XMM0 1\n#LLVM-EXEGESIS-DEFREG XMM1 1\nvzeroupper' | /tmp/llvm-exegesis -mode=latency -snippets-file=- echo -e '#LLVM-EXEGESIS-DEFREG XMM0 1\n#LLVM-EXEGESIS-DEFREG XMM1 1\nvzeroupper\naddps %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=latency -snippets-file=- Reviewers: RKSimon, craig.topper, andreadb Subscribers: gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D54107 llvm-svn: 346482
2018-11-09 17:49:06 +08:00
; GENERIC-NEXT: vzeroupper # sched: [1:1.00]
[X86] Add AVX512 VPOPCNTDQ schedule tests Demonstrates how to perform full coverage avx512 schedule tests llvm-svn: 320805
2017-12-15 19:32:31 +08:00
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; ICELAKE-LABEL: test_vpopcntd:
; ICELAKE: # %bb.0:
; ICELAKE-NEXT: kmovd %esi, %k1 # sched: [1:1.00]
; ICELAKE-NEXT: #APP
[X86] Fix skylake server scheduling info. Summary: This fixes most of the scheduling info for SKX vector operations. I had to split a lot of the YMM/ZMM classes into separate classes for YMM and ZMM. The before/after llvm-exegesis analysis are in the phabricator diff. Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D47721 llvm-svn: 334407
2018-06-11 22:37:53 +08:00
; ICELAKE-NEXT: vpopcntd %zmm1, %zmm0 # sched: [1:1.00]
; ICELAKE-NEXT: vpopcntd %zmm1, %zmm0 {%k1} # sched: [1:1.00]
; ICELAKE-NEXT: vpopcntd %zmm1, %zmm0 {%k1} {z} # sched: [1:1.00]
; ICELAKE-NEXT: vpopcntd (%rdi), %zmm0 # sched: [8:1.00]
; ICELAKE-NEXT: vpopcntd (%rdi), %zmm0 {%k1} # sched: [8:1.00]
; ICELAKE-NEXT: vpopcntd (%rdi), %zmm0 {%k1} {z} # sched: [8:1.00]
; ICELAKE-NEXT: vpopcntd (%rdi){1to16}, %zmm0 # sched: [8:1.00]
; ICELAKE-NEXT: vpopcntd (%rdi){1to16}, %zmm0 {%k1} # sched: [8:1.00]
; ICELAKE-NEXT: vpopcntd (%rdi){1to16}, %zmm0 {%k1} {z} # sched: [8:1.00]
[X86] Add AVX512 VPOPCNTDQ schedule tests Demonstrates how to perform full coverage avx512 schedule tests llvm-svn: 320805
2017-12-15 19:32:31 +08:00
; ICELAKE-NEXT: #NO_APP
[X86] Fix VZEROUPPER scheduling info on SNB,HSW,BDW,SXL,SKX. Summary: Starting from SNB, VZEROUPPER is handled by the renamer and uses no proc resources. After HSW, it also has zero latency. This fixes PR35606. To reproduce: Uops: llvm-exegesis -mode=uops -opcode-name=VZEROUPPER Latency: echo -e '#LLVM-EXEGESIS-DEFREG XMM0 1\n#LLVM-EXEGESIS-DEFREG XMM1 1\nvzeroupper' | /tmp/llvm-exegesis -mode=latency -snippets-file=- echo -e '#LLVM-EXEGESIS-DEFREG XMM0 1\n#LLVM-EXEGESIS-DEFREG XMM1 1\nvzeroupper\naddps %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=latency -snippets-file=- Reviewers: RKSimon, craig.topper, andreadb Subscribers: gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D54107 llvm-svn: 346482
2018-11-09 17:49:06 +08:00
; ICELAKE-NEXT: vzeroupper # sched: [0:0.67]
[X86] Add AVX512 VPOPCNTDQ schedule tests Demonstrates how to perform full coverage avx512 schedule tests llvm-svn: 320805
2017-12-15 19:32:31 +08:00
; ICELAKE-NEXT: retq # sched: [7:1.00]
tail call void asm "vpopcntd $1, $0 \0A\09 vpopcntd $1, $0 {$3} \0A\09 vpopcntd $1, $0 {$3} {z} \0A\09 vpopcntd $2, $0 \0A\09 vpopcntd $2, $0 {$3} \0A\09 vpopcntd $2, $0 {$3} {z} \0A\09 vpopcntd $2{1to16}, $0 \0A\09 vpopcntd $2{1to16}, $0 {$3} \0A\09 vpopcntd $2{1to16}, $0 {$3} {z}", "v,v,*m,^Yk"(<16 x i32> %a0, <16 x i32> %a1, <16 x i32> *%a2, i16 %a3) nounwind
ret void
}
define void @test_vpopcntq(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> *%a2, i8 %a3) {
; GENERIC-LABEL: test_vpopcntq:
; GENERIC: # %bb.0:
; GENERIC-NEXT: kmovw %esi, %k1 # sched: [1:0.33]
; GENERIC-NEXT: #APP
[X86] Split WriteVecALU/WritePHAdd into XMM and YMM/ZMM scheduler classes llvm-svn: 331453
2018-05-03 21:27:10 +08:00
; GENERIC-NEXT: vpopcntq %zmm1, %zmm0 # sched: [1:0.50]
; GENERIC-NEXT: vpopcntq %zmm1, %zmm0 {%k1} # sched: [1:0.50]
; GENERIC-NEXT: vpopcntq %zmm1, %zmm0 {%k1} {z} # sched: [1:0.50]
; GENERIC-NEXT: vpopcntq (%rdi), %zmm0 # sched: [8:0.50]
; GENERIC-NEXT: vpopcntq (%rdi), %zmm0 {%k1} # sched: [8:0.50]
; GENERIC-NEXT: vpopcntq (%rdi), %zmm0 {%k1} {z} # sched: [8:0.50]
; GENERIC-NEXT: vpopcntq (%rdi){1to8}, %zmm0 # sched: [8:0.50]
; GENERIC-NEXT: vpopcntq (%rdi){1to8}, %zmm0 {%k1} # sched: [8:0.50]
; GENERIC-NEXT: vpopcntq (%rdi){1to8}, %zmm0 {%k1} {z} # sched: [8:0.50]
[X86] Add AVX512 VPOPCNTDQ schedule tests Demonstrates how to perform full coverage avx512 schedule tests llvm-svn: 320805
2017-12-15 19:32:31 +08:00
; GENERIC-NEXT: #NO_APP
[X86] Fix VZEROUPPER scheduling info on SNB,HSW,BDW,SXL,SKX. Summary: Starting from SNB, VZEROUPPER is handled by the renamer and uses no proc resources. After HSW, it also has zero latency. This fixes PR35606. To reproduce: Uops: llvm-exegesis -mode=uops -opcode-name=VZEROUPPER Latency: echo -e '#LLVM-EXEGESIS-DEFREG XMM0 1\n#LLVM-EXEGESIS-DEFREG XMM1 1\nvzeroupper' | /tmp/llvm-exegesis -mode=latency -snippets-file=- echo -e '#LLVM-EXEGESIS-DEFREG XMM0 1\n#LLVM-EXEGESIS-DEFREG XMM1 1\nvzeroupper\naddps %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=latency -snippets-file=- Reviewers: RKSimon, craig.topper, andreadb Subscribers: gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D54107 llvm-svn: 346482
2018-11-09 17:49:06 +08:00
; GENERIC-NEXT: vzeroupper # sched: [1:1.00]
[X86] Add AVX512 VPOPCNTDQ schedule tests Demonstrates how to perform full coverage avx512 schedule tests llvm-svn: 320805
2017-12-15 19:32:31 +08:00
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; ICELAKE-LABEL: test_vpopcntq:
; ICELAKE: # %bb.0:
; ICELAKE-NEXT: kmovd %esi, %k1 # sched: [1:1.00]
; ICELAKE-NEXT: #APP
[X86] Fix skylake server scheduling info. Summary: This fixes most of the scheduling info for SKX vector operations. I had to split a lot of the YMM/ZMM classes into separate classes for YMM and ZMM. The before/after llvm-exegesis analysis are in the phabricator diff. Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D47721 llvm-svn: 334407
2018-06-11 22:37:53 +08:00
; ICELAKE-NEXT: vpopcntq %zmm1, %zmm0 # sched: [1:1.00]
; ICELAKE-NEXT: vpopcntq %zmm1, %zmm0 {%k1} # sched: [1:1.00]
; ICELAKE-NEXT: vpopcntq %zmm1, %zmm0 {%k1} {z} # sched: [1:1.00]
; ICELAKE-NEXT: vpopcntq (%rdi), %zmm0 # sched: [8:1.00]
; ICELAKE-NEXT: vpopcntq (%rdi), %zmm0 {%k1} # sched: [8:1.00]
; ICELAKE-NEXT: vpopcntq (%rdi), %zmm0 {%k1} {z} # sched: [8:1.00]
; ICELAKE-NEXT: vpopcntq (%rdi){1to8}, %zmm0 # sched: [8:1.00]
; ICELAKE-NEXT: vpopcntq (%rdi){1to8}, %zmm0 {%k1} # sched: [8:1.00]
; ICELAKE-NEXT: vpopcntq (%rdi){1to8}, %zmm0 {%k1} {z} # sched: [8:1.00]
[X86] Add AVX512 VPOPCNTDQ schedule tests Demonstrates how to perform full coverage avx512 schedule tests llvm-svn: 320805
2017-12-15 19:32:31 +08:00
; ICELAKE-NEXT: #NO_APP
[X86] Fix VZEROUPPER scheduling info on SNB,HSW,BDW,SXL,SKX. Summary: Starting from SNB, VZEROUPPER is handled by the renamer and uses no proc resources. After HSW, it also has zero latency. This fixes PR35606. To reproduce: Uops: llvm-exegesis -mode=uops -opcode-name=VZEROUPPER Latency: echo -e '#LLVM-EXEGESIS-DEFREG XMM0 1\n#LLVM-EXEGESIS-DEFREG XMM1 1\nvzeroupper' | /tmp/llvm-exegesis -mode=latency -snippets-file=- echo -e '#LLVM-EXEGESIS-DEFREG XMM0 1\n#LLVM-EXEGESIS-DEFREG XMM1 1\nvzeroupper\naddps %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=latency -snippets-file=- Reviewers: RKSimon, craig.topper, andreadb Subscribers: gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D54107 llvm-svn: 346482
2018-11-09 17:49:06 +08:00
; ICELAKE-NEXT: vzeroupper # sched: [0:0.67]
[X86] Add AVX512 VPOPCNTDQ schedule tests Demonstrates how to perform full coverage avx512 schedule tests llvm-svn: 320805
2017-12-15 19:32:31 +08:00
; ICELAKE-NEXT: retq # sched: [7:1.00]
tail call void asm "vpopcntq $1, $0 \0A\09 vpopcntq $1, $0 {$3} \0A\09 vpopcntq $1, $0 {$3} {z} \0A\09 vpopcntq $2, $0 \0A\09 vpopcntq $2, $0 {$3} \0A\09 vpopcntq $2, $0 {$3} {z} \0A\09 vpopcntq $2{1to8}, $0 \0A\09 vpopcntq $2{1to8}, $0 {$3} \0A\09 vpopcntq $2{1to8}, $0 {$3} {z}", "v,v,*m,^Yk"(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> *%a2, i8 %a3) nounwind
ret void
}