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llvm-project/llvm/lib/Target/AMDGPU/R600Processors.td

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AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-11 04:01:58 +08:00
//===-- R600Processors.td - R600 Processor definitions --------------------===//
//
Update the file headers across all of the LLVM projects in the monorepo to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
2019-01-19 16:50:56 +08:00
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-11 04:01:58 +08:00
//
//===----------------------------------------------------------------------===//
AMDGPU: Separate R600 and GCN TableGen files Summary: We now have two sets of generated TableGen files, one for R600 and one for GCN, so each sub-target now has its own tables of instructions, registers, ISel patterns, etc. This should help reduce compile time since each sub-target now only has to consider information that is specific to itself. This will also help prevent the R600 sub-target from slowing down new features for GCN, like disassembler support, GlobalISel, etc. Reviewers: arsenm, nhaehnle, jvesely Reviewed By: arsenm Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D46365 llvm-svn: 335942
2018-06-29 07:47:12 +08:00
class SubtargetFeatureFetchLimit <string Value> :
SubtargetFeature <"fetch"#Value,
"TexVTXClauseSize",
Value,
"Limit the maximum number of fetches in a clause to "#Value
>;
def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
"R600ALUInst",
"false",
"Older version of ALU instructions encoding"
>;
def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
"HasVertexCache",
"true",
"Specify use of dedicated vertex cache"
>;
def FeatureCaymanISA : SubtargetFeature<"caymanISA",
"CaymanISA",
"true",
"Use Cayman ISA"
>;
def FeatureCFALUBug : SubtargetFeature<"cfalubug",
"CFALUBug",
"true",
"GPU has CF_ALU bug"
>;
AMDGPU: Fix names for generation features We should overall stop using these, but the uppercase name didn't work. Any feature string is converted to lowercase, so these could never be found in the table. llvm-svn: 357541
2019-04-03 08:01:03 +08:00
class R600SubtargetFeatureGeneration <string Value, string FeatureName,
AMDGPU: Separate R600 and GCN TableGen files Summary: We now have two sets of generated TableGen files, one for R600 and one for GCN, so each sub-target now has its own tables of instructions, registers, ISel patterns, etc. This should help reduce compile time since each sub-target now only has to consider information that is specific to itself. This will also help prevent the R600 sub-target from slowing down new features for GCN, like disassembler support, GlobalISel, etc. Reviewers: arsenm, nhaehnle, jvesely Reviewed By: arsenm Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D46365 llvm-svn: 335942
2018-06-29 07:47:12 +08:00
list<SubtargetFeature> Implies> :
AMDGPU: Fix names for generation features We should overall stop using these, but the uppercase name didn't work. Any feature string is converted to lowercase, so these could never be found in the table. llvm-svn: 357541
2019-04-03 08:01:03 +08:00
SubtargetFeatureGeneration <Value, FeatureName, "R600Subtarget", Implies>;
AMDGPU: Separate R600 and GCN TableGen files Summary: We now have two sets of generated TableGen files, one for R600 and one for GCN, so each sub-target now has its own tables of instructions, registers, ISel patterns, etc. This should help reduce compile time since each sub-target now only has to consider information that is specific to itself. This will also help prevent the R600 sub-target from slowing down new features for GCN, like disassembler support, GlobalISel, etc. Reviewers: arsenm, nhaehnle, jvesely Reviewed By: arsenm Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D46365 llvm-svn: 335942
2018-06-29 07:47:12 +08:00
AMDGPU: Fix names for generation features We should overall stop using these, but the uppercase name didn't work. Any feature string is converted to lowercase, so these could never be found in the table. llvm-svn: 357541
2019-04-03 08:01:03 +08:00
def FeatureR600 : R600SubtargetFeatureGeneration<"R600", "r600",
AMDGPU: Separate R600 and GCN TableGen files Summary: We now have two sets of generated TableGen files, one for R600 and one for GCN, so each sub-target now has its own tables of instructions, registers, ISel patterns, etc. This should help reduce compile time since each sub-target now only has to consider information that is specific to itself. This will also help prevent the R600 sub-target from slowing down new features for GCN, like disassembler support, GlobalISel, etc. Reviewers: arsenm, nhaehnle, jvesely Reviewed By: arsenm Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D46365 llvm-svn: 335942
2018-06-29 07:47:12 +08:00
[FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]
>;
AMDGPU: Fix names for generation features We should overall stop using these, but the uppercase name didn't work. Any feature string is converted to lowercase, so these could never be found in the table. llvm-svn: 357541
2019-04-03 08:01:03 +08:00
def FeatureR700 : R600SubtargetFeatureGeneration<"R700", "r700",
AMDGPU: Separate R600 and GCN TableGen files Summary: We now have two sets of generated TableGen files, one for R600 and one for GCN, so each sub-target now has its own tables of instructions, registers, ISel patterns, etc. This should help reduce compile time since each sub-target now only has to consider information that is specific to itself. This will also help prevent the R600 sub-target from slowing down new features for GCN, like disassembler support, GlobalISel, etc. Reviewers: arsenm, nhaehnle, jvesely Reviewed By: arsenm Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D46365 llvm-svn: 335942
2018-06-29 07:47:12 +08:00
[FeatureFetchLimit16, FeatureLocalMemorySize0]
>;
AMDGPU: Fix names for generation features We should overall stop using these, but the uppercase name didn't work. Any feature string is converted to lowercase, so these could never be found in the table. llvm-svn: 357541
2019-04-03 08:01:03 +08:00
def FeatureEvergreen : R600SubtargetFeatureGeneration<"EVERGREEN", "evergreen",
AMDGPU: Separate R600 and GCN TableGen files Summary: We now have two sets of generated TableGen files, one for R600 and one for GCN, so each sub-target now has its own tables of instructions, registers, ISel patterns, etc. This should help reduce compile time since each sub-target now only has to consider information that is specific to itself. This will also help prevent the R600 sub-target from slowing down new features for GCN, like disassembler support, GlobalISel, etc. Reviewers: arsenm, nhaehnle, jvesely Reviewed By: arsenm Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D46365 llvm-svn: 335942
2018-06-29 07:47:12 +08:00
[FeatureFetchLimit16, FeatureLocalMemorySize32768]
>;
def FeatureNorthernIslands : R600SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
AMDGPU: Fix names for generation features We should overall stop using these, but the uppercase name didn't work. Any feature string is converted to lowercase, so these could never be found in the table. llvm-svn: 357541
2019-04-03 08:01:03 +08:00
"northern-islands",
AMDGPU: Separate R600 and GCN TableGen files Summary: We now have two sets of generated TableGen files, one for R600 and one for GCN, so each sub-target now has its own tables of instructions, registers, ISel patterns, etc. This should help reduce compile time since each sub-target now only has to consider information that is specific to itself. This will also help prevent the R600 sub-target from slowing down new features for GCN, like disassembler support, GlobalISel, etc. Reviewers: arsenm, nhaehnle, jvesely Reviewed By: arsenm Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D46365 llvm-svn: 335942
2018-06-29 07:47:12 +08:00
[FeatureFetchLimit16, FeatureWavefrontSize64,
FeatureLocalMemorySize32768]
>;
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-11 04:01:58 +08:00
//===----------------------------------------------------------------------===//
// Radeon HD 2000/3000 Series (R600).
//===----------------------------------------------------------------------===//
def : Processor<"r600", R600_VLIW5_Itin,
[FeatureR600, FeatureWavefrontSize64, FeatureVertexCache]
>;
def : Processor<"r630", R600_VLIW5_Itin,
[FeatureR600, FeatureWavefrontSize32, FeatureVertexCache]
>;
def : Processor<"rs880", R600_VLIW5_Itin,
[FeatureR600, FeatureWavefrontSize16]
>;
def : Processor<"rv670", R600_VLIW5_Itin,
AMDGPU: Disable fp64 support on pre GCN asics It's not implemented. Passing +fp64-fp16-denormal feature enables fp64 even on asics that don't support it v2: fix hasFP64 query Differential Revision: https://reviews.llvm.org/D39931 llvm-svn: 319709
2017-12-05 06:57:29 +08:00
[FeatureR600, FeatureWavefrontSize64, FeatureVertexCache]
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-11 04:01:58 +08:00
>;
//===----------------------------------------------------------------------===//
// Radeon HD 4000 Series (R700).
//===----------------------------------------------------------------------===//
def : Processor<"rv710", R600_VLIW5_Itin,
[FeatureR700, FeatureWavefrontSize32, FeatureVertexCache]
>;
def : Processor<"rv730", R600_VLIW5_Itin,
[FeatureR700, FeatureWavefrontSize32, FeatureVertexCache]
>;
def : Processor<"rv770", R600_VLIW5_Itin,
AMDGPU: Disable fp64 support on pre GCN asics It's not implemented. Passing +fp64-fp16-denormal feature enables fp64 even on asics that don't support it v2: fix hasFP64 query Differential Revision: https://reviews.llvm.org/D39931 llvm-svn: 319709
2017-12-05 06:57:29 +08:00
[FeatureR700, FeatureWavefrontSize64, FeatureVertexCache]
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-11 04:01:58 +08:00
>;
//===----------------------------------------------------------------------===//
// Radeon HD 5000 Series (Evergreen).
//===----------------------------------------------------------------------===//
def : Processor<"cedar", R600_VLIW5_Itin,
[FeatureEvergreen, FeatureWavefrontSize32, FeatureVertexCache,
FeatureCFALUBug]
>;
def : Processor<"cypress", R600_VLIW5_Itin,
AMDGPU/EG: Add a new FeatureFMA and use it to selectively enable FMA instruction Only used by pre-GCN targets v2: fix predicate setting for FMA_Common Differential Revision: https://reviews.llvm.org/D40692 llvm-svn: 319712
2017-12-05 07:07:28 +08:00
[FeatureEvergreen, FeatureWavefrontSize64, FeatureVertexCache, FeatureFMA]
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-11 04:01:58 +08:00
>;
def : Processor<"juniper", R600_VLIW5_Itin,
[FeatureEvergreen, FeatureWavefrontSize64, FeatureVertexCache]
>;
def : Processor<"redwood", R600_VLIW5_Itin,
[FeatureEvergreen, FeatureWavefrontSize64, FeatureVertexCache,
FeatureCFALUBug]
>;
def : Processor<"sumo", R600_VLIW5_Itin,
[FeatureEvergreen, FeatureWavefrontSize64, FeatureCFALUBug]
>;
//===----------------------------------------------------------------------===//
// Radeon HD 6000 Series (Northern Islands).
//===----------------------------------------------------------------------===//
def : Processor<"barts", R600_VLIW5_Itin,
[FeatureNorthernIslands, FeatureVertexCache, FeatureCFALUBug]
>;
def : Processor<"caicos", R600_VLIW5_Itin,
[FeatureNorthernIslands, FeatureCFALUBug]
>;
def : Processor<"cayman", R600_VLIW4_Itin,
AMDGPU/EG: Add a new FeatureFMA and use it to selectively enable FMA instruction Only used by pre-GCN targets v2: fix predicate setting for FMA_Common Differential Revision: https://reviews.llvm.org/D40692 llvm-svn: 319712
2017-12-05 07:07:28 +08:00
[FeatureNorthernIslands, FeatureCaymanISA, FeatureFMA]
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-11 04:01:58 +08:00
>;
def : Processor<"turks", R600_VLIW5_Itin,
[FeatureNorthernIslands, FeatureVertexCache, FeatureCFALUBug]
>;