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llvm-project/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h

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Re-commit AMDGPU/GlobalISel: Add support for simple shaders Fix build when global-isel is disabled and fix a warning. Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP. Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris Differential Revision: https://reviews.llvm.org/D26730 llvm-svn: 293551
2017-01-31 05:56:46 +08:00
//===- AMDGPULegalizerInfo ---------------------------------------*- C++ -*-==//
//
Update the file headers across all of the LLVM projects in the monorepo to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
2019-01-19 16:50:56 +08:00
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
Re-commit AMDGPU/GlobalISel: Add support for simple shaders Fix build when global-isel is disabled and fix a warning. Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP. Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris Differential Revision: https://reviews.llvm.org/D26730 llvm-svn: 293551
2017-01-31 05:56:46 +08:00
//
//===----------------------------------------------------------------------===//
/// \file
/// This file declares the targeting of the Machinelegalizer class for
/// AMDGPU.
/// \todo This should be generated by TableGen.
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H
#define LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H
#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
AMDGPU/GlobalISel: Legalize workitem ID intrinsics Tests don't cover the masked input path since non-kernel arguments aren't lowered yet. Test is copied directly from the existing test, with 2 additions. llvm-svn: 364833
2019-07-02 02:45:36 +08:00
#include "AMDGPUArgumentUsageInfo.h"
AMDGPU/GlobalISel: Legalize G_GLOBAL_VALUE Handle other cases besides LDS. Mostly a straight port of the existing handling, without the intermediate custom nodes. llvm-svn: 373286
2019-10-01 09:06:43 +08:00
#include "SIInstrInfo.h"
Re-commit AMDGPU/GlobalISel: Add support for simple shaders Fix build when global-isel is disabled and fix a warning. Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP. Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris Differential Revision: https://reviews.llvm.org/D26730 llvm-svn: 293551
2017-01-31 05:56:46 +08:00
namespace llvm {
AMDGPU/GlobalISel: Pass subtarget + TM to LegalizerInfo These are the parameters x86 already uses. llvm-svn: 327020
2018-03-09 00:24:16 +08:00
class GCNTargetMachine;
Re-commit AMDGPU/GlobalISel: Add support for simple shaders Fix build when global-isel is disabled and fix a warning. Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP. Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris Differential Revision: https://reviews.llvm.org/D26730 llvm-svn: 293551
2017-01-31 05:56:46 +08:00
class LLVMContext;
AMDGPU: Refactor Subtarget classes Summary: This is a follow-up to r335942. - Merge SISubtarget into AMDGPUSubtarget and rename to GCNSubtarget - Rename AMDGPUCommonSubtarget to AMDGPUSubtarget - Merge R600Subtarget::Generation and GCNSubtarget::Generation into AMDGPUSubtarget::Generation. Reviewers: arsenm, jvesely Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D49037 llvm-svn: 336851
2018-07-12 04:59:01 +08:00
class GCNSubtarget;
Re-commit AMDGPU/GlobalISel: Add support for simple shaders Fix build when global-isel is disabled and fix a warning. Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP. Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris Differential Revision: https://reviews.llvm.org/D26730 llvm-svn: 293551
2017-01-31 05:56:46 +08:00
/// This class provides the information for the target register banks.
class AMDGPULegalizerInfo : public LegalizerInfo {
AMDGPU/GlobalISel: Lower kernarg segment ptr intrinsics llvm-svn: 364835
2019-07-02 02:49:01 +08:00
const GCNSubtarget &ST;
Re-commit AMDGPU/GlobalISel: Add support for simple shaders Fix build when global-isel is disabled and fix a warning. Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP. Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris Differential Revision: https://reviews.llvm.org/D26730 llvm-svn: 293551
2017-01-31 05:56:46 +08:00
public:
AMDGPU: Refactor Subtarget classes Summary: This is a follow-up to r335942. - Merge SISubtarget into AMDGPUSubtarget and rename to GCNSubtarget - Rename AMDGPUCommonSubtarget to AMDGPUSubtarget - Merge R600Subtarget::Generation and GCNSubtarget::Generation into AMDGPUSubtarget::Generation. Reviewers: arsenm, jvesely Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D49037 llvm-svn: 336851
2018-07-12 04:59:01 +08:00
AMDGPULegalizerInfo(const GCNSubtarget &ST,
AMDGPU/GlobalISel: Pass subtarget + TM to LegalizerInfo These are the parameters x86 already uses. llvm-svn: 327020
2018-03-09 00:24:16 +08:00
const GCNTargetMachine &TM);
AMDGPU/GlobalISel: Legalize addrspacecast Use a placeholder constant for now on targets that need the load from the queue ptr. llvm-svn: 353497
2019-02-08 10:40:47 +08:00
bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI,
AMDGPU/GlobalISel: Rename MIRBuilder to B. NFC Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, dstuttard, tpr, t-tye, hiraditya, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67374 llvm-svn: 371467
2019-09-10 07:06:13 +08:00
MachineIRBuilder &B,
AMDGPU/GlobalISel: Legalize addrspacecast Use a placeholder constant for now on targets that need the load from the queue ptr. llvm-svn: 353497
2019-02-08 10:40:47 +08:00
GISelChangeObserver &Observer) const override;
AMDGPU/GlobalISel: Convert to using Register llvm-svn: 364616
2019-06-28 09:16:46 +08:00
Register getSegmentAperture(unsigned AddrSpace,
AMDGPU/GlobalISel: Legalize addrspacecast Use a placeholder constant for now on targets that need the load from the queue ptr. llvm-svn: 353497
2019-02-08 10:40:47 +08:00
MachineRegisterInfo &MRI,
AMDGPU/GlobalISel: Rename MIRBuilder to B. NFC Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, dstuttard, tpr, t-tye, hiraditya, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67374 llvm-svn: 371467
2019-09-10 07:06:13 +08:00
MachineIRBuilder &B) const;
AMDGPU/GlobalISel: Legalize addrspacecast Use a placeholder constant for now on targets that need the load from the queue ptr. llvm-svn: 353497
2019-02-08 10:40:47 +08:00
bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI,
AMDGPU/GlobalISel: Rename MIRBuilder to B. NFC Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, dstuttard, tpr, t-tye, hiraditya, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67374 llvm-svn: 371467
2019-09-10 07:06:13 +08:00
MachineIRBuilder &B) const;
AMDGPU/GlobalISel: Legalize G_FRINT llvm-svn: 361026
2019-05-17 20:19:57 +08:00
bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
AMDGPU/GlobalISel: Rename MIRBuilder to B. NFC Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, dstuttard, tpr, t-tye, hiraditya, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67374 llvm-svn: 371467
2019-09-10 07:06:13 +08:00
MachineIRBuilder &B) const;
AMDGPU/GlobalISel: Legalize G_FCEIL llvm-svn: 361028
2019-05-17 20:20:05 +08:00
bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
AMDGPU/GlobalISel: Rename MIRBuilder to B. NFC Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, dstuttard, tpr, t-tye, hiraditya, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67374 llvm-svn: 371467
2019-09-10 07:06:13 +08:00
MachineIRBuilder &B) const;
AMDGPU/GlobalISel: Legalize G_INTRINSIC_TRUNC llvm-svn: 361027
2019-05-17 20:20:01 +08:00
bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
AMDGPU/GlobalISel: Rename MIRBuilder to B. NFC Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, dstuttard, tpr, t-tye, hiraditya, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67374 llvm-svn: 371467
2019-09-10 07:06:13 +08:00
MachineIRBuilder &B) const;
AMDGPU/GlobalISel: Implement s64->s64 [SU]ITOFP llvm-svn: 361082
2019-05-18 07:05:18 +08:00
bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
AMDGPU/GlobalISel: Rename MIRBuilder to B. NFC Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, dstuttard, tpr, t-tye, hiraditya, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67374 llvm-svn: 371467
2019-09-10 07:06:13 +08:00
MachineIRBuilder &B, bool Signed) const;
AMDGPU/GlobalISel: Handle s64->s64 G_FPTOSI/G_FPTOUI
2020-01-05 05:40:45 +08:00
bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B, bool Signed) const;
GlobalISel: Legalization for G_FMINNUM/G_FMAXNUM llvm-svn: 365658
2019-07-11 00:31:19 +08:00
bool legalizeMinNumMaxNum(MachineInstr &MI, MachineRegisterInfo &MRI,
AMDGPU/GlobalISel: Rename MIRBuilder to B. NFC Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, dstuttard, tpr, t-tye, hiraditya, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67374 llvm-svn: 371467
2019-09-10 07:06:13 +08:00
MachineIRBuilder &B) const;
AMDGPU/GlobalISel: Custom legalize G_EXTRACT_VECTOR_ELT Turn the constant cases into G_EXTRACTs. llvm-svn: 366115
2019-07-16 03:40:59 +08:00
bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
AMDGPU/GlobalISel: Rename MIRBuilder to B. NFC Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, dstuttard, tpr, t-tye, hiraditya, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67374 llvm-svn: 371467
2019-09-10 07:06:13 +08:00
MachineIRBuilder &B) const;
AMDGPU/GlobalISel: Custom legalize G_INSERT_VECTOR_ELT llvm-svn: 366116
2019-07-16 03:43:04 +08:00
bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
AMDGPU/GlobalISel: Rename MIRBuilder to B. NFC Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, dstuttard, tpr, t-tye, hiraditya, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67374 llvm-svn: 371467
2019-09-10 07:06:13 +08:00
MachineIRBuilder &B) const;
AMDGPU/GlobalISel: Custom legalize v2s16 G_SHUFFLE_VECTOR Try to keep simple v2s16 cases as-is. This will more naturally map to how the VOP3P op_sel modifiers work compared to the expansion involving bitcasts and bitshifts. This could maybe try harder with wider source vector types, although that could be handled with a pre-legalize combine.
2020-01-02 04:51:46 +08:00
bool legalizeShuffleVector(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const;
AMDGPU/GlobalISel: Legalize sin/cos llvm-svn: 370402
2019-08-30 04:06:48 +08:00
bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI,
AMDGPU/GlobalISel: Rename MIRBuilder to B. NFC Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, dstuttard, tpr, t-tye, hiraditya, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67374 llvm-svn: 371467
2019-09-10 07:06:13 +08:00
MachineIRBuilder &B) const;
AMDGPU/GlobalISel: Implement LDS G_GLOBAL_VALUE Handle the simple case that lowers to a constant. llvm-svn: 371424
2019-09-10 01:13:44 +08:00
AMDGPU/GlobalISel: Legalize G_GLOBAL_VALUE Handle other cases besides LDS. Mostly a straight port of the existing handling, without the intermediate custom nodes. llvm-svn: 373286
2019-10-01 09:06:43 +08:00
bool buildPCRelGlobalAddress(
Register DstReg, LLT PtrTy, MachineIRBuilder &B, const GlobalValue *GV,
unsigned Offset, unsigned GAFlags = SIInstrInfo::MO_NONE) const;
AMDGPU/GlobalISel: Implement LDS G_GLOBAL_VALUE Handle the simple case that lowers to a constant. llvm-svn: 371424
2019-09-10 01:13:44 +08:00
bool legalizeGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI,
AMDGPU/GlobalISel: Rename MIRBuilder to B. NFC Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, dstuttard, tpr, t-tye, hiraditya, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67374 llvm-svn: 371467
2019-09-10 07:06:13 +08:00
MachineIRBuilder &B) const;
AMDGPU/GlobalISel: Legalize constant 32-bit loads Legalize by casting to a 64-bit constant address. This isn't how the DAG implements it, but it should. llvm-svn: 371535
2019-09-11 00:42:31 +08:00
bool legalizeLoad(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B,
GISelChangeObserver &Observer) const;
AMDGPU/GlobalISel: Custom lower control flow intrinsics Replace the brcond for the 2 cases that act as branches. For now follow how the current system works, although I think we can eventually get rid of the pseudos. llvm-svn: 364832
2019-07-02 02:40:23 +08:00
AMDGPU/GlobalISel: Legalize G_FMAD Unlike SelectionDAG, treat this as a normally legalizable operation. In SelectionDAG this is supposed to only ever formed if it's legal, but I've found that to be restricting. For AMDGPU this is contextually legal depending on whether denormal flushing is allowed in the use function. Technically we currently treat the denormal mode as a subtarget feature, so custom lowering could be avoided. However I consider this to be a defect, and this should be contextually dependent on the controllable rounding mode of the parent function. llvm-svn: 371800
2019-09-13 08:44:35 +08:00
bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const;
AMDGPU/GlobalISel: Handle flat/global G_ATOMIC_CMPXCHG Custom lower this to a target instruction with the merge operands. I think it might be better to directly select this and emit a REG_SEQUENCE, but this would be more work since it would require splitting the tablegen patterns for these cases from the other atomics.
2019-10-09 01:04:41 +08:00
bool legalizeAtomicCmpXChg(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const;
AMDGPU/GlobalISel: Custom lower G_LOG/G_LOG10 I'm pretty sure this is wrong and we should expand these in a correct way, but this matches the existing behavior.
2020-01-22 11:29:30 +08:00
bool legalizeFlog(MachineInstr &MI, MachineIRBuilder &B,
double Log2BaseInverted) const;
AMDGPU/GlobalISel: Custom lower G_FEXP
2020-01-25 09:53:26 +08:00
bool legalizeFExp(MachineInstr &MI, MachineIRBuilder &B) const;
AMDGPU/GlobalISel: Legalize G_FPOW There are few differences from the DAG handling. First, the DAG handling uses a primitive selection pattern instead of custom legalizing it. Because of this, this makes use of source modifiers while the DAG does not. Also instead of promoting f16, try to use the f16 log/exp. There's no f16 fmul_legacy, so widen just for the multiply, although I'm not sure that's the best solution.
2020-02-21 07:59:08 +08:00
bool legalizeFPow(MachineInstr &MI, MachineIRBuilder &B) const;
AMDGPU/GlobalISel: Legalize f64 G_FFLOOR for SI Use cmp ord instead of cmp_class compared to the DAG version for the nan check, but mostly try to match the existsing pattern. I think the sign doesn't matter for fract, so we could do a little better with the source modifier matching. I think this is also still broken as in D22898, but I'm leaving it as-is for now while I don't have an SI system to test on.
2020-01-24 23:01:15 +08:00
bool legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const;
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR If we have s_pack_* instructions, legalize this to G_BUILD_VECTOR_TRUNC from s32 elements. This is closer to how how the s_pack_* instructions really behave. If we don't have s_pack_ instructions, expand this by creating a merge to s32 and bitcasting. This expands to the expected bit operations. I think this eventually should go in a new bitcast legalize action type in LegalizerHelper. We already directly emit the shift operations in RegBankSelect for the vector case. This could possibly be cleaned up, but I also may want to defer doing this expansion to selection anyway. I'll see about that when I try to actually match VOP3P instructions. This breaks the selection of the build_vector since tablegen doesn't know how to match G_BUILD_VECTOR_TRUNC yet, so just xfail it for now.
2020-01-05 04:35:26 +08:00
bool legalizeBuildVector(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const;
AMDGPU/GlobalISel: Custom lower G_FEXP
2020-01-25 09:53:26 +08:00
AMDGPU/GlobalISel: Support llvm.trap and llvm.debugtrap intrinsics Summary: Lower trap and debugtrap intrinsics to AMDGPU machine instruction(s). Reviewers: arsenm, nhaehnle, kerbowa, cdevadas, t-tye, kzhuravl Reviewed By: arsenm Subscribers: kzhuravl, jvesely, wdng, yaxunl, rovka, dstuttard, tpr, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D74688
2020-03-05 10:45:55 +08:00
Register getLiveInRegister(MachineIRBuilder &B, MachineRegisterInfo &MRI,
Register PhyReg, LLT Ty,
bool InsertLiveInCopy = true) const;
Register insertLiveInCopy(MachineIRBuilder &B, MachineRegisterInfo &MRI,
Register LiveIn, Register PhyReg) const;
const ArgDescriptor *
getArgDescriptor(MachineIRBuilder &B,
AMDGPUFunctionArgInfo::PreloadedValue ArgType) const;
AMDGPU/GlobalISel: Legalize workitem ID intrinsics Tests don't cover the masked input path since non-kernel arguments aren't lowered yet. Test is copied directly from the existing test, with 2 additions. llvm-svn: 364833
2019-07-02 02:45:36 +08:00
bool loadInputValue(Register DstReg, MachineIRBuilder &B,
const ArgDescriptor *Arg) const;
bool legalizePreloadedArgIntrin(
MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B,
AMDGPUFunctionArgInfo::PreloadedValue ArgType) const;
AMDGPU/GlobalISel: Custom lower 32-bit G_UDIV/G_UREM AMDGPUCodeGenPrepare expands this most of the time, but not always. We will always at least need a fallback option here. This is the 3rd implementation of the same expansion in the backend. Eventually I would like to eliminate the IR expansion (and the DAG version obviously). Currently the new legalizer path produces a better result, since the IR expansion results in extra operations which need to be combined out. Notably, the IR expansion results in multiplies by 0.
2020-02-12 09:51:02 +08:00
bool legalizeUDIV_UREM(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const;
AMDGPU/GlobalISel: Custom lower 32-bit G_SDIV/G_SREM
2020-02-12 09:48:45 +08:00
void legalizeUDIV_UREM32Impl(MachineIRBuilder &B,
Register DstReg, Register Num, Register Den,
bool IsRem) const;
AMDGPU/GlobalISel: Custom lower 32-bit G_UDIV/G_UREM AMDGPUCodeGenPrepare expands this most of the time, but not always. We will always at least need a fallback option here. This is the 3rd implementation of the same expansion in the backend. Eventually I would like to eliminate the IR expansion (and the DAG version obviously). Currently the new legalizer path produces a better result, since the IR expansion results in extra operations which need to be combined out. Notably, the IR expansion results in multiplies by 0.
2020-02-12 09:51:02 +08:00
bool legalizeUDIV_UREM32(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const;
AMDGPU/GlobalISel: Custom lower 32-bit G_SDIV/G_SREM
2020-02-12 09:48:45 +08:00
bool legalizeSDIV_SREM32(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const;
AMDGPU/GlobalISel: Legalize 64-bit G_UDIV/G_UREM Mostly ported from the DAG version. This results in much worse code than the DAG version, largely due to a much worse expansion for G_UMULH.
2020-02-26 23:17:07 +08:00
bool legalizeUDIV_UREM64(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const;
AMDGPU/GlobalISel: Custom lower 32-bit G_SDIV/G_SREM
2020-02-12 09:48:45 +08:00
bool legalizeSDIV_SREM(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const;
AMDGPU/GlobalISel: Legalize fast unsafe FDIV Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, dstuttard, tpr, t-tye, hiraditya, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69231 llvm-svn: 375460
2019-10-22 06:18:26 +08:00
bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const;
AMDGPU/GlobalISel: Legalize FDIV16 Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, dstuttard, tpr, t-tye, hiraditya, volkan, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69347
2019-10-23 08:39:26 +08:00
bool legalizeFDIV16(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const;
AMDGPU/GlobalISel: Legalize FDIV32 Reviewers: arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, dstuttard, tpr, t-tye, hiraditya, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69581
2019-10-30 00:55:49 +08:00
bool legalizeFDIV32(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const;
AMDGPU/GlobalISel: Legalize FDIV64 Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, dstuttard, tpr, t-tye, hiraditya, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70403
2019-11-18 08:43:59 +08:00
bool legalizeFDIV64(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const;
AMDGPU/GlobalISel: Legalize fast unsafe FDIV Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, dstuttard, tpr, t-tye, hiraditya, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69231 llvm-svn: 375460
2019-10-22 06:18:26 +08:00
bool legalizeFastUnsafeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const;
bool legalizeFDIVFastIntrin(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const;
[AMDGPU/GlobalISel] Add llvm.amdgcn.fdiv.fast legalization. Reviewers: arsenm Reviewed By: arsenm Subscribers: volkan, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, dstuttard, tpr, t-tye, hiraditya, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64966 llvm-svn: 367344
2019-07-31 02:49:16 +08:00
AMDGPU/GlobalISel: Lower kernarg segment ptr intrinsics llvm-svn: 364835
2019-07-02 02:49:01 +08:00
bool legalizeImplicitArgPtr(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const;
AMDGPU: Add intrinsics for address space identification The library currently uses ptrtoint and directly checks the queue ptr for this, which counts as a pointer capture. llvm-svn: 371009
2019-09-05 10:20:39 +08:00
bool legalizeIsAddrSpace(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B, unsigned AddrSpace) const;
Reapply r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics" This reverts r372314, reapplying r372285 and the commits which depend on it (r372286-r372293, and r372296-r372297) This was missing one switch to getTargetConstant in an untested case. llvm-svn: 372338
2019-09-20 00:26:14 +08:00
AMDGPU/GlobalISel: Select llvm.amdgcn.raw.buffer.load Use intermediate instructions, unlike with buffer stores. This is necessary because of the need to have an internal way to distinguish between signed and unsigned extloads. This introduces some duplication and near duplication with the buffer store selection path. The store handling should maybe be moved into legalization to match and eliminate the duplication.
2019-09-19 12:29:20 +08:00
std::tuple<Register, unsigned, unsigned>
splitBufferOffsets(MachineIRBuilder &B, Register OrigOffset) const;
Reapply r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics" This reverts r372314, reapplying r372285 and the commits which depend on it (r372286-r372293, and r372296-r372297) This was missing one switch to getTargetConstant in an untested case. llvm-svn: 372338
2019-09-20 00:26:14 +08:00
Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
Register Reg) const;
bool legalizeRawBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B, bool IsFormat) const;
AMDGPU/GlobalISel: Select llvm.amdgcn.raw.buffer.load Use intermediate instructions, unlike with buffer stores. This is necessary because of the need to have an internal way to distinguish between signed and unsigned extloads. This introduces some duplication and near duplication with the buffer store selection path. The store handling should maybe be moved into legalization to match and eliminate the duplication.
2019-09-19 12:29:20 +08:00
bool legalizeRawBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B, bool IsFormat) const;
AMDGPU/GlobalISel: Move llvm.amdgcn.raw.buffer.store handling Treat this the same way as loads. There's less value to the intermediate nodes, but it's good to be consistent.
2020-01-14 09:39:09 +08:00
Register fixStoreSourceType(MachineIRBuilder &B, Register VData,
bool IsFormat) const;
bool legalizeBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B, bool IsTyped,
bool IsFormat) const;
AMDGPU/GlobalISel: Select llvm.amdgcn.struct.buffer.load
2020-01-14 05:02:14 +08:00
bool legalizeBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI,
AMDGPU/GlobalISel: Move llvm.amdgcn.raw.buffer.store handling Treat this the same way as loads. There's less value to the intermediate nodes, but it's good to be consistent.
2020-01-14 09:39:09 +08:00
MachineIRBuilder &B, bool IsTyped,
bool IsFormat) const;
AMDGPU/GlobalISel: Select buffer atomics The cmpswap handling is incomplete and fails to select.
2020-01-14 12:17:59 +08:00
bool legalizeBufferAtomic(MachineInstr &MI, MachineIRBuilder &B,
Intrinsic::ID IID) const;
AMDGPU/GlobalISel: Select llvm.amdgcn.struct.buffer.load
2020-01-14 05:02:14 +08:00
AMDGPU/GlobalISel: Legalize unpacked d16 image operations On targets that don't have the normal packed f16 layout, handle these during legalization. Directly modify the register types. We can infer this was a d16 load based on the mem operand size during selection. A16 operands should possibly be handled here as well, but don't worry about that yet.
2020-01-16 03:23:20 +08:00
bool legalizeImageIntrinsic(
MachineInstr &MI, MachineIRBuilder &B,
GISelChangeObserver &Observer,
const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr) const;
AMDGPU/GlobalISel: Legalize llvm.amdgcn.s.buffer.load The 96-bit results need to be widened. I find the interaction between LegalizerHelper and MIRBuilder somewhat awkward. The custom legalization is called by the LegalizerHelper, but then does not have access to the helper. You have to construct a new helper, which then does not own the MachineIRBuilder, but does modify it. Maybe custom legalization should be passed the helper?
2020-01-31 06:34:33 +08:00
bool legalizeSBufferLoad(
MachineInstr &MI, MachineIRBuilder &B,
GISelChangeObserver &Observer) const;
AMDGPU/GlobalISel: Handle atomic_inc/atomic_dec The intermediate instruction drops the extra volatile argument. We are missing an atomic ordering on these.
2020-01-18 09:51:01 +08:00
bool legalizeAtomicIncDec(MachineInstr &MI, MachineIRBuilder &B,
bool IsInc) const;
AMDGPU/GlobalISel: Support llvm.trap and llvm.debugtrap intrinsics Summary: Lower trap and debugtrap intrinsics to AMDGPU machine instruction(s). Reviewers: arsenm, nhaehnle, kerbowa, cdevadas, t-tye, kzhuravl Reviewed By: arsenm Subscribers: kzhuravl, jvesely, wdng, yaxunl, rovka, dstuttard, tpr, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D74688
2020-03-05 10:45:55 +08:00
bool legalizeTrapIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const;
bool legalizeDebugTrapIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const;
GlobalISel: Add observer argument to legalizeIntrinsic This is passed to legalizeCustom, but not intrinsic. Also remove the MRI argument, since you can get that from the MachineIRBuilder. I'm not sure why MachineIRBuilder has a private observer member, and this is passed separately.
2020-01-28 04:50:55 +08:00
bool legalizeIntrinsic(MachineInstr &MI, MachineIRBuilder &B,
GISelChangeObserver &Observer) const override;
Re-commit AMDGPU/GlobalISel: Add support for simple shaders Fix build when global-isel is disabled and fix a warning. Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP. Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris Differential Revision: https://reviews.llvm.org/D26730 llvm-svn: 293551
2017-01-31 05:56:46 +08:00
};
} // End llvm namespace.
#endif